1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_P1010 15 #define CONFIG_E500 /* BOOKE e500 family */ 16 #include <asm/config_mpc85xx.h> 17 #define CONFIG_NAND_FSL_IFC 18 19 #ifdef CONFIG_SDCARD 20 #define CONFIG_SPL_MMC_MINIMAL 21 #define CONFIG_SPL_FLUSH_IMAGE 22 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 23 #define CONFIG_FSL_LAW /* Use common FSL init code */ 24 #define CONFIG_SYS_TEXT_BASE 0x11001000 25 #define CONFIG_SPL_TEXT_BASE 0xD0001000 26 #define CONFIG_SPL_PAD_TO 0x18000 27 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 28 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 29 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 30 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 31 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 32 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 33 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 34 #define CONFIG_SPL_MMC_BOOT 35 #ifdef CONFIG_SPL_BUILD 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #endif 38 #endif 39 40 #ifdef CONFIG_SPIFLASH 41 #ifdef CONFIG_SECURE_BOOT 42 #define CONFIG_RAMBOOT_SPIFLASH 43 #define CONFIG_SYS_TEXT_BASE 0x11000000 44 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 45 #else 46 #define CONFIG_SPL_SPI_FLASH_MINIMAL 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 #define CONFIG_SYS_TEXT_BASE 0x11001000 51 #define CONFIG_SPL_TEXT_BASE 0xD0001000 52 #define CONFIG_SPL_PAD_TO 0x18000 53 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 58 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 60 #define CONFIG_SPL_SPI_BOOT 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_COMMON_INIT_DDR 63 #endif 64 #endif 65 #endif 66 67 #ifdef CONFIG_NAND 68 #ifdef CONFIG_SECURE_BOOT 69 #define CONFIG_SPL_INIT_MINIMAL 70 #define CONFIG_SPL_NAND_BOOT 71 #define CONFIG_SPL_FLUSH_IMAGE 72 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 73 74 #define CONFIG_SYS_TEXT_BASE 0x00201000 75 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 76 #define CONFIG_SPL_MAX_SIZE 8192 77 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 78 #define CONFIG_SPL_RELOC_STACK 0x00100000 79 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 80 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 81 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 82 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 84 #else 85 #ifdef CONFIG_TPL_BUILD 86 #define CONFIG_SPL_NAND_BOOT 87 #define CONFIG_SPL_FLUSH_IMAGE 88 #define CONFIG_SPL_NAND_INIT 89 #define CONFIG_SPL_COMMON_INIT_DDR 90 #define CONFIG_SPL_MAX_SIZE (128 << 10) 91 #define CONFIG_SPL_TEXT_BASE 0xD0001000 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 94 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 95 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 96 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 97 #elif defined(CONFIG_SPL_BUILD) 98 #define CONFIG_SPL_INIT_MINIMAL 99 #define CONFIG_SPL_NAND_MINIMAL 100 #define CONFIG_SPL_FLUSH_IMAGE 101 #define CONFIG_SPL_TEXT_BASE 0xff800000 102 #define CONFIG_SPL_MAX_SIZE 8192 103 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 104 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 105 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 106 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 107 #endif 108 #define CONFIG_SPL_PAD_TO 0x20000 109 #define CONFIG_TPL_PAD_TO 0x20000 110 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 111 #define CONFIG_SYS_TEXT_BASE 0x11001000 112 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 113 #endif 114 #endif 115 116 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 117 #define CONFIG_RAMBOOT_NAND 118 #define CONFIG_SYS_TEXT_BASE 0x11000000 119 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 120 #endif 121 122 #ifndef CONFIG_SYS_TEXT_BASE 123 #define CONFIG_SYS_TEXT_BASE 0xeff40000 124 #endif 125 126 #ifndef CONFIG_RESET_VECTOR_ADDRESS 127 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 128 #endif 129 130 #ifdef CONFIG_SPL_BUILD 131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 132 #else 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 134 #endif 135 136 /* High Level Configuration Options */ 137 #define CONFIG_BOOKE /* BOOKE */ 138 #define CONFIG_E500 /* BOOKE e500 family */ 139 #define CONFIG_FSL_IFC /* Enable IFC Support */ 140 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 141 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 142 143 #define CONFIG_PCI /* Enable PCI/PCIE */ 144 #if defined(CONFIG_PCI) 145 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 146 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 147 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 148 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 149 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 150 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 151 152 #define CONFIG_CMD_PCI 153 154 /* 155 * PCI Windows 156 * Memory space is mapped 1-1, but I/O space must start from 0. 157 */ 158 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 159 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 160 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 161 #ifdef CONFIG_PHYS_64BIT 162 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 163 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 164 #else 165 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 166 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 167 #endif 168 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 169 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 170 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 171 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 172 #ifdef CONFIG_PHYS_64BIT 173 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 174 #else 175 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 176 #endif 177 178 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 179 #if defined(CONFIG_P1010RDB_PA) 180 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 181 #elif defined(CONFIG_P1010RDB_PB) 182 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 183 #endif 184 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 185 #ifdef CONFIG_PHYS_64BIT 186 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 187 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 188 #else 189 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 190 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 191 #endif 192 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 193 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 194 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 195 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 196 #ifdef CONFIG_PHYS_64BIT 197 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 198 #else 199 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 200 #endif 201 202 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 203 204 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 205 #define CONFIG_DOS_PARTITION 206 #endif 207 208 #define CONFIG_FSL_LAW /* Use common FSL init code */ 209 #define CONFIG_TSEC_ENET 210 #define CONFIG_ENV_OVERWRITE 211 212 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 213 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 214 215 #define CONFIG_MISC_INIT_R 216 #define CONFIG_HWCONFIG 217 /* 218 * These can be toggled for performance analysis, otherwise use default. 219 */ 220 #define CONFIG_L2_CACHE /* toggle L2 cache */ 221 #define CONFIG_BTB /* toggle branch predition */ 222 223 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 224 225 #define CONFIG_ENABLE_36BIT_PHYS 226 227 #ifdef CONFIG_PHYS_64BIT 228 #define CONFIG_ADDR_MAP 1 229 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 230 #endif 231 232 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 233 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 234 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 235 236 /* DDR Setup */ 237 #define CONFIG_SYS_FSL_DDR3 238 #define CONFIG_SYS_DDR_RAW_TIMING 239 #define CONFIG_DDR_SPD 240 #define CONFIG_SYS_SPD_BUS_NUM 1 241 #define SPD_EEPROM_ADDRESS 0x52 242 243 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 244 245 #ifndef __ASSEMBLY__ 246 extern unsigned long get_sdram_size(void); 247 #endif 248 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 249 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 250 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 251 252 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 253 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 254 255 /* DDR3 Controller Settings */ 256 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 257 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 258 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 259 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 260 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 261 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 262 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 263 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 264 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 265 #define CONFIG_SYS_DDR_RCW_1 0x00000000 266 #define CONFIG_SYS_DDR_RCW_2 0x00000000 267 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 268 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 269 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 270 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 271 272 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 273 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 274 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 275 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 276 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 277 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 278 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 279 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 280 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 281 282 /* settings for DDR3 at 667MT/s */ 283 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 284 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 285 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 286 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 287 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 288 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 289 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 290 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 291 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 292 293 #define CONFIG_SYS_CCSRBAR 0xffe00000 294 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 295 296 /* Don't relocate CCSRBAR while in NAND_SPL */ 297 #ifdef CONFIG_SPL_BUILD 298 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 299 #endif 300 301 /* 302 * Memory map 303 * 304 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 305 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 306 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 307 * 308 * Localbus non-cacheable 309 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 310 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 311 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 312 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 313 */ 314 315 /* 316 * IFC Definitions 317 */ 318 /* NOR Flash on IFC */ 319 #ifdef CONFIG_SPL_BUILD 320 #define CONFIG_SYS_NO_FLASH 321 #endif 322 323 #define CONFIG_SYS_FLASH_BASE 0xee000000 324 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 325 326 #ifdef CONFIG_PHYS_64BIT 327 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 328 #else 329 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 330 #endif 331 332 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 333 CSPR_PORT_SIZE_16 | \ 334 CSPR_MSEL_NOR | \ 335 CSPR_V) 336 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 337 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 338 /* NOR Flash Timing Params */ 339 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 340 FTIM0_NOR_TEADC(0x5) | \ 341 FTIM0_NOR_TEAHC(0x5) 342 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 343 FTIM1_NOR_TRAD_NOR(0x0f) 344 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 345 FTIM2_NOR_TCH(0x4) | \ 346 FTIM2_NOR_TWP(0x1c) 347 #define CONFIG_SYS_NOR_FTIM3 0x0 348 349 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 350 #define CONFIG_SYS_FLASH_QUIET_TEST 351 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 352 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 353 354 #undef CONFIG_SYS_FLASH_CHECKSUM 355 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 356 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 357 358 /* CFI for NOR Flash */ 359 #define CONFIG_FLASH_CFI_DRIVER 360 #define CONFIG_SYS_FLASH_CFI 361 #define CONFIG_SYS_FLASH_EMPTY_INFO 362 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 363 364 /* NAND Flash on IFC */ 365 #define CONFIG_SYS_NAND_BASE 0xff800000 366 #ifdef CONFIG_PHYS_64BIT 367 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 368 #else 369 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 370 #endif 371 372 #define CONFIG_MTD_DEVICE 373 #define CONFIG_MTD_PARTITION 374 #define CONFIG_CMD_MTDPARTS 375 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 376 #define MTDPARTS_DEFAULT \ 377 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 378 379 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 380 | CSPR_PORT_SIZE_8 \ 381 | CSPR_MSEL_NAND \ 382 | CSPR_V) 383 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 384 385 #if defined(CONFIG_P1010RDB_PA) 386 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 387 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 388 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 389 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 390 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 391 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 392 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 393 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 394 395 #elif defined(CONFIG_P1010RDB_PB) 396 #define CONFIG_SYS_NAND_ONFI_DETECTION 397 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 398 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 399 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 400 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 401 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 402 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 403 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 404 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 405 #endif 406 407 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 408 #define CONFIG_SYS_MAX_NAND_DEVICE 1 409 #define CONFIG_CMD_NAND 410 411 #if defined(CONFIG_P1010RDB_PA) 412 /* NAND Flash Timing Params */ 413 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 414 FTIM0_NAND_TWP(0x0C) | \ 415 FTIM0_NAND_TWCHT(0x04) | \ 416 FTIM0_NAND_TWH(0x05) 417 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 418 FTIM1_NAND_TWBE(0x1d) | \ 419 FTIM1_NAND_TRR(0x07) | \ 420 FTIM1_NAND_TRP(0x0c) 421 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 422 FTIM2_NAND_TREH(0x05) | \ 423 FTIM2_NAND_TWHRE(0x0f) 424 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 425 426 #elif defined(CONFIG_P1010RDB_PB) 427 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 428 /* ONFI NAND Flash mode0 Timing Params */ 429 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 430 FTIM0_NAND_TWP(0x18) | \ 431 FTIM0_NAND_TWCHT(0x07) | \ 432 FTIM0_NAND_TWH(0x0a)) 433 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 434 FTIM1_NAND_TWBE(0x39) | \ 435 FTIM1_NAND_TRR(0x0e) | \ 436 FTIM1_NAND_TRP(0x18)) 437 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 438 FTIM2_NAND_TREH(0x0a) | \ 439 FTIM2_NAND_TWHRE(0x1e)) 440 #define CONFIG_SYS_NAND_FTIM3 0x0 441 #endif 442 443 #define CONFIG_SYS_NAND_DDR_LAW 11 444 445 /* Set up IFC registers for boot location NOR/NAND */ 446 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 447 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 448 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 449 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 450 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 451 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 452 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 453 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 454 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 455 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 456 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 457 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 458 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 459 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 460 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 461 #else 462 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 463 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 464 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 465 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 466 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 467 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 468 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 469 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 470 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 471 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 472 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 473 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 474 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 475 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 476 #endif 477 478 /* CPLD on IFC */ 479 #define CONFIG_SYS_CPLD_BASE 0xffb00000 480 481 #ifdef CONFIG_PHYS_64BIT 482 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 483 #else 484 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 485 #endif 486 487 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 488 | CSPR_PORT_SIZE_8 \ 489 | CSPR_MSEL_GPCM \ 490 | CSPR_V) 491 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 492 #define CONFIG_SYS_CSOR3 0x0 493 /* CPLD Timing parameters for IFC CS3 */ 494 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 495 FTIM0_GPCM_TEADC(0x0e) | \ 496 FTIM0_GPCM_TEAHC(0x0e)) 497 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 498 FTIM1_GPCM_TRAD(0x1f)) 499 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 500 FTIM2_GPCM_TCH(0x8) | \ 501 FTIM2_GPCM_TWP(0x1f)) 502 #define CONFIG_SYS_CS3_FTIM3 0x0 503 504 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 505 defined(CONFIG_RAMBOOT_NAND) 506 #define CONFIG_SYS_RAMBOOT 507 #define CONFIG_SYS_EXTRA_ENV_RELOC 508 #else 509 #undef CONFIG_SYS_RAMBOOT 510 #endif 511 512 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 513 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 514 #define CONFIG_A003399_NOR_WORKAROUND 515 #endif 516 #endif 517 518 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 519 #define CONFIG_BOARD_EARLY_INIT_R 520 521 #define CONFIG_SYS_INIT_RAM_LOCK 522 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 523 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 524 525 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 526 - GENERATED_GBL_DATA_SIZE) 527 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 528 529 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 530 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 531 532 /* 533 * Config the L2 Cache as L2 SRAM 534 */ 535 #if defined(CONFIG_SPL_BUILD) 536 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 537 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 538 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 539 #define CONFIG_SYS_L2_SIZE (256 << 10) 540 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 541 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 542 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 543 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 544 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 545 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 546 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 547 #elif defined(CONFIG_NAND) 548 #ifdef CONFIG_TPL_BUILD 549 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 550 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 551 #define CONFIG_SYS_L2_SIZE (256 << 10) 552 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 553 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 554 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 555 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 556 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 557 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 558 #else 559 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 560 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 561 #define CONFIG_SYS_L2_SIZE (256 << 10) 562 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 563 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 564 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 565 #endif 566 #endif 567 #endif 568 569 /* Serial Port */ 570 #define CONFIG_CONS_INDEX 1 571 #undef CONFIG_SERIAL_SOFTWARE_FIFO 572 #define CONFIG_SYS_NS16550_SERIAL 573 #define CONFIG_SYS_NS16550_REG_SIZE 1 574 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 575 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 576 #define CONFIG_NS16550_MIN_FUNCTIONS 577 #endif 578 579 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 580 581 #define CONFIG_SYS_BAUDRATE_TABLE \ 582 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 583 584 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 585 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 586 587 /* I2C */ 588 #define CONFIG_SYS_I2C 589 #define CONFIG_SYS_I2C_FSL 590 #define CONFIG_SYS_FSL_I2C_SPEED 400000 591 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 592 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 593 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 594 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 595 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 596 #define I2C_PCA9557_ADDR1 0x18 597 #define I2C_PCA9557_ADDR2 0x19 598 #define I2C_PCA9557_BUS_NUM 0 599 600 /* I2C EEPROM */ 601 #if defined(CONFIG_P1010RDB_PB) 602 #define CONFIG_ID_EEPROM 603 #ifdef CONFIG_ID_EEPROM 604 #define CONFIG_SYS_I2C_EEPROM_NXID 605 #endif 606 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 607 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 608 #define CONFIG_SYS_EEPROM_BUS_NUM 0 609 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 610 #endif 611 /* enable read and write access to EEPROM */ 612 #define CONFIG_CMD_EEPROM 613 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 614 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 615 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 616 617 /* RTC */ 618 #define CONFIG_RTC_PT7C4338 619 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 620 621 /* 622 * SPI interface will not be available in case of NAND boot SPI CS0 will be 623 * used for SLIC 624 */ 625 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 626 /* eSPI - Enhanced SPI */ 627 #define CONFIG_SF_DEFAULT_SPEED 10000000 628 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 629 #endif 630 631 #if defined(CONFIG_TSEC_ENET) 632 #define CONFIG_MII /* MII PHY management */ 633 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 634 #define CONFIG_TSEC1 1 635 #define CONFIG_TSEC1_NAME "eTSEC1" 636 #define CONFIG_TSEC2 1 637 #define CONFIG_TSEC2_NAME "eTSEC2" 638 #define CONFIG_TSEC3 1 639 #define CONFIG_TSEC3_NAME "eTSEC3" 640 641 #define TSEC1_PHY_ADDR 1 642 #define TSEC2_PHY_ADDR 0 643 #define TSEC3_PHY_ADDR 2 644 645 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 646 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 647 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 648 649 #define TSEC1_PHYIDX 0 650 #define TSEC2_PHYIDX 0 651 #define TSEC3_PHYIDX 0 652 653 #define CONFIG_ETHPRIME "eTSEC1" 654 655 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 656 657 /* TBI PHY configuration for SGMII mode */ 658 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 659 TBICR_PHY_RESET \ 660 | TBICR_ANEG_ENABLE \ 661 | TBICR_FULL_DUPLEX \ 662 | TBICR_SPEED1_SET \ 663 ) 664 665 #endif /* CONFIG_TSEC_ENET */ 666 667 /* SATA */ 668 #define CONFIG_FSL_SATA 669 #define CONFIG_FSL_SATA_V2 670 #define CONFIG_LIBATA 671 672 #ifdef CONFIG_FSL_SATA 673 #define CONFIG_SYS_SATA_MAX_DEVICE 2 674 #define CONFIG_SATA1 675 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 676 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 677 #define CONFIG_SATA2 678 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 679 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 680 681 #define CONFIG_CMD_SATA 682 #define CONFIG_LBA48 683 #endif /* #ifdef CONFIG_FSL_SATA */ 684 685 #define CONFIG_MMC 686 #ifdef CONFIG_MMC 687 #define CONFIG_DOS_PARTITION 688 #define CONFIG_FSL_ESDHC 689 #define CONFIG_GENERIC_MMC 690 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 691 #endif 692 693 #define CONFIG_HAS_FSL_DR_USB 694 695 #if defined(CONFIG_HAS_FSL_DR_USB) 696 #define CONFIG_USB_EHCI 697 698 #ifdef CONFIG_USB_EHCI 699 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 700 #define CONFIG_USB_EHCI_FSL 701 #endif 702 #endif 703 704 /* 705 * Environment 706 */ 707 #if defined(CONFIG_SDCARD) 708 #define CONFIG_ENV_IS_IN_MMC 709 #define CONFIG_FSL_FIXED_MMC_LOCATION 710 #define CONFIG_SYS_MMC_ENV_DEV 0 711 #define CONFIG_ENV_SIZE 0x2000 712 #elif defined(CONFIG_SPIFLASH) 713 #define CONFIG_ENV_IS_IN_SPI_FLASH 714 #define CONFIG_ENV_SPI_BUS 0 715 #define CONFIG_ENV_SPI_CS 0 716 #define CONFIG_ENV_SPI_MAX_HZ 10000000 717 #define CONFIG_ENV_SPI_MODE 0 718 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 719 #define CONFIG_ENV_SECT_SIZE 0x10000 720 #define CONFIG_ENV_SIZE 0x2000 721 #elif defined(CONFIG_NAND) 722 #define CONFIG_ENV_IS_IN_NAND 723 #ifdef CONFIG_TPL_BUILD 724 #define CONFIG_ENV_SIZE 0x2000 725 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 726 #else 727 #if defined(CONFIG_P1010RDB_PA) 728 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 729 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 730 #elif defined(CONFIG_P1010RDB_PB) 731 #define CONFIG_ENV_SIZE (16 * 1024) 732 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 733 #endif 734 #endif 735 #define CONFIG_ENV_OFFSET (1024 * 1024) 736 #elif defined(CONFIG_SYS_RAMBOOT) 737 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 738 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 739 #define CONFIG_ENV_SIZE 0x2000 740 #else 741 #define CONFIG_ENV_IS_IN_FLASH 742 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 743 #define CONFIG_ENV_SIZE 0x2000 744 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 745 #endif 746 747 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 748 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 749 750 /* 751 * Command line configuration. 752 */ 753 #define CONFIG_CMD_DATE 754 #define CONFIG_CMD_ERRATA 755 #define CONFIG_CMD_IRQ 756 #define CONFIG_CMD_REGINFO 757 758 #undef CONFIG_WATCHDOG /* watchdog disabled */ 759 760 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 761 || defined(CONFIG_FSL_SATA) 762 #define CONFIG_DOS_PARTITION 763 #endif 764 765 /* Hash command with SHA acceleration supported in hardware */ 766 #ifdef CONFIG_FSL_CAAM 767 #define CONFIG_CMD_HASH 768 #define CONFIG_SHA_HW_ACCEL 769 #endif 770 771 /* 772 * Miscellaneous configurable options 773 */ 774 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 775 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 776 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 777 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 778 779 #if defined(CONFIG_CMD_KGDB) 780 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 781 #else 782 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 783 #endif 784 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 785 /* Print Buffer Size */ 786 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 787 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 788 789 /* 790 * For booting Linux, the board info and command line data 791 * have to be in the first 64 MB of memory, since this is 792 * the maximum mapped by the Linux kernel during initialization. 793 */ 794 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 795 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 796 797 #if defined(CONFIG_CMD_KGDB) 798 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 799 #endif 800 801 /* 802 * Environment Configuration 803 */ 804 805 #if defined(CONFIG_TSEC_ENET) 806 #define CONFIG_HAS_ETH0 807 #define CONFIG_HAS_ETH1 808 #define CONFIG_HAS_ETH2 809 #endif 810 811 #define CONFIG_ROOTPATH "/opt/nfsroot" 812 #define CONFIG_BOOTFILE "uImage" 813 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 814 815 /* default location for tftp and bootm */ 816 #define CONFIG_LOADADDR 1000000 817 818 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 819 820 #define CONFIG_BAUDRATE 115200 821 822 #define CONFIG_EXTRA_ENV_SETTINGS \ 823 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 824 "netdev=eth0\0" \ 825 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 826 "loadaddr=1000000\0" \ 827 "consoledev=ttyS0\0" \ 828 "ramdiskaddr=2000000\0" \ 829 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 830 "fdtaddr=1e00000\0" \ 831 "fdtfile=p1010rdb.dtb\0" \ 832 "bdev=sda1\0" \ 833 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 834 "othbootargs=ramdisk_size=600000\0" \ 835 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 836 "console=$consoledev,$baudrate $othbootargs; " \ 837 "usb start;" \ 838 "fatload usb 0:2 $loadaddr $bootfile;" \ 839 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 840 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 841 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 842 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 843 "console=$consoledev,$baudrate $othbootargs; " \ 844 "usb start;" \ 845 "ext2load usb 0:4 $loadaddr $bootfile;" \ 846 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 847 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 848 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 849 CONFIG_BOOTMODE 850 851 #if defined(CONFIG_P1010RDB_PA) 852 #define CONFIG_BOOTMODE \ 853 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 854 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 855 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 856 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 857 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 858 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 859 860 #elif defined(CONFIG_P1010RDB_PB) 861 #define CONFIG_BOOTMODE \ 862 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 863 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 864 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 865 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 866 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 867 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 868 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 869 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 870 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 871 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 872 #endif 873 874 #define CONFIG_RAMBOOTCOMMAND \ 875 "setenv bootargs root=/dev/ram rw " \ 876 "console=$consoledev,$baudrate $othbootargs; " \ 877 "tftp $ramdiskaddr $ramdiskfile;" \ 878 "tftp $loadaddr $bootfile;" \ 879 "tftp $fdtaddr $fdtfile;" \ 880 "bootm $loadaddr $ramdiskaddr $fdtaddr" 881 882 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 883 884 #include <asm/fsl_secure_boot.h> 885 886 #endif /* __CONFIG_H */ 887