1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/config_mpc85xx.h> 15 #define CONFIG_NAND_FSL_IFC 16 17 #ifdef CONFIG_SDCARD 18 #define CONFIG_SPL_MMC_MINIMAL 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 21 #define CONFIG_SYS_TEXT_BASE 0x11001000 22 #define CONFIG_SPL_TEXT_BASE 0xD0001000 23 #define CONFIG_SPL_PAD_TO 0x18000 24 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 25 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 31 #define CONFIG_SPL_MMC_BOOT 32 #ifdef CONFIG_SPL_BUILD 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #endif 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #ifdef CONFIG_SECURE_BOOT 39 #define CONFIG_RAMBOOT_SPIFLASH 40 #define CONFIG_SYS_TEXT_BASE 0x11000000 41 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 42 #else 43 #define CONFIG_SPL_SPI_FLASH_MINIMAL 44 #define CONFIG_SPL_FLUSH_IMAGE 45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 46 #define CONFIG_SYS_TEXT_BASE 0x11001000 47 #define CONFIG_SPL_TEXT_BASE 0xD0001000 48 #define CONFIG_SPL_PAD_TO 0x18000 49 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 56 #define CONFIG_SPL_SPI_BOOT 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #endif 60 #endif 61 #endif 62 63 #ifdef CONFIG_NAND 64 #ifdef CONFIG_SECURE_BOOT 65 #define CONFIG_SPL_INIT_MINIMAL 66 #define CONFIG_SPL_NAND_BOOT 67 #define CONFIG_SPL_FLUSH_IMAGE 68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 69 70 #define CONFIG_SYS_TEXT_BASE 0x00201000 71 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 72 #define CONFIG_SPL_MAX_SIZE 8192 73 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 74 #define CONFIG_SPL_RELOC_STACK 0x00100000 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 76 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 77 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 78 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 80 #else 81 #ifdef CONFIG_TPL_BUILD 82 #define CONFIG_SPL_NAND_BOOT 83 #define CONFIG_SPL_FLUSH_IMAGE 84 #define CONFIG_SPL_NAND_INIT 85 #define CONFIG_SPL_COMMON_INIT_DDR 86 #define CONFIG_SPL_MAX_SIZE (128 << 10) 87 #define CONFIG_SPL_TEXT_BASE 0xD0001000 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 90 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 91 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 92 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 93 #elif defined(CONFIG_SPL_BUILD) 94 #define CONFIG_SPL_INIT_MINIMAL 95 #define CONFIG_SPL_NAND_MINIMAL 96 #define CONFIG_SPL_FLUSH_IMAGE 97 #define CONFIG_SPL_TEXT_BASE 0xff800000 98 #define CONFIG_SPL_MAX_SIZE 8192 99 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 100 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 101 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 103 #endif 104 #define CONFIG_SPL_PAD_TO 0x20000 105 #define CONFIG_TPL_PAD_TO 0x20000 106 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 107 #define CONFIG_SYS_TEXT_BASE 0x11001000 108 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 109 #endif 110 #endif 111 112 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 113 #define CONFIG_RAMBOOT_NAND 114 #define CONFIG_SYS_TEXT_BASE 0x11000000 115 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 116 #endif 117 118 #ifndef CONFIG_SYS_TEXT_BASE 119 #define CONFIG_SYS_TEXT_BASE 0xeff40000 120 #endif 121 122 #ifndef CONFIG_RESET_VECTOR_ADDRESS 123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 124 #endif 125 126 #ifdef CONFIG_SPL_BUILD 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 128 #else 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 #endif 131 132 /* High Level Configuration Options */ 133 #define CONFIG_FSL_IFC /* Enable IFC Support */ 134 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 135 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 136 137 #if defined(CONFIG_PCI) 138 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 139 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 140 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 141 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 142 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 143 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 144 145 #define CONFIG_CMD_PCI 146 147 /* 148 * PCI Windows 149 * Memory space is mapped 1-1, but I/O space must start from 0. 150 */ 151 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 152 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 153 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 156 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 157 #else 158 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 159 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 160 #endif 161 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 162 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 163 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 164 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 167 #else 168 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 169 #endif 170 171 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 172 #if defined(CONFIG_TARGET_P1010RDB_PA) 173 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 174 #elif defined(CONFIG_TARGET_P1010RDB_PB) 175 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 176 #endif 177 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 178 #ifdef CONFIG_PHYS_64BIT 179 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 180 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 181 #else 182 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 183 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 184 #endif 185 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 186 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 187 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 188 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 189 #ifdef CONFIG_PHYS_64BIT 190 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 191 #else 192 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 193 #endif 194 195 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 196 #endif 197 198 #define CONFIG_TSEC_ENET 199 #define CONFIG_ENV_OVERWRITE 200 201 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 202 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 203 204 #define CONFIG_MISC_INIT_R 205 #define CONFIG_HWCONFIG 206 /* 207 * These can be toggled for performance analysis, otherwise use default. 208 */ 209 #define CONFIG_L2_CACHE /* toggle L2 cache */ 210 #define CONFIG_BTB /* toggle branch predition */ 211 212 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 213 214 #define CONFIG_ENABLE_36BIT_PHYS 215 216 #ifdef CONFIG_PHYS_64BIT 217 #define CONFIG_ADDR_MAP 1 218 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 219 #endif 220 221 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 222 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 223 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 224 225 /* DDR Setup */ 226 #define CONFIG_SYS_DDR_RAW_TIMING 227 #define CONFIG_DDR_SPD 228 #define CONFIG_SYS_SPD_BUS_NUM 1 229 #define SPD_EEPROM_ADDRESS 0x52 230 231 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 232 233 #ifndef __ASSEMBLY__ 234 extern unsigned long get_sdram_size(void); 235 #endif 236 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 237 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 238 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 239 240 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 241 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 242 243 /* DDR3 Controller Settings */ 244 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 245 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 246 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 247 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 248 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 249 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 250 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 251 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 252 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 253 #define CONFIG_SYS_DDR_RCW_1 0x00000000 254 #define CONFIG_SYS_DDR_RCW_2 0x00000000 255 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 256 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 257 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 258 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 259 260 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 261 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 262 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 263 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 264 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 265 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 266 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 267 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 268 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 269 270 /* settings for DDR3 at 667MT/s */ 271 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 272 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 273 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 274 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 275 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 276 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 277 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 278 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 279 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 280 281 #define CONFIG_SYS_CCSRBAR 0xffe00000 282 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 283 284 /* Don't relocate CCSRBAR while in NAND_SPL */ 285 #ifdef CONFIG_SPL_BUILD 286 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 287 #endif 288 289 /* 290 * Memory map 291 * 292 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 293 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 294 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 295 * 296 * Localbus non-cacheable 297 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 298 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 299 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 300 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 301 */ 302 303 /* 304 * IFC Definitions 305 */ 306 /* NOR Flash on IFC */ 307 #ifdef CONFIG_SPL_BUILD 308 #define CONFIG_SYS_NO_FLASH 309 #endif 310 311 #define CONFIG_SYS_FLASH_BASE 0xee000000 312 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 313 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 316 #else 317 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 318 #endif 319 320 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 321 CSPR_PORT_SIZE_16 | \ 322 CSPR_MSEL_NOR | \ 323 CSPR_V) 324 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 325 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 326 /* NOR Flash Timing Params */ 327 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 328 FTIM0_NOR_TEADC(0x5) | \ 329 FTIM0_NOR_TEAHC(0x5) 330 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 331 FTIM1_NOR_TRAD_NOR(0x0f) 332 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 333 FTIM2_NOR_TCH(0x4) | \ 334 FTIM2_NOR_TWP(0x1c) 335 #define CONFIG_SYS_NOR_FTIM3 0x0 336 337 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 338 #define CONFIG_SYS_FLASH_QUIET_TEST 339 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 340 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 341 342 #undef CONFIG_SYS_FLASH_CHECKSUM 343 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 344 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 345 346 /* CFI for NOR Flash */ 347 #define CONFIG_FLASH_CFI_DRIVER 348 #define CONFIG_SYS_FLASH_CFI 349 #define CONFIG_SYS_FLASH_EMPTY_INFO 350 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 351 352 /* NAND Flash on IFC */ 353 #define CONFIG_SYS_NAND_BASE 0xff800000 354 #ifdef CONFIG_PHYS_64BIT 355 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 356 #else 357 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 358 #endif 359 360 #define CONFIG_MTD_DEVICE 361 #define CONFIG_MTD_PARTITION 362 #define CONFIG_CMD_MTDPARTS 363 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 364 #define MTDPARTS_DEFAULT \ 365 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 366 367 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 368 | CSPR_PORT_SIZE_8 \ 369 | CSPR_MSEL_NAND \ 370 | CSPR_V) 371 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 372 373 #if defined(CONFIG_TARGET_P1010RDB_PA) 374 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 375 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 376 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 377 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 378 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 379 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 380 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 381 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 382 383 #elif defined(CONFIG_TARGET_P1010RDB_PB) 384 #define CONFIG_SYS_NAND_ONFI_DETECTION 385 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 386 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 387 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 388 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 389 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 390 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 391 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 392 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 393 #endif 394 395 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 396 #define CONFIG_SYS_MAX_NAND_DEVICE 1 397 #define CONFIG_CMD_NAND 398 399 #if defined(CONFIG_TARGET_P1010RDB_PA) 400 /* NAND Flash Timing Params */ 401 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 402 FTIM0_NAND_TWP(0x0C) | \ 403 FTIM0_NAND_TWCHT(0x04) | \ 404 FTIM0_NAND_TWH(0x05) 405 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 406 FTIM1_NAND_TWBE(0x1d) | \ 407 FTIM1_NAND_TRR(0x07) | \ 408 FTIM1_NAND_TRP(0x0c) 409 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 410 FTIM2_NAND_TREH(0x05) | \ 411 FTIM2_NAND_TWHRE(0x0f) 412 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 413 414 #elif defined(CONFIG_TARGET_P1010RDB_PB) 415 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 416 /* ONFI NAND Flash mode0 Timing Params */ 417 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 418 FTIM0_NAND_TWP(0x18) | \ 419 FTIM0_NAND_TWCHT(0x07) | \ 420 FTIM0_NAND_TWH(0x0a)) 421 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 422 FTIM1_NAND_TWBE(0x39) | \ 423 FTIM1_NAND_TRR(0x0e) | \ 424 FTIM1_NAND_TRP(0x18)) 425 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 426 FTIM2_NAND_TREH(0x0a) | \ 427 FTIM2_NAND_TWHRE(0x1e)) 428 #define CONFIG_SYS_NAND_FTIM3 0x0 429 #endif 430 431 #define CONFIG_SYS_NAND_DDR_LAW 11 432 433 /* Set up IFC registers for boot location NOR/NAND */ 434 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 435 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 436 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 437 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 438 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 439 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 440 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 441 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 442 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 443 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 444 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 445 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 446 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 447 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 448 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 449 #else 450 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 451 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 452 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 453 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 454 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 455 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 456 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 457 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 458 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 459 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 460 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 461 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 462 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 463 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 464 #endif 465 466 /* CPLD on IFC */ 467 #define CONFIG_SYS_CPLD_BASE 0xffb00000 468 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 471 #else 472 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 473 #endif 474 475 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 476 | CSPR_PORT_SIZE_8 \ 477 | CSPR_MSEL_GPCM \ 478 | CSPR_V) 479 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 480 #define CONFIG_SYS_CSOR3 0x0 481 /* CPLD Timing parameters for IFC CS3 */ 482 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 483 FTIM0_GPCM_TEADC(0x0e) | \ 484 FTIM0_GPCM_TEAHC(0x0e)) 485 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 486 FTIM1_GPCM_TRAD(0x1f)) 487 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 488 FTIM2_GPCM_TCH(0x8) | \ 489 FTIM2_GPCM_TWP(0x1f)) 490 #define CONFIG_SYS_CS3_FTIM3 0x0 491 492 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 493 defined(CONFIG_RAMBOOT_NAND) 494 #define CONFIG_SYS_RAMBOOT 495 #define CONFIG_SYS_EXTRA_ENV_RELOC 496 #else 497 #undef CONFIG_SYS_RAMBOOT 498 #endif 499 500 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 501 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 502 #define CONFIG_A003399_NOR_WORKAROUND 503 #endif 504 #endif 505 506 #define CONFIG_BOARD_EARLY_INIT_R 507 508 #define CONFIG_SYS_INIT_RAM_LOCK 509 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 510 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 511 512 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 513 - GENERATED_GBL_DATA_SIZE) 514 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 515 516 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 517 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 518 519 /* 520 * Config the L2 Cache as L2 SRAM 521 */ 522 #if defined(CONFIG_SPL_BUILD) 523 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 524 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 525 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 526 #define CONFIG_SYS_L2_SIZE (256 << 10) 527 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 528 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 529 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 530 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 531 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 532 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 533 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 534 #elif defined(CONFIG_NAND) 535 #ifdef CONFIG_TPL_BUILD 536 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 537 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 538 #define CONFIG_SYS_L2_SIZE (256 << 10) 539 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 540 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 541 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 542 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 543 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 544 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 545 #else 546 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 547 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 548 #define CONFIG_SYS_L2_SIZE (256 << 10) 549 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 550 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 551 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 552 #endif 553 #endif 554 #endif 555 556 /* Serial Port */ 557 #define CONFIG_CONS_INDEX 1 558 #undef CONFIG_SERIAL_SOFTWARE_FIFO 559 #define CONFIG_SYS_NS16550_SERIAL 560 #define CONFIG_SYS_NS16550_REG_SIZE 1 561 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 562 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 563 #define CONFIG_NS16550_MIN_FUNCTIONS 564 #endif 565 566 #define CONFIG_SYS_BAUDRATE_TABLE \ 567 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 568 569 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 570 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 571 572 /* I2C */ 573 #define CONFIG_SYS_I2C 574 #define CONFIG_SYS_I2C_FSL 575 #define CONFIG_SYS_FSL_I2C_SPEED 400000 576 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 577 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 578 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 579 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 580 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 581 #define I2C_PCA9557_ADDR1 0x18 582 #define I2C_PCA9557_ADDR2 0x19 583 #define I2C_PCA9557_BUS_NUM 0 584 585 /* I2C EEPROM */ 586 #if defined(CONFIG_TARGET_P1010RDB_PB) 587 #define CONFIG_ID_EEPROM 588 #ifdef CONFIG_ID_EEPROM 589 #define CONFIG_SYS_I2C_EEPROM_NXID 590 #endif 591 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 592 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 593 #define CONFIG_SYS_EEPROM_BUS_NUM 0 594 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 595 #endif 596 /* enable read and write access to EEPROM */ 597 #define CONFIG_CMD_EEPROM 598 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 599 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 600 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 601 602 /* RTC */ 603 #define CONFIG_RTC_PT7C4338 604 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 605 606 /* 607 * SPI interface will not be available in case of NAND boot SPI CS0 will be 608 * used for SLIC 609 */ 610 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 611 /* eSPI - Enhanced SPI */ 612 #define CONFIG_SF_DEFAULT_SPEED 10000000 613 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 614 #endif 615 616 #if defined(CONFIG_TSEC_ENET) 617 #define CONFIG_MII /* MII PHY management */ 618 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 619 #define CONFIG_TSEC1 1 620 #define CONFIG_TSEC1_NAME "eTSEC1" 621 #define CONFIG_TSEC2 1 622 #define CONFIG_TSEC2_NAME "eTSEC2" 623 #define CONFIG_TSEC3 1 624 #define CONFIG_TSEC3_NAME "eTSEC3" 625 626 #define TSEC1_PHY_ADDR 1 627 #define TSEC2_PHY_ADDR 0 628 #define TSEC3_PHY_ADDR 2 629 630 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 631 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 632 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 633 634 #define TSEC1_PHYIDX 0 635 #define TSEC2_PHYIDX 0 636 #define TSEC3_PHYIDX 0 637 638 #define CONFIG_ETHPRIME "eTSEC1" 639 640 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 641 642 /* TBI PHY configuration for SGMII mode */ 643 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 644 TBICR_PHY_RESET \ 645 | TBICR_ANEG_ENABLE \ 646 | TBICR_FULL_DUPLEX \ 647 | TBICR_SPEED1_SET \ 648 ) 649 650 #endif /* CONFIG_TSEC_ENET */ 651 652 /* SATA */ 653 #define CONFIG_FSL_SATA 654 #define CONFIG_FSL_SATA_V2 655 #define CONFIG_LIBATA 656 657 #ifdef CONFIG_FSL_SATA 658 #define CONFIG_SYS_SATA_MAX_DEVICE 2 659 #define CONFIG_SATA1 660 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 661 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 662 #define CONFIG_SATA2 663 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 664 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 665 666 #define CONFIG_CMD_SATA 667 #define CONFIG_LBA48 668 #endif /* #ifdef CONFIG_FSL_SATA */ 669 670 #ifdef CONFIG_MMC 671 #define CONFIG_FSL_ESDHC 672 #define CONFIG_GENERIC_MMC 673 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 674 #endif 675 676 #define CONFIG_HAS_FSL_DR_USB 677 678 #if defined(CONFIG_HAS_FSL_DR_USB) 679 #define CONFIG_USB_EHCI 680 681 #ifdef CONFIG_USB_EHCI 682 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 683 #define CONFIG_USB_EHCI_FSL 684 #endif 685 #endif 686 687 /* 688 * Environment 689 */ 690 #if defined(CONFIG_SDCARD) 691 #define CONFIG_ENV_IS_IN_MMC 692 #define CONFIG_FSL_FIXED_MMC_LOCATION 693 #define CONFIG_SYS_MMC_ENV_DEV 0 694 #define CONFIG_ENV_SIZE 0x2000 695 #elif defined(CONFIG_SPIFLASH) 696 #define CONFIG_ENV_IS_IN_SPI_FLASH 697 #define CONFIG_ENV_SPI_BUS 0 698 #define CONFIG_ENV_SPI_CS 0 699 #define CONFIG_ENV_SPI_MAX_HZ 10000000 700 #define CONFIG_ENV_SPI_MODE 0 701 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 702 #define CONFIG_ENV_SECT_SIZE 0x10000 703 #define CONFIG_ENV_SIZE 0x2000 704 #elif defined(CONFIG_NAND) 705 #define CONFIG_ENV_IS_IN_NAND 706 #ifdef CONFIG_TPL_BUILD 707 #define CONFIG_ENV_SIZE 0x2000 708 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 709 #else 710 #if defined(CONFIG_TARGET_P1010RDB_PA) 711 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 712 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 713 #elif defined(CONFIG_TARGET_P1010RDB_PB) 714 #define CONFIG_ENV_SIZE (16 * 1024) 715 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 716 #endif 717 #endif 718 #define CONFIG_ENV_OFFSET (1024 * 1024) 719 #elif defined(CONFIG_SYS_RAMBOOT) 720 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 721 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 722 #define CONFIG_ENV_SIZE 0x2000 723 #else 724 #define CONFIG_ENV_IS_IN_FLASH 725 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 726 #define CONFIG_ENV_SIZE 0x2000 727 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 728 #endif 729 730 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 731 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 732 733 /* 734 * Command line configuration. 735 */ 736 #define CONFIG_CMD_DATE 737 #define CONFIG_CMD_ERRATA 738 #define CONFIG_CMD_IRQ 739 #define CONFIG_CMD_REGINFO 740 741 #undef CONFIG_WATCHDOG /* watchdog disabled */ 742 743 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 744 || defined(CONFIG_FSL_SATA) 745 #endif 746 747 /* Hash command with SHA acceleration supported in hardware */ 748 #ifdef CONFIG_FSL_CAAM 749 #define CONFIG_CMD_HASH 750 #define CONFIG_SHA_HW_ACCEL 751 #endif 752 753 /* 754 * Miscellaneous configurable options 755 */ 756 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 757 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 758 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 759 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 760 761 #if defined(CONFIG_CMD_KGDB) 762 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 763 #else 764 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 765 #endif 766 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 767 /* Print Buffer Size */ 768 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 769 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 770 771 /* 772 * For booting Linux, the board info and command line data 773 * have to be in the first 64 MB of memory, since this is 774 * the maximum mapped by the Linux kernel during initialization. 775 */ 776 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 777 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 778 779 #if defined(CONFIG_CMD_KGDB) 780 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 781 #endif 782 783 /* 784 * Environment Configuration 785 */ 786 787 #if defined(CONFIG_TSEC_ENET) 788 #define CONFIG_HAS_ETH0 789 #define CONFIG_HAS_ETH1 790 #define CONFIG_HAS_ETH2 791 #endif 792 793 #define CONFIG_ROOTPATH "/opt/nfsroot" 794 #define CONFIG_BOOTFILE "uImage" 795 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 796 797 /* default location for tftp and bootm */ 798 #define CONFIG_LOADADDR 1000000 799 800 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 801 802 #define CONFIG_BAUDRATE 115200 803 804 #define CONFIG_EXTRA_ENV_SETTINGS \ 805 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 806 "netdev=eth0\0" \ 807 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 808 "loadaddr=1000000\0" \ 809 "consoledev=ttyS0\0" \ 810 "ramdiskaddr=2000000\0" \ 811 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 812 "fdtaddr=1e00000\0" \ 813 "fdtfile=p1010rdb.dtb\0" \ 814 "bdev=sda1\0" \ 815 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 816 "othbootargs=ramdisk_size=600000\0" \ 817 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 818 "console=$consoledev,$baudrate $othbootargs; " \ 819 "usb start;" \ 820 "fatload usb 0:2 $loadaddr $bootfile;" \ 821 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 822 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 823 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 824 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 825 "console=$consoledev,$baudrate $othbootargs; " \ 826 "usb start;" \ 827 "ext2load usb 0:4 $loadaddr $bootfile;" \ 828 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 829 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 830 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 831 CONFIG_BOOTMODE 832 833 #if defined(CONFIG_TARGET_P1010RDB_PA) 834 #define CONFIG_BOOTMODE \ 835 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 836 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 837 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 838 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 839 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 840 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 841 842 #elif defined(CONFIG_TARGET_P1010RDB_PB) 843 #define CONFIG_BOOTMODE \ 844 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 845 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 846 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 847 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 848 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 849 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 850 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 851 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 852 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 853 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 854 #endif 855 856 #define CONFIG_RAMBOOTCOMMAND \ 857 "setenv bootargs root=/dev/ram rw " \ 858 "console=$consoledev,$baudrate $othbootargs; " \ 859 "tftp $ramdiskaddr $ramdiskfile;" \ 860 "tftp $loadaddr $bootfile;" \ 861 "tftp $fdtaddr $fdtfile;" \ 862 "bootm $loadaddr $ramdiskaddr $fdtaddr" 863 864 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 865 866 #include <asm/fsl_secure_boot.h> 867 868 #endif /* __CONFIG_H */ 869