1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #define CONFIG_P1010 19 #define CONFIG_E500 /* BOOKE e500 family */ 20 #include <asm/config_mpc85xx.h> 21 #define CONFIG_NAND_FSL_IFC 22 23 #ifdef CONFIG_SDCARD 24 #define CONFIG_RAMBOOT_SDCARD 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifdef CONFIG_SPIFLASH 30 #define CONFIG_RAMBOOT_SPIFLASH 31 #define CONFIG_SYS_TEXT_BASE 0x11000000 32 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 33 #endif 34 35 #ifdef CONFIG_NAND 36 #define CONFIG_SPL 37 #define CONFIG_SPL_INIT_MINIMAL 38 #define CONFIG_SPL_SERIAL_SUPPORT 39 #define CONFIG_SPL_NAND_SUPPORT 40 #define CONFIG_SPL_NAND_BOOT 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 46 #define CONFIG_SPL_MAX_SIZE 8192 47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 48 #define CONFIG_SPL_RELOC_STACK 0x00100000 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #endif 55 56 57 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 58 #define CONFIG_RAMBOOT_NAND 59 #define CONFIG_SYS_TEXT_BASE 0x11000000 60 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 61 #endif 62 63 #ifndef CONFIG_SYS_TEXT_BASE 64 #define CONFIG_SYS_TEXT_BASE 0xeff40000 65 #endif 66 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 69 #endif 70 71 #ifdef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 73 #else 74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 75 #endif 76 77 /* High Level Configuration Options */ 78 #define CONFIG_BOOKE /* BOOKE */ 79 #define CONFIG_E500 /* BOOKE e500 family */ 80 #define CONFIG_FSL_IFC /* Enable IFC Support */ 81 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 82 83 #define CONFIG_PCI /* Enable PCI/PCIE */ 84 #if defined(CONFIG_PCI) 85 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 86 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 87 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 88 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 89 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 90 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 91 92 #define CONFIG_CMD_NET 93 #define CONFIG_CMD_PCI 94 95 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 96 97 /* 98 * PCI Windows 99 * Memory space is mapped 1-1, but I/O space must start from 0. 100 */ 101 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 102 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 103 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 104 #ifdef CONFIG_PHYS_64BIT 105 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 106 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 107 #else 108 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 109 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 110 #endif 111 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 112 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 113 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 114 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 117 #else 118 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 119 #endif 120 121 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 122 #if defined(CONFIG_P1010RDB_PA) 123 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 124 #elif defined(CONFIG_P1010RDB_PB) 125 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 126 #endif 127 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 128 #ifdef CONFIG_PHYS_64BIT 129 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 130 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 131 #else 132 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 133 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 134 #endif 135 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 136 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 137 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 138 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 141 #else 142 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 143 #endif 144 145 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 146 147 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 148 #define CONFIG_DOS_PARTITION 149 #endif 150 151 #define CONFIG_FSL_LAW /* Use common FSL init code */ 152 #define CONFIG_TSEC_ENET 153 #define CONFIG_ENV_OVERWRITE 154 155 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 156 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 157 158 #define CONFIG_MISC_INIT_R 159 #define CONFIG_HWCONFIG 160 /* 161 * These can be toggled for performance analysis, otherwise use default. 162 */ 163 #define CONFIG_L2_CACHE /* toggle L2 cache */ 164 #define CONFIG_BTB /* toggle branch predition */ 165 166 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 167 168 #define CONFIG_ENABLE_36BIT_PHYS 169 170 #ifdef CONFIG_PHYS_64BIT 171 #define CONFIG_ADDR_MAP 1 172 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 173 #endif 174 175 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 176 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 177 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 178 179 /* DDR Setup */ 180 #define CONFIG_SYS_FSL_DDR3 181 #define CONFIG_SYS_DDR_RAW_TIMING 182 #define CONFIG_DDR_SPD 183 #define CONFIG_SYS_SPD_BUS_NUM 1 184 #define SPD_EEPROM_ADDRESS 0x52 185 186 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 187 188 #ifndef __ASSEMBLY__ 189 extern unsigned long get_sdram_size(void); 190 #endif 191 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 192 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 193 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 194 195 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 196 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 197 198 /* DDR3 Controller Settings */ 199 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 200 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 201 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 202 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 203 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 204 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 205 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 206 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 207 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 208 #define CONFIG_SYS_DDR_RCW_1 0x00000000 209 #define CONFIG_SYS_DDR_RCW_2 0x00000000 210 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 211 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 212 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 213 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 214 215 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 216 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 217 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 218 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 219 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 220 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 221 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 222 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 223 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 224 225 /* settings for DDR3 at 667MT/s */ 226 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 227 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 228 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 229 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 230 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 231 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 232 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 233 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 234 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 235 236 #define CONFIG_SYS_CCSRBAR 0xffe00000 237 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 238 239 /* Don't relocate CCSRBAR while in NAND_SPL */ 240 #ifdef CONFIG_SPL_BUILD 241 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 242 #endif 243 244 /* 245 * Memory map 246 * 247 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 248 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 249 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 250 * 251 * Localbus non-cacheable 252 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 253 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 254 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 255 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 256 */ 257 258 /* 259 * IFC Definitions 260 */ 261 /* NOR Flash on IFC */ 262 #ifdef CONFIG_SPL_BUILD 263 #define CONFIG_SYS_NO_FLASH 264 #endif 265 266 #define CONFIG_SYS_FLASH_BASE 0xee000000 267 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 268 269 #ifdef CONFIG_PHYS_64BIT 270 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 271 #else 272 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 273 #endif 274 275 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 276 CSPR_PORT_SIZE_16 | \ 277 CSPR_MSEL_NOR | \ 278 CSPR_V) 279 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 280 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 281 /* NOR Flash Timing Params */ 282 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 283 FTIM0_NOR_TEADC(0x5) | \ 284 FTIM0_NOR_TEAHC(0x5) 285 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 286 FTIM1_NOR_TRAD_NOR(0x0f) 287 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 288 FTIM2_NOR_TCH(0x4) | \ 289 FTIM2_NOR_TWP(0x1c) 290 #define CONFIG_SYS_NOR_FTIM3 0x0 291 292 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 293 #define CONFIG_SYS_FLASH_QUIET_TEST 294 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 295 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 296 297 #undef CONFIG_SYS_FLASH_CHECKSUM 298 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 299 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 300 301 /* CFI for NOR Flash */ 302 #define CONFIG_FLASH_CFI_DRIVER 303 #define CONFIG_SYS_FLASH_CFI 304 #define CONFIG_SYS_FLASH_EMPTY_INFO 305 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 306 307 /* NAND Flash on IFC */ 308 #define CONFIG_SYS_NAND_BASE 0xff800000 309 #ifdef CONFIG_PHYS_64BIT 310 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 311 #else 312 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 313 #endif 314 315 #define CONFIG_MTD_DEVICE 316 #define CONFIG_MTD_PARTITION 317 #define CONFIG_CMD_MTDPARTS 318 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 319 #define MTDPARTS_DEFAULT \ 320 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 321 322 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 323 | CSPR_PORT_SIZE_8 \ 324 | CSPR_MSEL_NAND \ 325 | CSPR_V) 326 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 327 328 #if defined(CONFIG_P1010RDB_PA) 329 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 330 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 331 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 332 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 333 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 334 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 335 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 336 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 337 338 #elif defined(CONFIG_P1010RDB_PB) 339 #define CONFIG_SYS_NAND_ONFI_DETECTION 340 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 341 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 342 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 343 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 344 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 345 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 346 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 347 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 348 #endif 349 350 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 351 #define CONFIG_SYS_MAX_NAND_DEVICE 1 352 #define CONFIG_MTD_NAND_VERIFY_WRITE 353 #define CONFIG_CMD_NAND 354 355 #if defined(CONFIG_P1010RDB_PA) 356 /* NAND Flash Timing Params */ 357 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 358 FTIM0_NAND_TWP(0x0C) | \ 359 FTIM0_NAND_TWCHT(0x04) | \ 360 FTIM0_NAND_TWH(0x05) 361 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 362 FTIM1_NAND_TWBE(0x1d) | \ 363 FTIM1_NAND_TRR(0x07) | \ 364 FTIM1_NAND_TRP(0x0c) 365 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 366 FTIM2_NAND_TREH(0x05) | \ 367 FTIM2_NAND_TWHRE(0x0f) 368 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 369 370 #elif defined(CONFIG_P1010RDB_PB) 371 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 372 /* ONFI NAND Flash mode0 Timing Params */ 373 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 374 FTIM0_NAND_TWP(0x18) | \ 375 FTIM0_NAND_TWCHT(0x07) | \ 376 FTIM0_NAND_TWH(0x0a)) 377 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 378 FTIM1_NAND_TWBE(0x39) | \ 379 FTIM1_NAND_TRR(0x0e) | \ 380 FTIM1_NAND_TRP(0x18)) 381 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 382 FTIM2_NAND_TREH(0x0a) | \ 383 FTIM2_NAND_TWHRE(0x1e)) 384 #define CONFIG_SYS_NAND_FTIM3 0x0 385 #endif 386 387 #define CONFIG_SYS_NAND_DDR_LAW 11 388 389 /* Set up IFC registers for boot location NOR/NAND */ 390 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 391 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 392 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 393 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 394 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 395 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 396 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 397 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 398 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 399 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 400 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 401 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 402 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 403 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 404 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 405 #else 406 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 407 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 408 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 409 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 410 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 411 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 412 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 413 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 414 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 415 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 416 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 417 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 418 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 419 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 420 #endif 421 422 /* CPLD on IFC */ 423 #define CONFIG_SYS_CPLD_BASE 0xffb00000 424 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 427 #else 428 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 429 #endif 430 431 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 432 | CSPR_PORT_SIZE_8 \ 433 | CSPR_MSEL_GPCM \ 434 | CSPR_V) 435 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 436 #define CONFIG_SYS_CSOR3 0x0 437 /* CPLD Timing parameters for IFC CS3 */ 438 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 439 FTIM0_GPCM_TEADC(0x0e) | \ 440 FTIM0_GPCM_TEAHC(0x0e)) 441 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 442 FTIM1_GPCM_TRAD(0x1f)) 443 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 444 FTIM2_GPCM_TCH(0x0) | \ 445 FTIM2_GPCM_TWP(0x1f)) 446 #define CONFIG_SYS_CS3_FTIM3 0x0 447 448 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 449 #define CONFIG_SYS_RAMBOOT 450 #define CONFIG_SYS_EXTRA_ENV_RELOC 451 #else 452 #undef CONFIG_SYS_RAMBOOT 453 #endif 454 455 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 456 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ 457 && !defined(CONFIG_SECURE_BOOT) 458 #define CONFIG_A003399_NOR_WORKAROUND 459 #endif 460 #endif 461 462 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 463 #define CONFIG_BOARD_EARLY_INIT_R 464 465 #define CONFIG_SYS_INIT_RAM_LOCK 466 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 467 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 468 469 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 470 - GENERATED_GBL_DATA_SIZE) 471 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 472 473 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 474 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 475 476 /* Serial Port */ 477 #define CONFIG_CONS_INDEX 1 478 #undef CONFIG_SERIAL_SOFTWARE_FIFO 479 #define CONFIG_SYS_NS16550 480 #define CONFIG_SYS_NS16550_SERIAL 481 #define CONFIG_SYS_NS16550_REG_SIZE 1 482 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 483 #ifdef CONFIG_SPL_BUILD 484 #define CONFIG_NS16550_MIN_FUNCTIONS 485 #endif 486 487 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 488 489 #define CONFIG_SYS_BAUDRATE_TABLE \ 490 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 491 492 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 493 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 494 495 /* Use the HUSH parser */ 496 #define CONFIG_SYS_HUSH_PARSER 497 498 /* 499 * Pass open firmware flat tree 500 */ 501 #define CONFIG_OF_LIBFDT 502 #define CONFIG_OF_BOARD_SETUP 503 #define CONFIG_OF_STDOUT_VIA_ALIAS 504 505 /* new uImage format support */ 506 #define CONFIG_FIT 507 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 508 509 /* I2C */ 510 #define CONFIG_SYS_I2C 511 #define CONFIG_SYS_I2C_FSL 512 #define CONFIG_SYS_FSL_I2C_SPEED 400000 513 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 514 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 515 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 516 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 518 #define I2C_PCA9557_ADDR1 0x18 519 #define I2C_PCA9557_ADDR2 0x19 520 #define I2C_PCA9557_BUS_NUM 0 521 522 /* I2C EEPROM */ 523 #if defined(CONFIG_P1010RDB_PB) 524 #define CONFIG_ID_EEPROM 525 #ifdef CONFIG_ID_EEPROM 526 #define CONFIG_SYS_I2C_EEPROM_NXID 527 #endif 528 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 529 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 530 #define CONFIG_SYS_EEPROM_BUS_NUM 0 531 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 532 #endif 533 /* enable read and write access to EEPROM */ 534 #define CONFIG_CMD_EEPROM 535 #define CONFIG_SYS_I2C_MULTI_EEPROMS 536 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 537 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 538 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 539 540 /* RTC */ 541 #define CONFIG_RTC_PT7C4338 542 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 543 544 #define CONFIG_CMD_I2C 545 546 /* 547 * SPI interface will not be available in case of NAND boot SPI CS0 will be 548 * used for SLIC 549 */ 550 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 551 /* eSPI - Enhanced SPI */ 552 #define CONFIG_FSL_ESPI 553 #define CONFIG_SPI_FLASH 554 #define CONFIG_SPI_FLASH_SPANSION 555 #define CONFIG_CMD_SF 556 #define CONFIG_SF_DEFAULT_SPEED 10000000 557 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 558 #endif 559 560 #if defined(CONFIG_TSEC_ENET) 561 #define CONFIG_MII /* MII PHY management */ 562 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 563 #define CONFIG_TSEC1 1 564 #define CONFIG_TSEC1_NAME "eTSEC1" 565 #define CONFIG_TSEC2 1 566 #define CONFIG_TSEC2_NAME "eTSEC2" 567 #define CONFIG_TSEC3 1 568 #define CONFIG_TSEC3_NAME "eTSEC3" 569 570 #define TSEC1_PHY_ADDR 1 571 #define TSEC2_PHY_ADDR 0 572 #define TSEC3_PHY_ADDR 2 573 574 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 575 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 576 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 577 578 #define TSEC1_PHYIDX 0 579 #define TSEC2_PHYIDX 0 580 #define TSEC3_PHYIDX 0 581 582 #define CONFIG_ETHPRIME "eTSEC1" 583 584 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 585 586 /* TBI PHY configuration for SGMII mode */ 587 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 588 TBICR_PHY_RESET \ 589 | TBICR_ANEG_ENABLE \ 590 | TBICR_FULL_DUPLEX \ 591 | TBICR_SPEED1_SET \ 592 ) 593 594 #endif /* CONFIG_TSEC_ENET */ 595 596 597 /* SATA */ 598 #define CONFIG_FSL_SATA 599 #define CONFIG_FSL_SATA_V2 600 #define CONFIG_LIBATA 601 602 #ifdef CONFIG_FSL_SATA 603 #define CONFIG_SYS_SATA_MAX_DEVICE 2 604 #define CONFIG_SATA1 605 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 606 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 607 #define CONFIG_SATA2 608 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 609 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 610 611 #define CONFIG_CMD_SATA 612 #define CONFIG_LBA48 613 #endif /* #ifdef CONFIG_FSL_SATA */ 614 615 #define CONFIG_MMC 616 #ifdef CONFIG_MMC 617 #define CONFIG_CMD_MMC 618 #define CONFIG_DOS_PARTITION 619 #define CONFIG_FSL_ESDHC 620 #define CONFIG_GENERIC_MMC 621 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 622 #endif 623 624 #define CONFIG_HAS_FSL_DR_USB 625 626 #if defined(CONFIG_HAS_FSL_DR_USB) 627 #define CONFIG_USB_EHCI 628 629 #ifdef CONFIG_USB_EHCI 630 #define CONFIG_CMD_USB 631 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 632 #define CONFIG_USB_EHCI_FSL 633 #define CONFIG_USB_STORAGE 634 #endif 635 #endif 636 637 /* 638 * Environment 639 */ 640 #if defined(CONFIG_RAMBOOT_SDCARD) 641 #define CONFIG_ENV_IS_IN_MMC 642 #define CONFIG_FSL_FIXED_MMC_LOCATION 643 #define CONFIG_SYS_MMC_ENV_DEV 0 644 #define CONFIG_ENV_SIZE 0x2000 645 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 646 #define CONFIG_ENV_IS_IN_SPI_FLASH 647 #define CONFIG_ENV_SPI_BUS 0 648 #define CONFIG_ENV_SPI_CS 0 649 #define CONFIG_ENV_SPI_MAX_HZ 10000000 650 #define CONFIG_ENV_SPI_MODE 0 651 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 652 #define CONFIG_ENV_SECT_SIZE 0x10000 653 #define CONFIG_ENV_SIZE 0x2000 654 #elif defined(CONFIG_NAND) 655 #define CONFIG_ENV_IS_IN_NAND 656 #if defined(CONFIG_P1010RDB_PA) 657 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 658 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 659 #elif defined(CONFIG_P1010RDB_PB) 660 #define CONFIG_ENV_SIZE (16 * 1024) 661 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 662 #endif 663 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 664 #elif defined(CONFIG_SYS_RAMBOOT) 665 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 666 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 667 #define CONFIG_ENV_SIZE 0x2000 668 #else 669 #define CONFIG_ENV_IS_IN_FLASH 670 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 671 #define CONFIG_ENV_SIZE 0x2000 672 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 673 #endif 674 675 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 676 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 677 678 /* 679 * Command line configuration. 680 */ 681 #include <config_cmd_default.h> 682 683 #define CONFIG_CMD_DATE 684 #define CONFIG_CMD_ERRATA 685 #define CONFIG_CMD_ELF 686 #define CONFIG_CMD_IRQ 687 #define CONFIG_CMD_MII 688 #define CONFIG_CMD_PING 689 #define CONFIG_CMD_SETEXPR 690 #define CONFIG_CMD_REGINFO 691 692 #undef CONFIG_WATCHDOG /* watchdog disabled */ 693 694 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 695 || defined(CONFIG_FSL_SATA) 696 #define CONFIG_CMD_EXT2 697 #define CONFIG_CMD_FAT 698 #define CONFIG_DOS_PARTITION 699 #endif 700 701 /* 702 * Miscellaneous configurable options 703 */ 704 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 705 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 706 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 707 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 708 709 #if defined(CONFIG_CMD_KGDB) 710 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 711 #else 712 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 713 #endif 714 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 715 /* Print Buffer Size */ 716 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 717 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 718 719 /* 720 * Internal Definitions 721 * 722 * Boot Flags 723 */ 724 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 725 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 726 727 /* 728 * For booting Linux, the board info and command line data 729 * have to be in the first 64 MB of memory, since this is 730 * the maximum mapped by the Linux kernel during initialization. 731 */ 732 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 733 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 734 735 #if defined(CONFIG_CMD_KGDB) 736 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 737 #endif 738 739 /* 740 * Environment Configuration 741 */ 742 743 #if defined(CONFIG_TSEC_ENET) 744 #define CONFIG_HAS_ETH0 745 #define CONFIG_HAS_ETH1 746 #define CONFIG_HAS_ETH2 747 #endif 748 749 #define CONFIG_ROOTPATH "/opt/nfsroot" 750 #define CONFIG_BOOTFILE "uImage" 751 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 752 753 /* default location for tftp and bootm */ 754 #define CONFIG_LOADADDR 1000000 755 756 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 757 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 758 759 #define CONFIG_BAUDRATE 115200 760 761 #define CONFIG_EXTRA_ENV_SETTINGS \ 762 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 763 "netdev=eth0\0" \ 764 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 765 "loadaddr=1000000\0" \ 766 "consoledev=ttyS0\0" \ 767 "ramdiskaddr=2000000\0" \ 768 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 769 "fdtaddr=c00000\0" \ 770 "fdtfile=p1010rdb.dtb\0" \ 771 "bdev=sda1\0" \ 772 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 773 "othbootargs=ramdisk_size=600000\0" \ 774 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 775 "console=$consoledev,$baudrate $othbootargs; " \ 776 "usb start;" \ 777 "fatload usb 0:2 $loadaddr $bootfile;" \ 778 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 779 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 780 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 781 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 782 "console=$consoledev,$baudrate $othbootargs; " \ 783 "usb start;" \ 784 "ext2load usb 0:4 $loadaddr $bootfile;" \ 785 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 786 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 787 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 788 CONFIG_BOOTMODE 789 790 #if defined(CONFIG_P1010RDB_PA) 791 #define CONFIG_BOOTMODE \ 792 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 793 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 794 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 795 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 796 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 797 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 798 799 #elif defined(CONFIG_P1010RDB_PB) 800 #define CONFIG_BOOTMODE \ 801 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 802 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 803 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 804 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 805 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 806 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 807 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 808 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 809 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 810 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 811 #endif 812 813 #define CONFIG_RAMBOOTCOMMAND \ 814 "setenv bootargs root=/dev/ram rw " \ 815 "console=$consoledev,$baudrate $othbootargs; " \ 816 "tftp $ramdiskaddr $ramdiskfile;" \ 817 "tftp $loadaddr $bootfile;" \ 818 "tftp $fdtaddr $fdtfile;" \ 819 "bootm $loadaddr $ramdiskaddr $fdtaddr" 820 821 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 822 823 #include <asm/fsl_secure_boot.h> 824 825 #endif /* __CONFIG_H */ 826