1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/config_mpc85xx.h> 15 #define CONFIG_NAND_FSL_IFC 16 17 #ifdef CONFIG_SDCARD 18 #define CONFIG_SPL_FLUSH_IMAGE 19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 20 #define CONFIG_SPL_TEXT_BASE 0xD0001000 21 #define CONFIG_SPL_PAD_TO 0x18000 22 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 23 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 24 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 26 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 28 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 29 #define CONFIG_SPL_MMC_BOOT 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_COMMON_INIT_DDR 32 #endif 33 #endif 34 35 #ifdef CONFIG_SPIFLASH 36 #ifdef CONFIG_SECURE_BOOT 37 #define CONFIG_RAMBOOT_SPIFLASH 38 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 39 #else 40 #define CONFIG_SPL_SPI_FLASH_MINIMAL 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 #define CONFIG_SPL_TEXT_BASE 0xD0001000 44 #define CONFIG_SPL_PAD_TO 0x18000 45 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 50 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 52 #define CONFIG_SPL_SPI_BOOT 53 #ifdef CONFIG_SPL_BUILD 54 #define CONFIG_SPL_COMMON_INIT_DDR 55 #endif 56 #endif 57 #endif 58 59 #ifdef CONFIG_NAND 60 #ifdef CONFIG_SECURE_BOOT 61 #define CONFIG_SPL_INIT_MINIMAL 62 #define CONFIG_SPL_NAND_BOOT 63 #define CONFIG_SPL_FLUSH_IMAGE 64 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 65 66 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 67 #define CONFIG_SPL_MAX_SIZE 8192 68 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 69 #define CONFIG_SPL_RELOC_STACK 0x00100000 70 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 71 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 72 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 73 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 75 #else 76 #ifdef CONFIG_TPL_BUILD 77 #define CONFIG_SPL_NAND_BOOT 78 #define CONFIG_SPL_FLUSH_IMAGE 79 #define CONFIG_SPL_NAND_INIT 80 #define CONFIG_SPL_COMMON_INIT_DDR 81 #define CONFIG_SPL_MAX_SIZE (128 << 10) 82 #define CONFIG_SPL_TEXT_BASE 0xD0001000 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 85 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 86 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 87 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 88 #elif defined(CONFIG_SPL_BUILD) 89 #define CONFIG_SPL_INIT_MINIMAL 90 #define CONFIG_SPL_NAND_MINIMAL 91 #define CONFIG_SPL_FLUSH_IMAGE 92 #define CONFIG_SPL_TEXT_BASE 0xff800000 93 #define CONFIG_SPL_MAX_SIZE 8192 94 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 95 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 96 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 97 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 98 #endif 99 #define CONFIG_SPL_PAD_TO 0x20000 100 #define CONFIG_TPL_PAD_TO 0x20000 101 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 102 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 103 #endif 104 #endif 105 106 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 107 #define CONFIG_RAMBOOT_NAND 108 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 109 #endif 110 111 #ifndef CONFIG_RESET_VECTOR_ADDRESS 112 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 113 #endif 114 115 #ifdef CONFIG_SPL_BUILD 116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 117 #else 118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 119 #endif 120 121 /* High Level Configuration Options */ 122 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 123 124 #if defined(CONFIG_PCI) 125 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 126 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 127 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 128 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 129 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 130 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 131 132 /* 133 * PCI Windows 134 * Memory space is mapped 1-1, but I/O space must start from 0. 135 */ 136 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 137 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 138 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 141 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 142 #else 143 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 144 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 145 #endif 146 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 147 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 148 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 149 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 150 #ifdef CONFIG_PHYS_64BIT 151 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 152 #else 153 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 154 #endif 155 156 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 157 #if defined(CONFIG_TARGET_P1010RDB_PA) 158 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 159 #elif defined(CONFIG_TARGET_P1010RDB_PB) 160 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 161 #endif 162 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 163 #ifdef CONFIG_PHYS_64BIT 164 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 165 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 166 #else 167 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 168 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 169 #endif 170 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 171 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 172 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 173 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 174 #ifdef CONFIG_PHYS_64BIT 175 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 176 #else 177 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 178 #endif 179 180 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 181 #endif 182 183 #define CONFIG_TSEC_ENET 184 #define CONFIG_ENV_OVERWRITE 185 186 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 187 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 188 189 #define CONFIG_MISC_INIT_R 190 #define CONFIG_HWCONFIG 191 /* 192 * These can be toggled for performance analysis, otherwise use default. 193 */ 194 #define CONFIG_L2_CACHE /* toggle L2 cache */ 195 #define CONFIG_BTB /* toggle branch predition */ 196 197 198 #define CONFIG_ENABLE_36BIT_PHYS 199 200 #ifdef CONFIG_PHYS_64BIT 201 #define CONFIG_ADDR_MAP 1 202 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 203 #endif 204 205 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 206 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 207 208 /* DDR Setup */ 209 #define CONFIG_SYS_DDR_RAW_TIMING 210 #define CONFIG_DDR_SPD 211 #define CONFIG_SYS_SPD_BUS_NUM 1 212 #define SPD_EEPROM_ADDRESS 0x52 213 214 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 215 216 #ifndef __ASSEMBLY__ 217 extern unsigned long get_sdram_size(void); 218 #endif 219 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 220 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 221 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 222 223 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 224 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 225 226 /* DDR3 Controller Settings */ 227 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 228 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 229 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 230 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 231 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 232 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 233 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 234 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 235 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 236 #define CONFIG_SYS_DDR_RCW_1 0x00000000 237 #define CONFIG_SYS_DDR_RCW_2 0x00000000 238 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 239 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 240 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 241 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 242 243 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 244 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 245 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 246 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 247 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 248 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 249 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 250 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 251 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 252 253 /* settings for DDR3 at 667MT/s */ 254 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 255 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 256 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 257 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 258 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 259 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 260 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 261 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 262 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 263 264 #define CONFIG_SYS_CCSRBAR 0xffe00000 265 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 266 267 /* Don't relocate CCSRBAR while in NAND_SPL */ 268 #ifdef CONFIG_SPL_BUILD 269 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 270 #endif 271 272 /* 273 * Memory map 274 * 275 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 276 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 277 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 278 * 279 * Localbus non-cacheable 280 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 281 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 282 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 283 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 284 */ 285 286 /* 287 * IFC Definitions 288 */ 289 /* NOR Flash on IFC */ 290 291 #define CONFIG_SYS_FLASH_BASE 0xee000000 292 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 293 294 #ifdef CONFIG_PHYS_64BIT 295 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 296 #else 297 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 298 #endif 299 300 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 301 CSPR_PORT_SIZE_16 | \ 302 CSPR_MSEL_NOR | \ 303 CSPR_V) 304 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 305 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 306 /* NOR Flash Timing Params */ 307 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 308 FTIM0_NOR_TEADC(0x5) | \ 309 FTIM0_NOR_TEAHC(0x5) 310 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 311 FTIM1_NOR_TRAD_NOR(0x0f) 312 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 313 FTIM2_NOR_TCH(0x4) | \ 314 FTIM2_NOR_TWP(0x1c) 315 #define CONFIG_SYS_NOR_FTIM3 0x0 316 317 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 318 #define CONFIG_SYS_FLASH_QUIET_TEST 319 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 320 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 321 322 #undef CONFIG_SYS_FLASH_CHECKSUM 323 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 324 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 325 326 /* CFI for NOR Flash */ 327 #define CONFIG_FLASH_CFI_DRIVER 328 #define CONFIG_SYS_FLASH_CFI 329 #define CONFIG_SYS_FLASH_EMPTY_INFO 330 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 331 332 /* NAND Flash on IFC */ 333 #define CONFIG_SYS_NAND_BASE 0xff800000 334 #ifdef CONFIG_PHYS_64BIT 335 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 336 #else 337 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 338 #endif 339 340 #define CONFIG_MTD_DEVICE 341 #define CONFIG_MTD_PARTITION 342 343 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 344 | CSPR_PORT_SIZE_8 \ 345 | CSPR_MSEL_NAND \ 346 | CSPR_V) 347 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 348 349 #if defined(CONFIG_TARGET_P1010RDB_PA) 350 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 351 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 352 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 353 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 354 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 355 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 356 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 357 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 358 359 #elif defined(CONFIG_TARGET_P1010RDB_PB) 360 #define CONFIG_SYS_NAND_ONFI_DETECTION 361 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 362 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 363 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 364 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 365 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 366 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 367 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 368 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 369 #endif 370 371 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 372 #define CONFIG_SYS_MAX_NAND_DEVICE 1 373 374 #if defined(CONFIG_TARGET_P1010RDB_PA) 375 /* NAND Flash Timing Params */ 376 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 377 FTIM0_NAND_TWP(0x0C) | \ 378 FTIM0_NAND_TWCHT(0x04) | \ 379 FTIM0_NAND_TWH(0x05) 380 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 381 FTIM1_NAND_TWBE(0x1d) | \ 382 FTIM1_NAND_TRR(0x07) | \ 383 FTIM1_NAND_TRP(0x0c) 384 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 385 FTIM2_NAND_TREH(0x05) | \ 386 FTIM2_NAND_TWHRE(0x0f) 387 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 388 389 #elif defined(CONFIG_TARGET_P1010RDB_PB) 390 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 391 /* ONFI NAND Flash mode0 Timing Params */ 392 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 393 FTIM0_NAND_TWP(0x18) | \ 394 FTIM0_NAND_TWCHT(0x07) | \ 395 FTIM0_NAND_TWH(0x0a)) 396 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 397 FTIM1_NAND_TWBE(0x39) | \ 398 FTIM1_NAND_TRR(0x0e) | \ 399 FTIM1_NAND_TRP(0x18)) 400 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 401 FTIM2_NAND_TREH(0x0a) | \ 402 FTIM2_NAND_TWHRE(0x1e)) 403 #define CONFIG_SYS_NAND_FTIM3 0x0 404 #endif 405 406 #define CONFIG_SYS_NAND_DDR_LAW 11 407 408 /* Set up IFC registers for boot location NOR/NAND */ 409 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 410 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 411 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 412 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 413 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 414 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 415 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 416 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 417 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 418 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 419 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 420 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 421 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 422 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 423 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 424 #else 425 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 426 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 427 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 428 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 429 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 430 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 431 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 432 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 433 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 434 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 435 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 436 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 437 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 438 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 439 #endif 440 441 /* CPLD on IFC */ 442 #define CONFIG_SYS_CPLD_BASE 0xffb00000 443 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 446 #else 447 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 448 #endif 449 450 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 451 | CSPR_PORT_SIZE_8 \ 452 | CSPR_MSEL_GPCM \ 453 | CSPR_V) 454 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 455 #define CONFIG_SYS_CSOR3 0x0 456 /* CPLD Timing parameters for IFC CS3 */ 457 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 458 FTIM0_GPCM_TEADC(0x0e) | \ 459 FTIM0_GPCM_TEAHC(0x0e)) 460 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 461 FTIM1_GPCM_TRAD(0x1f)) 462 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 463 FTIM2_GPCM_TCH(0x8) | \ 464 FTIM2_GPCM_TWP(0x1f)) 465 #define CONFIG_SYS_CS3_FTIM3 0x0 466 467 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 468 defined(CONFIG_RAMBOOT_NAND) 469 #define CONFIG_SYS_RAMBOOT 470 #define CONFIG_SYS_EXTRA_ENV_RELOC 471 #else 472 #undef CONFIG_SYS_RAMBOOT 473 #endif 474 475 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 476 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 477 #define CONFIG_A003399_NOR_WORKAROUND 478 #endif 479 #endif 480 481 #define CONFIG_BOARD_EARLY_INIT_R 482 483 #define CONFIG_SYS_INIT_RAM_LOCK 484 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 485 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 486 487 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 488 - GENERATED_GBL_DATA_SIZE) 489 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 490 491 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 492 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 493 494 /* 495 * Config the L2 Cache as L2 SRAM 496 */ 497 #if defined(CONFIG_SPL_BUILD) 498 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 499 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 500 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 501 #define CONFIG_SYS_L2_SIZE (256 << 10) 502 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 503 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 504 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 505 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 506 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 507 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 508 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 509 #elif defined(CONFIG_NAND) 510 #ifdef CONFIG_TPL_BUILD 511 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 512 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 513 #define CONFIG_SYS_L2_SIZE (256 << 10) 514 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 515 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 516 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 517 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 518 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 519 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 520 #else 521 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 522 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 523 #define CONFIG_SYS_L2_SIZE (256 << 10) 524 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 525 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 526 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 527 #endif 528 #endif 529 #endif 530 531 /* Serial Port */ 532 #define CONFIG_CONS_INDEX 1 533 #undef CONFIG_SERIAL_SOFTWARE_FIFO 534 #define CONFIG_SYS_NS16550_SERIAL 535 #define CONFIG_SYS_NS16550_REG_SIZE 1 536 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 537 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 538 #define CONFIG_NS16550_MIN_FUNCTIONS 539 #endif 540 541 #define CONFIG_SYS_BAUDRATE_TABLE \ 542 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 543 544 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 545 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 546 547 /* I2C */ 548 #define CONFIG_SYS_I2C 549 #define CONFIG_SYS_I2C_FSL 550 #define CONFIG_SYS_FSL_I2C_SPEED 400000 551 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 552 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 553 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 554 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 555 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 556 #define I2C_PCA9557_ADDR1 0x18 557 #define I2C_PCA9557_ADDR2 0x19 558 #define I2C_PCA9557_BUS_NUM 0 559 560 /* I2C EEPROM */ 561 #if defined(CONFIG_TARGET_P1010RDB_PB) 562 #define CONFIG_ID_EEPROM 563 #ifdef CONFIG_ID_EEPROM 564 #define CONFIG_SYS_I2C_EEPROM_NXID 565 #endif 566 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 567 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 568 #define CONFIG_SYS_EEPROM_BUS_NUM 0 569 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 570 #endif 571 /* enable read and write access to EEPROM */ 572 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 573 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 574 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 575 576 /* RTC */ 577 #define CONFIG_RTC_PT7C4338 578 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 579 580 /* 581 * SPI interface will not be available in case of NAND boot SPI CS0 will be 582 * used for SLIC 583 */ 584 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 585 /* eSPI - Enhanced SPI */ 586 #define CONFIG_SF_DEFAULT_SPEED 10000000 587 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 588 #endif 589 590 #if defined(CONFIG_TSEC_ENET) 591 #define CONFIG_MII /* MII PHY management */ 592 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 593 #define CONFIG_TSEC1 1 594 #define CONFIG_TSEC1_NAME "eTSEC1" 595 #define CONFIG_TSEC2 1 596 #define CONFIG_TSEC2_NAME "eTSEC2" 597 #define CONFIG_TSEC3 1 598 #define CONFIG_TSEC3_NAME "eTSEC3" 599 600 #define TSEC1_PHY_ADDR 1 601 #define TSEC2_PHY_ADDR 0 602 #define TSEC3_PHY_ADDR 2 603 604 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 605 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 606 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 607 608 #define TSEC1_PHYIDX 0 609 #define TSEC2_PHYIDX 0 610 #define TSEC3_PHYIDX 0 611 612 #define CONFIG_ETHPRIME "eTSEC1" 613 614 /* TBI PHY configuration for SGMII mode */ 615 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 616 TBICR_PHY_RESET \ 617 | TBICR_ANEG_ENABLE \ 618 | TBICR_FULL_DUPLEX \ 619 | TBICR_SPEED1_SET \ 620 ) 621 622 #endif /* CONFIG_TSEC_ENET */ 623 624 /* SATA */ 625 #define CONFIG_FSL_SATA_V2 626 627 #ifdef CONFIG_FSL_SATA 628 #define CONFIG_SYS_SATA_MAX_DEVICE 2 629 #define CONFIG_SATA1 630 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 631 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 632 #define CONFIG_SATA2 633 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 634 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 635 636 #define CONFIG_LBA48 637 #endif /* #ifdef CONFIG_FSL_SATA */ 638 639 #ifdef CONFIG_MMC 640 #define CONFIG_FSL_ESDHC 641 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 642 #endif 643 644 #define CONFIG_HAS_FSL_DR_USB 645 646 #if defined(CONFIG_HAS_FSL_DR_USB) 647 #ifdef CONFIG_USB_EHCI_HCD 648 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 649 #define CONFIG_USB_EHCI_FSL 650 #endif 651 #endif 652 653 /* 654 * Environment 655 */ 656 #if defined(CONFIG_SDCARD) 657 #define CONFIG_FSL_FIXED_MMC_LOCATION 658 #define CONFIG_SYS_MMC_ENV_DEV 0 659 #define CONFIG_ENV_SIZE 0x2000 660 #elif defined(CONFIG_SPIFLASH) 661 #define CONFIG_ENV_SPI_BUS 0 662 #define CONFIG_ENV_SPI_CS 0 663 #define CONFIG_ENV_SPI_MAX_HZ 10000000 664 #define CONFIG_ENV_SPI_MODE 0 665 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 666 #define CONFIG_ENV_SECT_SIZE 0x10000 667 #define CONFIG_ENV_SIZE 0x2000 668 #elif defined(CONFIG_NAND) 669 #ifdef CONFIG_TPL_BUILD 670 #define CONFIG_ENV_SIZE 0x2000 671 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 672 #else 673 #if defined(CONFIG_TARGET_P1010RDB_PA) 674 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 675 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 676 #elif defined(CONFIG_TARGET_P1010RDB_PB) 677 #define CONFIG_ENV_SIZE (16 * 1024) 678 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 679 #endif 680 #endif 681 #define CONFIG_ENV_OFFSET (1024 * 1024) 682 #elif defined(CONFIG_SYS_RAMBOOT) 683 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 684 #define CONFIG_ENV_SIZE 0x2000 685 #else 686 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 687 #define CONFIG_ENV_SIZE 0x2000 688 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 689 #endif 690 691 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 692 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 693 694 #undef CONFIG_WATCHDOG /* watchdog disabled */ 695 696 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ 697 || defined(CONFIG_FSL_SATA) 698 #endif 699 700 /* 701 * Miscellaneous configurable options 702 */ 703 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 704 705 /* 706 * For booting Linux, the board info and command line data 707 * have to be in the first 64 MB of memory, since this is 708 * the maximum mapped by the Linux kernel during initialization. 709 */ 710 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 711 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 712 713 #if defined(CONFIG_CMD_KGDB) 714 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 715 #endif 716 717 /* 718 * Environment Configuration 719 */ 720 721 #if defined(CONFIG_TSEC_ENET) 722 #define CONFIG_HAS_ETH0 723 #define CONFIG_HAS_ETH1 724 #define CONFIG_HAS_ETH2 725 #endif 726 727 #define CONFIG_ROOTPATH "/opt/nfsroot" 728 #define CONFIG_BOOTFILE "uImage" 729 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 730 731 /* default location for tftp and bootm */ 732 #define CONFIG_LOADADDR 1000000 733 734 #define CONFIG_EXTRA_ENV_SETTINGS \ 735 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 736 "netdev=eth0\0" \ 737 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 738 "loadaddr=1000000\0" \ 739 "consoledev=ttyS0\0" \ 740 "ramdiskaddr=2000000\0" \ 741 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 742 "fdtaddr=1e00000\0" \ 743 "fdtfile=p1010rdb.dtb\0" \ 744 "bdev=sda1\0" \ 745 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 746 "othbootargs=ramdisk_size=600000\0" \ 747 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 748 "console=$consoledev,$baudrate $othbootargs; " \ 749 "usb start;" \ 750 "fatload usb 0:2 $loadaddr $bootfile;" \ 751 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 752 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 753 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 754 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 755 "console=$consoledev,$baudrate $othbootargs; " \ 756 "usb start;" \ 757 "ext2load usb 0:4 $loadaddr $bootfile;" \ 758 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 759 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 760 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 761 CONFIG_BOOTMODE 762 763 #if defined(CONFIG_TARGET_P1010RDB_PA) 764 #define CONFIG_BOOTMODE \ 765 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 766 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 767 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 768 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 769 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 770 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 771 772 #elif defined(CONFIG_TARGET_P1010RDB_PB) 773 #define CONFIG_BOOTMODE \ 774 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 775 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 776 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 777 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 778 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 779 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 780 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 781 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 782 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 783 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 784 #endif 785 786 #define CONFIG_RAMBOOTCOMMAND \ 787 "setenv bootargs root=/dev/ram rw " \ 788 "console=$consoledev,$baudrate $othbootargs; " \ 789 "tftp $ramdiskaddr $ramdiskfile;" \ 790 "tftp $loadaddr $bootfile;" \ 791 "tftp $fdtaddr $fdtfile;" \ 792 "bootm $loadaddr $ramdiskaddr $fdtaddr" 793 794 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 795 796 #include <asm/fsl_secure_boot.h> 797 798 #endif /* __CONFIG_H */ 799