1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/config_mpc85xx.h> 15 #define CONFIG_NAND_FSL_IFC 16 17 #ifdef CONFIG_SDCARD 18 #define CONFIG_SPL_FLUSH_IMAGE 19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 20 #define CONFIG_SPL_TEXT_BASE 0xD0001000 21 #define CONFIG_SPL_PAD_TO 0x18000 22 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 23 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 24 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 26 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 27 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 28 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 29 #define CONFIG_SPL_MMC_BOOT 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_COMMON_INIT_DDR 32 #endif 33 #endif 34 35 #ifdef CONFIG_SPIFLASH 36 #ifdef CONFIG_SECURE_BOOT 37 #define CONFIG_RAMBOOT_SPIFLASH 38 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 39 #else 40 #define CONFIG_SPL_SPI_FLASH_MINIMAL 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 #define CONFIG_SPL_TEXT_BASE 0xD0001000 44 #define CONFIG_SPL_PAD_TO 0x18000 45 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 49 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 50 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 51 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 52 #define CONFIG_SPL_SPI_BOOT 53 #ifdef CONFIG_SPL_BUILD 54 #define CONFIG_SPL_COMMON_INIT_DDR 55 #endif 56 #endif 57 #endif 58 59 #ifdef CONFIG_NAND 60 #ifdef CONFIG_SECURE_BOOT 61 #define CONFIG_SPL_INIT_MINIMAL 62 #define CONFIG_SPL_NAND_BOOT 63 #define CONFIG_SPL_FLUSH_IMAGE 64 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 65 66 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 67 #define CONFIG_SPL_MAX_SIZE 8192 68 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 69 #define CONFIG_SPL_RELOC_STACK 0x00100000 70 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 71 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 72 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 73 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 75 #else 76 #ifdef CONFIG_TPL_BUILD 77 #define CONFIG_SPL_NAND_BOOT 78 #define CONFIG_SPL_FLUSH_IMAGE 79 #define CONFIG_SPL_NAND_INIT 80 #define CONFIG_SPL_COMMON_INIT_DDR 81 #define CONFIG_SPL_MAX_SIZE (128 << 10) 82 #define CONFIG_SPL_TEXT_BASE 0xD0001000 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 85 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 86 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 87 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 88 #elif defined(CONFIG_SPL_BUILD) 89 #define CONFIG_SPL_INIT_MINIMAL 90 #define CONFIG_SPL_NAND_MINIMAL 91 #define CONFIG_SPL_FLUSH_IMAGE 92 #define CONFIG_SPL_TEXT_BASE 0xff800000 93 #define CONFIG_SPL_MAX_SIZE 8192 94 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 95 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 96 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 97 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 98 #endif 99 #define CONFIG_SPL_PAD_TO 0x20000 100 #define CONFIG_TPL_PAD_TO 0x20000 101 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 102 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 103 #endif 104 #endif 105 106 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 107 #define CONFIG_RAMBOOT_NAND 108 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 109 #endif 110 111 #ifndef CONFIG_RESET_VECTOR_ADDRESS 112 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 113 #endif 114 115 #ifdef CONFIG_SPL_BUILD 116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 117 #else 118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 119 #endif 120 121 /* High Level Configuration Options */ 122 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 123 124 #if defined(CONFIG_PCI) 125 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 126 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 127 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 128 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 129 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 130 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 131 132 /* 133 * PCI Windows 134 * Memory space is mapped 1-1, but I/O space must start from 0. 135 */ 136 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 137 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 138 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 139 #ifdef CONFIG_PHYS_64BIT 140 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 141 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 142 #else 143 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 144 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 145 #endif 146 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 147 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 148 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 149 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 150 #ifdef CONFIG_PHYS_64BIT 151 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 152 #else 153 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 154 #endif 155 156 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 157 #if defined(CONFIG_TARGET_P1010RDB_PA) 158 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 159 #elif defined(CONFIG_TARGET_P1010RDB_PB) 160 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 161 #endif 162 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 163 #ifdef CONFIG_PHYS_64BIT 164 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 165 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 166 #else 167 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 168 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 169 #endif 170 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 171 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 172 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 173 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 174 #ifdef CONFIG_PHYS_64BIT 175 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 176 #else 177 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 178 #endif 179 180 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 181 #endif 182 183 #define CONFIG_ENV_OVERWRITE 184 185 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 186 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 187 188 #define CONFIG_MISC_INIT_R 189 #define CONFIG_HWCONFIG 190 /* 191 * These can be toggled for performance analysis, otherwise use default. 192 */ 193 #define CONFIG_L2_CACHE /* toggle L2 cache */ 194 #define CONFIG_BTB /* toggle branch predition */ 195 196 197 #define CONFIG_ENABLE_36BIT_PHYS 198 199 #ifdef CONFIG_PHYS_64BIT 200 #define CONFIG_ADDR_MAP 1 201 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 202 #endif 203 204 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 205 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 206 207 /* DDR Setup */ 208 #define CONFIG_SYS_DDR_RAW_TIMING 209 #define CONFIG_DDR_SPD 210 #define CONFIG_SYS_SPD_BUS_NUM 1 211 #define SPD_EEPROM_ADDRESS 0x52 212 213 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 214 215 #ifndef __ASSEMBLY__ 216 extern unsigned long get_sdram_size(void); 217 #endif 218 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 219 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 220 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 221 222 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 223 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 224 225 /* DDR3 Controller Settings */ 226 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 227 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 228 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 229 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 230 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 231 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 232 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 233 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 234 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 235 #define CONFIG_SYS_DDR_RCW_1 0x00000000 236 #define CONFIG_SYS_DDR_RCW_2 0x00000000 237 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 238 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 239 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 240 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 241 242 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 243 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 244 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 245 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 246 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 247 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 248 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 249 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 250 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 251 252 /* settings for DDR3 at 667MT/s */ 253 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 254 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 255 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 256 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 257 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 258 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 259 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 260 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 261 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 262 263 #define CONFIG_SYS_CCSRBAR 0xffe00000 264 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 265 266 /* Don't relocate CCSRBAR while in NAND_SPL */ 267 #ifdef CONFIG_SPL_BUILD 268 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 269 #endif 270 271 /* 272 * Memory map 273 * 274 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 275 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 276 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 277 * 278 * Localbus non-cacheable 279 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 280 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 281 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 282 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 283 */ 284 285 /* 286 * IFC Definitions 287 */ 288 /* NOR Flash on IFC */ 289 290 #define CONFIG_SYS_FLASH_BASE 0xee000000 291 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 292 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 295 #else 296 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 297 #endif 298 299 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 300 CSPR_PORT_SIZE_16 | \ 301 CSPR_MSEL_NOR | \ 302 CSPR_V) 303 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 304 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 305 /* NOR Flash Timing Params */ 306 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 307 FTIM0_NOR_TEADC(0x5) | \ 308 FTIM0_NOR_TEAHC(0x5) 309 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 310 FTIM1_NOR_TRAD_NOR(0x0f) 311 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 312 FTIM2_NOR_TCH(0x4) | \ 313 FTIM2_NOR_TWP(0x1c) 314 #define CONFIG_SYS_NOR_FTIM3 0x0 315 316 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 317 #define CONFIG_SYS_FLASH_QUIET_TEST 318 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 319 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 320 321 #undef CONFIG_SYS_FLASH_CHECKSUM 322 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 323 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 324 325 /* CFI for NOR Flash */ 326 #define CONFIG_FLASH_CFI_DRIVER 327 #define CONFIG_SYS_FLASH_CFI 328 #define CONFIG_SYS_FLASH_EMPTY_INFO 329 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 330 331 /* NAND Flash on IFC */ 332 #define CONFIG_SYS_NAND_BASE 0xff800000 333 #ifdef CONFIG_PHYS_64BIT 334 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 335 #else 336 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 337 #endif 338 339 #define CONFIG_MTD_DEVICE 340 #define CONFIG_MTD_PARTITION 341 342 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 343 | CSPR_PORT_SIZE_8 \ 344 | CSPR_MSEL_NAND \ 345 | CSPR_V) 346 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 347 348 #if defined(CONFIG_TARGET_P1010RDB_PA) 349 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 350 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 351 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 352 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 353 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 354 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 355 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 356 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 357 358 #elif defined(CONFIG_TARGET_P1010RDB_PB) 359 #define CONFIG_SYS_NAND_ONFI_DETECTION 360 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 361 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 362 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 363 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 364 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 365 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 366 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 367 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 368 #endif 369 370 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 371 #define CONFIG_SYS_MAX_NAND_DEVICE 1 372 373 #if defined(CONFIG_TARGET_P1010RDB_PA) 374 /* NAND Flash Timing Params */ 375 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 376 FTIM0_NAND_TWP(0x0C) | \ 377 FTIM0_NAND_TWCHT(0x04) | \ 378 FTIM0_NAND_TWH(0x05) 379 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 380 FTIM1_NAND_TWBE(0x1d) | \ 381 FTIM1_NAND_TRR(0x07) | \ 382 FTIM1_NAND_TRP(0x0c) 383 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 384 FTIM2_NAND_TREH(0x05) | \ 385 FTIM2_NAND_TWHRE(0x0f) 386 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 387 388 #elif defined(CONFIG_TARGET_P1010RDB_PB) 389 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 390 /* ONFI NAND Flash mode0 Timing Params */ 391 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 392 FTIM0_NAND_TWP(0x18) | \ 393 FTIM0_NAND_TWCHT(0x07) | \ 394 FTIM0_NAND_TWH(0x0a)) 395 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 396 FTIM1_NAND_TWBE(0x39) | \ 397 FTIM1_NAND_TRR(0x0e) | \ 398 FTIM1_NAND_TRP(0x18)) 399 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 400 FTIM2_NAND_TREH(0x0a) | \ 401 FTIM2_NAND_TWHRE(0x1e)) 402 #define CONFIG_SYS_NAND_FTIM3 0x0 403 #endif 404 405 #define CONFIG_SYS_NAND_DDR_LAW 11 406 407 /* Set up IFC registers for boot location NOR/NAND */ 408 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 409 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 410 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 411 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 412 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 413 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 414 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 415 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 416 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 417 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 418 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 419 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 420 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 421 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 422 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 423 #else 424 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 425 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 426 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 427 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 428 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 429 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 430 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 431 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 432 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 433 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 434 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 435 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 436 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 437 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 438 #endif 439 440 /* CPLD on IFC */ 441 #define CONFIG_SYS_CPLD_BASE 0xffb00000 442 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 445 #else 446 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 447 #endif 448 449 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 450 | CSPR_PORT_SIZE_8 \ 451 | CSPR_MSEL_GPCM \ 452 | CSPR_V) 453 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 454 #define CONFIG_SYS_CSOR3 0x0 455 /* CPLD Timing parameters for IFC CS3 */ 456 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 457 FTIM0_GPCM_TEADC(0x0e) | \ 458 FTIM0_GPCM_TEAHC(0x0e)) 459 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 460 FTIM1_GPCM_TRAD(0x1f)) 461 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 462 FTIM2_GPCM_TCH(0x8) | \ 463 FTIM2_GPCM_TWP(0x1f)) 464 #define CONFIG_SYS_CS3_FTIM3 0x0 465 466 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 467 defined(CONFIG_RAMBOOT_NAND) 468 #define CONFIG_SYS_RAMBOOT 469 #define CONFIG_SYS_EXTRA_ENV_RELOC 470 #else 471 #undef CONFIG_SYS_RAMBOOT 472 #endif 473 474 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 475 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 476 #define CONFIG_A003399_NOR_WORKAROUND 477 #endif 478 #endif 479 480 #define CONFIG_SYS_INIT_RAM_LOCK 481 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 482 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 483 484 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 485 - GENERATED_GBL_DATA_SIZE) 486 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 487 488 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 489 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 490 491 /* 492 * Config the L2 Cache as L2 SRAM 493 */ 494 #if defined(CONFIG_SPL_BUILD) 495 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 496 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 497 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 498 #define CONFIG_SYS_L2_SIZE (256 << 10) 499 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 500 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 501 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 502 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 503 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 504 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 505 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 506 #elif defined(CONFIG_NAND) 507 #ifdef CONFIG_TPL_BUILD 508 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 509 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 510 #define CONFIG_SYS_L2_SIZE (256 << 10) 511 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 512 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 513 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 514 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 515 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 516 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 517 #else 518 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 519 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 520 #define CONFIG_SYS_L2_SIZE (256 << 10) 521 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 522 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 523 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 524 #endif 525 #endif 526 #endif 527 528 /* Serial Port */ 529 #undef CONFIG_SERIAL_SOFTWARE_FIFO 530 #define CONFIG_SYS_NS16550_SERIAL 531 #define CONFIG_SYS_NS16550_REG_SIZE 1 532 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 533 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 534 #define CONFIG_NS16550_MIN_FUNCTIONS 535 #endif 536 537 #define CONFIG_SYS_BAUDRATE_TABLE \ 538 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 539 540 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 541 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 542 543 /* I2C */ 544 #define CONFIG_SYS_I2C 545 #define CONFIG_SYS_I2C_FSL 546 #define CONFIG_SYS_FSL_I2C_SPEED 400000 547 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 548 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 549 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 550 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 551 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 552 #define I2C_PCA9557_ADDR1 0x18 553 #define I2C_PCA9557_ADDR2 0x19 554 #define I2C_PCA9557_BUS_NUM 0 555 556 /* I2C EEPROM */ 557 #if defined(CONFIG_TARGET_P1010RDB_PB) 558 #define CONFIG_ID_EEPROM 559 #ifdef CONFIG_ID_EEPROM 560 #define CONFIG_SYS_I2C_EEPROM_NXID 561 #endif 562 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 563 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 564 #define CONFIG_SYS_EEPROM_BUS_NUM 0 565 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 566 #endif 567 /* enable read and write access to EEPROM */ 568 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 569 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 570 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 571 572 /* RTC */ 573 #define CONFIG_RTC_PT7C4338 574 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 575 576 /* 577 * SPI interface will not be available in case of NAND boot SPI CS0 will be 578 * used for SLIC 579 */ 580 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 581 /* eSPI - Enhanced SPI */ 582 #define CONFIG_SF_DEFAULT_SPEED 10000000 583 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 584 #endif 585 586 #if defined(CONFIG_TSEC_ENET) 587 #define CONFIG_MII /* MII PHY management */ 588 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 589 #define CONFIG_TSEC1 1 590 #define CONFIG_TSEC1_NAME "eTSEC1" 591 #define CONFIG_TSEC2 1 592 #define CONFIG_TSEC2_NAME "eTSEC2" 593 #define CONFIG_TSEC3 1 594 #define CONFIG_TSEC3_NAME "eTSEC3" 595 596 #define TSEC1_PHY_ADDR 1 597 #define TSEC2_PHY_ADDR 0 598 #define TSEC3_PHY_ADDR 2 599 600 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 601 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 602 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 603 604 #define TSEC1_PHYIDX 0 605 #define TSEC2_PHYIDX 0 606 #define TSEC3_PHYIDX 0 607 608 #define CONFIG_ETHPRIME "eTSEC1" 609 610 /* TBI PHY configuration for SGMII mode */ 611 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 612 TBICR_PHY_RESET \ 613 | TBICR_ANEG_ENABLE \ 614 | TBICR_FULL_DUPLEX \ 615 | TBICR_SPEED1_SET \ 616 ) 617 618 #endif /* CONFIG_TSEC_ENET */ 619 620 /* SATA */ 621 #define CONFIG_FSL_SATA_V2 622 623 #ifdef CONFIG_FSL_SATA 624 #define CONFIG_SYS_SATA_MAX_DEVICE 2 625 #define CONFIG_SATA1 626 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 627 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 628 #define CONFIG_SATA2 629 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 630 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 631 632 #define CONFIG_LBA48 633 #endif /* #ifdef CONFIG_FSL_SATA */ 634 635 #ifdef CONFIG_MMC 636 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 637 #endif 638 639 #define CONFIG_HAS_FSL_DR_USB 640 641 #if defined(CONFIG_HAS_FSL_DR_USB) 642 #ifdef CONFIG_USB_EHCI_HCD 643 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 644 #define CONFIG_USB_EHCI_FSL 645 #endif 646 #endif 647 648 /* 649 * Environment 650 */ 651 #if defined(CONFIG_SDCARD) 652 #define CONFIG_FSL_FIXED_MMC_LOCATION 653 #define CONFIG_SYS_MMC_ENV_DEV 0 654 #define CONFIG_ENV_SIZE 0x2000 655 #elif defined(CONFIG_SPIFLASH) 656 #define CONFIG_ENV_SPI_BUS 0 657 #define CONFIG_ENV_SPI_CS 0 658 #define CONFIG_ENV_SPI_MAX_HZ 10000000 659 #define CONFIG_ENV_SPI_MODE 0 660 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 661 #define CONFIG_ENV_SECT_SIZE 0x10000 662 #define CONFIG_ENV_SIZE 0x2000 663 #elif defined(CONFIG_NAND) 664 #ifdef CONFIG_TPL_BUILD 665 #define CONFIG_ENV_SIZE 0x2000 666 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 667 #else 668 #if defined(CONFIG_TARGET_P1010RDB_PA) 669 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 670 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 671 #elif defined(CONFIG_TARGET_P1010RDB_PB) 672 #define CONFIG_ENV_SIZE (16 * 1024) 673 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 674 #endif 675 #endif 676 #define CONFIG_ENV_OFFSET (1024 * 1024) 677 #elif defined(CONFIG_SYS_RAMBOOT) 678 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 679 #define CONFIG_ENV_SIZE 0x2000 680 #else 681 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 682 #define CONFIG_ENV_SIZE 0x2000 683 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 684 #endif 685 686 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 687 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 688 689 #undef CONFIG_WATCHDOG /* watchdog disabled */ 690 691 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ 692 || defined(CONFIG_FSL_SATA) 693 #endif 694 695 /* 696 * Miscellaneous configurable options 697 */ 698 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 699 700 /* 701 * For booting Linux, the board info and command line data 702 * have to be in the first 64 MB of memory, since this is 703 * the maximum mapped by the Linux kernel during initialization. 704 */ 705 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 706 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 707 708 #if defined(CONFIG_CMD_KGDB) 709 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 710 #endif 711 712 /* 713 * Environment Configuration 714 */ 715 716 #if defined(CONFIG_TSEC_ENET) 717 #define CONFIG_HAS_ETH0 718 #define CONFIG_HAS_ETH1 719 #define CONFIG_HAS_ETH2 720 #endif 721 722 #define CONFIG_ROOTPATH "/opt/nfsroot" 723 #define CONFIG_BOOTFILE "uImage" 724 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 725 726 /* default location for tftp and bootm */ 727 #define CONFIG_LOADADDR 1000000 728 729 #define CONFIG_EXTRA_ENV_SETTINGS \ 730 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 731 "netdev=eth0\0" \ 732 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 733 "loadaddr=1000000\0" \ 734 "consoledev=ttyS0\0" \ 735 "ramdiskaddr=2000000\0" \ 736 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 737 "fdtaddr=1e00000\0" \ 738 "fdtfile=p1010rdb.dtb\0" \ 739 "bdev=sda1\0" \ 740 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 741 "othbootargs=ramdisk_size=600000\0" \ 742 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 743 "console=$consoledev,$baudrate $othbootargs; " \ 744 "usb start;" \ 745 "fatload usb 0:2 $loadaddr $bootfile;" \ 746 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 747 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 748 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 749 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 750 "console=$consoledev,$baudrate $othbootargs; " \ 751 "usb start;" \ 752 "ext2load usb 0:4 $loadaddr $bootfile;" \ 753 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 754 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 755 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 756 CONFIG_BOOTMODE 757 758 #if defined(CONFIG_TARGET_P1010RDB_PA) 759 #define CONFIG_BOOTMODE \ 760 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 761 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 762 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 763 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 764 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 765 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 766 767 #elif defined(CONFIG_TARGET_P1010RDB_PB) 768 #define CONFIG_BOOTMODE \ 769 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 770 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 771 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 772 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 773 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 774 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 775 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 776 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 777 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 778 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 779 #endif 780 781 #define CONFIG_RAMBOOTCOMMAND \ 782 "setenv bootargs root=/dev/ram rw " \ 783 "console=$consoledev,$baudrate $othbootargs; " \ 784 "tftp $ramdiskaddr $ramdiskfile;" \ 785 "tftp $loadaddr $bootfile;" \ 786 "tftp $fdtaddr $fdtfile;" \ 787 "bootm $loadaddr $ramdiskaddr $fdtaddr" 788 789 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 790 791 #include <asm/fsl_secure_boot.h> 792 793 #endif /* __CONFIG_H */ 794