1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/config_mpc85xx.h> 15 #define CONFIG_NAND_FSL_IFC 16 17 #ifdef CONFIG_SDCARD 18 #define CONFIG_SPL_MMC_MINIMAL 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 21 #define CONFIG_SYS_TEXT_BASE 0x11001000 22 #define CONFIG_SPL_TEXT_BASE 0xD0001000 23 #define CONFIG_SPL_PAD_TO 0x18000 24 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 25 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 31 #define CONFIG_SPL_MMC_BOOT 32 #ifdef CONFIG_SPL_BUILD 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #endif 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #ifdef CONFIG_SECURE_BOOT 39 #define CONFIG_RAMBOOT_SPIFLASH 40 #define CONFIG_SYS_TEXT_BASE 0x11000000 41 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 42 #else 43 #define CONFIG_SPL_SPI_FLASH_MINIMAL 44 #define CONFIG_SPL_FLUSH_IMAGE 45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 46 #define CONFIG_SYS_TEXT_BASE 0x11001000 47 #define CONFIG_SPL_TEXT_BASE 0xD0001000 48 #define CONFIG_SPL_PAD_TO 0x18000 49 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 56 #define CONFIG_SPL_SPI_BOOT 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #endif 60 #endif 61 #endif 62 63 #ifdef CONFIG_NAND 64 #ifdef CONFIG_SECURE_BOOT 65 #define CONFIG_SPL_INIT_MINIMAL 66 #define CONFIG_SPL_NAND_BOOT 67 #define CONFIG_SPL_FLUSH_IMAGE 68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 69 70 #define CONFIG_SYS_TEXT_BASE 0x00201000 71 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 72 #define CONFIG_SPL_MAX_SIZE 8192 73 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 74 #define CONFIG_SPL_RELOC_STACK 0x00100000 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 76 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 77 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 78 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 80 #else 81 #ifdef CONFIG_TPL_BUILD 82 #define CONFIG_SPL_NAND_BOOT 83 #define CONFIG_SPL_FLUSH_IMAGE 84 #define CONFIG_SPL_NAND_INIT 85 #define CONFIG_SPL_COMMON_INIT_DDR 86 #define CONFIG_SPL_MAX_SIZE (128 << 10) 87 #define CONFIG_SPL_TEXT_BASE 0xD0001000 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 90 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 91 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 92 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 93 #elif defined(CONFIG_SPL_BUILD) 94 #define CONFIG_SPL_INIT_MINIMAL 95 #define CONFIG_SPL_NAND_MINIMAL 96 #define CONFIG_SPL_FLUSH_IMAGE 97 #define CONFIG_SPL_TEXT_BASE 0xff800000 98 #define CONFIG_SPL_MAX_SIZE 8192 99 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 100 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 101 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 103 #endif 104 #define CONFIG_SPL_PAD_TO 0x20000 105 #define CONFIG_TPL_PAD_TO 0x20000 106 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 107 #define CONFIG_SYS_TEXT_BASE 0x11001000 108 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 109 #endif 110 #endif 111 112 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 113 #define CONFIG_RAMBOOT_NAND 114 #define CONFIG_SYS_TEXT_BASE 0x11000000 115 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 116 #endif 117 118 #ifndef CONFIG_SYS_TEXT_BASE 119 #define CONFIG_SYS_TEXT_BASE 0xeff40000 120 #endif 121 122 #ifndef CONFIG_RESET_VECTOR_ADDRESS 123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 124 #endif 125 126 #ifdef CONFIG_SPL_BUILD 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 128 #else 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 #endif 131 132 /* High Level Configuration Options */ 133 #define CONFIG_FSL_IFC /* Enable IFC Support */ 134 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 135 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 136 137 #if defined(CONFIG_PCI) 138 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 139 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 140 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 141 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 142 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 143 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 144 145 #define CONFIG_CMD_PCI 146 147 /* 148 * PCI Windows 149 * Memory space is mapped 1-1, but I/O space must start from 0. 150 */ 151 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 152 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 153 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 154 #ifdef CONFIG_PHYS_64BIT 155 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 156 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 157 #else 158 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 159 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 160 #endif 161 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 162 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 163 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 164 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 167 #else 168 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 169 #endif 170 171 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 172 #if defined(CONFIG_TARGET_P1010RDB_PA) 173 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 174 #elif defined(CONFIG_TARGET_P1010RDB_PB) 175 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 176 #endif 177 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 178 #ifdef CONFIG_PHYS_64BIT 179 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 180 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 181 #else 182 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 183 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 184 #endif 185 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 186 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 187 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 188 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 189 #ifdef CONFIG_PHYS_64BIT 190 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 191 #else 192 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 193 #endif 194 195 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 196 #define CONFIG_DOS_PARTITION 197 #endif 198 199 #define CONFIG_TSEC_ENET 200 #define CONFIG_ENV_OVERWRITE 201 202 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 203 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 204 205 #define CONFIG_MISC_INIT_R 206 #define CONFIG_HWCONFIG 207 /* 208 * These can be toggled for performance analysis, otherwise use default. 209 */ 210 #define CONFIG_L2_CACHE /* toggle L2 cache */ 211 #define CONFIG_BTB /* toggle branch predition */ 212 213 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 214 215 #define CONFIG_ENABLE_36BIT_PHYS 216 217 #ifdef CONFIG_PHYS_64BIT 218 #define CONFIG_ADDR_MAP 1 219 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 220 #endif 221 222 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 223 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 224 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 225 226 /* DDR Setup */ 227 #define CONFIG_SYS_DDR_RAW_TIMING 228 #define CONFIG_DDR_SPD 229 #define CONFIG_SYS_SPD_BUS_NUM 1 230 #define SPD_EEPROM_ADDRESS 0x52 231 232 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 233 234 #ifndef __ASSEMBLY__ 235 extern unsigned long get_sdram_size(void); 236 #endif 237 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 238 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 239 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 240 241 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 242 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 243 244 /* DDR3 Controller Settings */ 245 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 246 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 247 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 248 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 249 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 250 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 251 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 252 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 253 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 254 #define CONFIG_SYS_DDR_RCW_1 0x00000000 255 #define CONFIG_SYS_DDR_RCW_2 0x00000000 256 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 257 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 258 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 259 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 260 261 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 262 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 263 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 264 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 265 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 266 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 267 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 268 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 269 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 270 271 /* settings for DDR3 at 667MT/s */ 272 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 273 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 274 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 275 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 276 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 277 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 278 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 279 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 280 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 281 282 #define CONFIG_SYS_CCSRBAR 0xffe00000 283 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 284 285 /* Don't relocate CCSRBAR while in NAND_SPL */ 286 #ifdef CONFIG_SPL_BUILD 287 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 288 #endif 289 290 /* 291 * Memory map 292 * 293 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 294 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 295 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 296 * 297 * Localbus non-cacheable 298 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 299 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 300 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 301 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 302 */ 303 304 /* 305 * IFC Definitions 306 */ 307 /* NOR Flash on IFC */ 308 #ifdef CONFIG_SPL_BUILD 309 #define CONFIG_SYS_NO_FLASH 310 #endif 311 312 #define CONFIG_SYS_FLASH_BASE 0xee000000 313 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 314 315 #ifdef CONFIG_PHYS_64BIT 316 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 317 #else 318 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 319 #endif 320 321 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 322 CSPR_PORT_SIZE_16 | \ 323 CSPR_MSEL_NOR | \ 324 CSPR_V) 325 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 326 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 327 /* NOR Flash Timing Params */ 328 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 329 FTIM0_NOR_TEADC(0x5) | \ 330 FTIM0_NOR_TEAHC(0x5) 331 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 332 FTIM1_NOR_TRAD_NOR(0x0f) 333 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 334 FTIM2_NOR_TCH(0x4) | \ 335 FTIM2_NOR_TWP(0x1c) 336 #define CONFIG_SYS_NOR_FTIM3 0x0 337 338 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 339 #define CONFIG_SYS_FLASH_QUIET_TEST 340 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 341 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 342 343 #undef CONFIG_SYS_FLASH_CHECKSUM 344 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 345 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 346 347 /* CFI for NOR Flash */ 348 #define CONFIG_FLASH_CFI_DRIVER 349 #define CONFIG_SYS_FLASH_CFI 350 #define CONFIG_SYS_FLASH_EMPTY_INFO 351 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 352 353 /* NAND Flash on IFC */ 354 #define CONFIG_SYS_NAND_BASE 0xff800000 355 #ifdef CONFIG_PHYS_64BIT 356 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 357 #else 358 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 359 #endif 360 361 #define CONFIG_MTD_DEVICE 362 #define CONFIG_MTD_PARTITION 363 #define CONFIG_CMD_MTDPARTS 364 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 365 #define MTDPARTS_DEFAULT \ 366 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 367 368 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 369 | CSPR_PORT_SIZE_8 \ 370 | CSPR_MSEL_NAND \ 371 | CSPR_V) 372 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 373 374 #if defined(CONFIG_TARGET_P1010RDB_PA) 375 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 376 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 377 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 378 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 379 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 380 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 381 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 382 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 383 384 #elif defined(CONFIG_TARGET_P1010RDB_PB) 385 #define CONFIG_SYS_NAND_ONFI_DETECTION 386 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 387 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 388 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 389 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 390 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 391 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 392 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 393 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 394 #endif 395 396 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 397 #define CONFIG_SYS_MAX_NAND_DEVICE 1 398 #define CONFIG_CMD_NAND 399 400 #if defined(CONFIG_TARGET_P1010RDB_PA) 401 /* NAND Flash Timing Params */ 402 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 403 FTIM0_NAND_TWP(0x0C) | \ 404 FTIM0_NAND_TWCHT(0x04) | \ 405 FTIM0_NAND_TWH(0x05) 406 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 407 FTIM1_NAND_TWBE(0x1d) | \ 408 FTIM1_NAND_TRR(0x07) | \ 409 FTIM1_NAND_TRP(0x0c) 410 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 411 FTIM2_NAND_TREH(0x05) | \ 412 FTIM2_NAND_TWHRE(0x0f) 413 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 414 415 #elif defined(CONFIG_TARGET_P1010RDB_PB) 416 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 417 /* ONFI NAND Flash mode0 Timing Params */ 418 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 419 FTIM0_NAND_TWP(0x18) | \ 420 FTIM0_NAND_TWCHT(0x07) | \ 421 FTIM0_NAND_TWH(0x0a)) 422 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 423 FTIM1_NAND_TWBE(0x39) | \ 424 FTIM1_NAND_TRR(0x0e) | \ 425 FTIM1_NAND_TRP(0x18)) 426 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 427 FTIM2_NAND_TREH(0x0a) | \ 428 FTIM2_NAND_TWHRE(0x1e)) 429 #define CONFIG_SYS_NAND_FTIM3 0x0 430 #endif 431 432 #define CONFIG_SYS_NAND_DDR_LAW 11 433 434 /* Set up IFC registers for boot location NOR/NAND */ 435 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 436 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 437 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 438 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 439 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 440 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 441 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 442 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 443 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 444 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 445 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 446 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 447 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 448 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 449 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 450 #else 451 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 452 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 453 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 454 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 455 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 456 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 457 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 458 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 459 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 460 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 461 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 462 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 463 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 464 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 465 #endif 466 467 /* CPLD on IFC */ 468 #define CONFIG_SYS_CPLD_BASE 0xffb00000 469 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 472 #else 473 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 474 #endif 475 476 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 477 | CSPR_PORT_SIZE_8 \ 478 | CSPR_MSEL_GPCM \ 479 | CSPR_V) 480 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 481 #define CONFIG_SYS_CSOR3 0x0 482 /* CPLD Timing parameters for IFC CS3 */ 483 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 484 FTIM0_GPCM_TEADC(0x0e) | \ 485 FTIM0_GPCM_TEAHC(0x0e)) 486 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 487 FTIM1_GPCM_TRAD(0x1f)) 488 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 489 FTIM2_GPCM_TCH(0x8) | \ 490 FTIM2_GPCM_TWP(0x1f)) 491 #define CONFIG_SYS_CS3_FTIM3 0x0 492 493 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 494 defined(CONFIG_RAMBOOT_NAND) 495 #define CONFIG_SYS_RAMBOOT 496 #define CONFIG_SYS_EXTRA_ENV_RELOC 497 #else 498 #undef CONFIG_SYS_RAMBOOT 499 #endif 500 501 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 502 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 503 #define CONFIG_A003399_NOR_WORKAROUND 504 #endif 505 #endif 506 507 #define CONFIG_BOARD_EARLY_INIT_R 508 509 #define CONFIG_SYS_INIT_RAM_LOCK 510 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 511 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 512 513 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 514 - GENERATED_GBL_DATA_SIZE) 515 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 516 517 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 518 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 519 520 /* 521 * Config the L2 Cache as L2 SRAM 522 */ 523 #if defined(CONFIG_SPL_BUILD) 524 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 525 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 526 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 527 #define CONFIG_SYS_L2_SIZE (256 << 10) 528 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 529 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 530 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 531 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 532 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 533 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 534 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 535 #elif defined(CONFIG_NAND) 536 #ifdef CONFIG_TPL_BUILD 537 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 538 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 539 #define CONFIG_SYS_L2_SIZE (256 << 10) 540 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 541 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 542 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 543 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 544 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 545 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 546 #else 547 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 548 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 549 #define CONFIG_SYS_L2_SIZE (256 << 10) 550 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 551 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 552 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 553 #endif 554 #endif 555 #endif 556 557 /* Serial Port */ 558 #define CONFIG_CONS_INDEX 1 559 #undef CONFIG_SERIAL_SOFTWARE_FIFO 560 #define CONFIG_SYS_NS16550_SERIAL 561 #define CONFIG_SYS_NS16550_REG_SIZE 1 562 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 563 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 564 #define CONFIG_NS16550_MIN_FUNCTIONS 565 #endif 566 567 #define CONFIG_SYS_BAUDRATE_TABLE \ 568 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 569 570 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 571 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 572 573 /* I2C */ 574 #define CONFIG_SYS_I2C 575 #define CONFIG_SYS_I2C_FSL 576 #define CONFIG_SYS_FSL_I2C_SPEED 400000 577 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 578 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 579 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 580 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 581 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 582 #define I2C_PCA9557_ADDR1 0x18 583 #define I2C_PCA9557_ADDR2 0x19 584 #define I2C_PCA9557_BUS_NUM 0 585 586 /* I2C EEPROM */ 587 #if defined(CONFIG_TARGET_P1010RDB_PB) 588 #define CONFIG_ID_EEPROM 589 #ifdef CONFIG_ID_EEPROM 590 #define CONFIG_SYS_I2C_EEPROM_NXID 591 #endif 592 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 593 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 594 #define CONFIG_SYS_EEPROM_BUS_NUM 0 595 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 596 #endif 597 /* enable read and write access to EEPROM */ 598 #define CONFIG_CMD_EEPROM 599 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 600 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 601 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 602 603 /* RTC */ 604 #define CONFIG_RTC_PT7C4338 605 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 606 607 /* 608 * SPI interface will not be available in case of NAND boot SPI CS0 will be 609 * used for SLIC 610 */ 611 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 612 /* eSPI - Enhanced SPI */ 613 #define CONFIG_SF_DEFAULT_SPEED 10000000 614 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 615 #endif 616 617 #if defined(CONFIG_TSEC_ENET) 618 #define CONFIG_MII /* MII PHY management */ 619 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 620 #define CONFIG_TSEC1 1 621 #define CONFIG_TSEC1_NAME "eTSEC1" 622 #define CONFIG_TSEC2 1 623 #define CONFIG_TSEC2_NAME "eTSEC2" 624 #define CONFIG_TSEC3 1 625 #define CONFIG_TSEC3_NAME "eTSEC3" 626 627 #define TSEC1_PHY_ADDR 1 628 #define TSEC2_PHY_ADDR 0 629 #define TSEC3_PHY_ADDR 2 630 631 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 632 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 633 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 634 635 #define TSEC1_PHYIDX 0 636 #define TSEC2_PHYIDX 0 637 #define TSEC3_PHYIDX 0 638 639 #define CONFIG_ETHPRIME "eTSEC1" 640 641 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 642 643 /* TBI PHY configuration for SGMII mode */ 644 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 645 TBICR_PHY_RESET \ 646 | TBICR_ANEG_ENABLE \ 647 | TBICR_FULL_DUPLEX \ 648 | TBICR_SPEED1_SET \ 649 ) 650 651 #endif /* CONFIG_TSEC_ENET */ 652 653 /* SATA */ 654 #define CONFIG_FSL_SATA 655 #define CONFIG_FSL_SATA_V2 656 #define CONFIG_LIBATA 657 658 #ifdef CONFIG_FSL_SATA 659 #define CONFIG_SYS_SATA_MAX_DEVICE 2 660 #define CONFIG_SATA1 661 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 662 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 663 #define CONFIG_SATA2 664 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 665 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 666 667 #define CONFIG_CMD_SATA 668 #define CONFIG_LBA48 669 #endif /* #ifdef CONFIG_FSL_SATA */ 670 671 #ifdef CONFIG_MMC 672 #define CONFIG_DOS_PARTITION 673 #define CONFIG_FSL_ESDHC 674 #define CONFIG_GENERIC_MMC 675 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 676 #endif 677 678 #define CONFIG_HAS_FSL_DR_USB 679 680 #if defined(CONFIG_HAS_FSL_DR_USB) 681 #define CONFIG_USB_EHCI 682 683 #ifdef CONFIG_USB_EHCI 684 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 685 #define CONFIG_USB_EHCI_FSL 686 #endif 687 #endif 688 689 /* 690 * Environment 691 */ 692 #if defined(CONFIG_SDCARD) 693 #define CONFIG_ENV_IS_IN_MMC 694 #define CONFIG_FSL_FIXED_MMC_LOCATION 695 #define CONFIG_SYS_MMC_ENV_DEV 0 696 #define CONFIG_ENV_SIZE 0x2000 697 #elif defined(CONFIG_SPIFLASH) 698 #define CONFIG_ENV_IS_IN_SPI_FLASH 699 #define CONFIG_ENV_SPI_BUS 0 700 #define CONFIG_ENV_SPI_CS 0 701 #define CONFIG_ENV_SPI_MAX_HZ 10000000 702 #define CONFIG_ENV_SPI_MODE 0 703 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 704 #define CONFIG_ENV_SECT_SIZE 0x10000 705 #define CONFIG_ENV_SIZE 0x2000 706 #elif defined(CONFIG_NAND) 707 #define CONFIG_ENV_IS_IN_NAND 708 #ifdef CONFIG_TPL_BUILD 709 #define CONFIG_ENV_SIZE 0x2000 710 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 711 #else 712 #if defined(CONFIG_TARGET_P1010RDB_PA) 713 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 714 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 715 #elif defined(CONFIG_TARGET_P1010RDB_PB) 716 #define CONFIG_ENV_SIZE (16 * 1024) 717 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 718 #endif 719 #endif 720 #define CONFIG_ENV_OFFSET (1024 * 1024) 721 #elif defined(CONFIG_SYS_RAMBOOT) 722 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 723 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 724 #define CONFIG_ENV_SIZE 0x2000 725 #else 726 #define CONFIG_ENV_IS_IN_FLASH 727 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 728 #define CONFIG_ENV_SIZE 0x2000 729 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 730 #endif 731 732 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 733 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 734 735 /* 736 * Command line configuration. 737 */ 738 #define CONFIG_CMD_DATE 739 #define CONFIG_CMD_ERRATA 740 #define CONFIG_CMD_IRQ 741 #define CONFIG_CMD_REGINFO 742 743 #undef CONFIG_WATCHDOG /* watchdog disabled */ 744 745 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 746 || defined(CONFIG_FSL_SATA) 747 #define CONFIG_DOS_PARTITION 748 #endif 749 750 /* Hash command with SHA acceleration supported in hardware */ 751 #ifdef CONFIG_FSL_CAAM 752 #define CONFIG_CMD_HASH 753 #define CONFIG_SHA_HW_ACCEL 754 #endif 755 756 /* 757 * Miscellaneous configurable options 758 */ 759 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 760 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 761 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 762 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 763 764 #if defined(CONFIG_CMD_KGDB) 765 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 766 #else 767 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 768 #endif 769 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 770 /* Print Buffer Size */ 771 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 772 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 773 774 /* 775 * For booting Linux, the board info and command line data 776 * have to be in the first 64 MB of memory, since this is 777 * the maximum mapped by the Linux kernel during initialization. 778 */ 779 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 780 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 781 782 #if defined(CONFIG_CMD_KGDB) 783 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 784 #endif 785 786 /* 787 * Environment Configuration 788 */ 789 790 #if defined(CONFIG_TSEC_ENET) 791 #define CONFIG_HAS_ETH0 792 #define CONFIG_HAS_ETH1 793 #define CONFIG_HAS_ETH2 794 #endif 795 796 #define CONFIG_ROOTPATH "/opt/nfsroot" 797 #define CONFIG_BOOTFILE "uImage" 798 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 799 800 /* default location for tftp and bootm */ 801 #define CONFIG_LOADADDR 1000000 802 803 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 804 805 #define CONFIG_BAUDRATE 115200 806 807 #define CONFIG_EXTRA_ENV_SETTINGS \ 808 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 809 "netdev=eth0\0" \ 810 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 811 "loadaddr=1000000\0" \ 812 "consoledev=ttyS0\0" \ 813 "ramdiskaddr=2000000\0" \ 814 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 815 "fdtaddr=1e00000\0" \ 816 "fdtfile=p1010rdb.dtb\0" \ 817 "bdev=sda1\0" \ 818 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 819 "othbootargs=ramdisk_size=600000\0" \ 820 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 821 "console=$consoledev,$baudrate $othbootargs; " \ 822 "usb start;" \ 823 "fatload usb 0:2 $loadaddr $bootfile;" \ 824 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 825 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 826 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 827 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 828 "console=$consoledev,$baudrate $othbootargs; " \ 829 "usb start;" \ 830 "ext2load usb 0:4 $loadaddr $bootfile;" \ 831 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 832 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 833 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 834 CONFIG_BOOTMODE 835 836 #if defined(CONFIG_TARGET_P1010RDB_PA) 837 #define CONFIG_BOOTMODE \ 838 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 839 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 840 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 841 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 842 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 843 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 844 845 #elif defined(CONFIG_TARGET_P1010RDB_PB) 846 #define CONFIG_BOOTMODE \ 847 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 848 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 849 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 850 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 851 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 852 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 853 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 854 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 855 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 856 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 857 #endif 858 859 #define CONFIG_RAMBOOTCOMMAND \ 860 "setenv bootargs root=/dev/ram rw " \ 861 "console=$consoledev,$baudrate $othbootargs; " \ 862 "tftp $ramdiskaddr $ramdiskfile;" \ 863 "tftp $loadaddr $bootfile;" \ 864 "tftp $fdtaddr $fdtfile;" \ 865 "bootm $loadaddr $ramdiskaddr $fdtaddr" 866 867 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 868 869 #include <asm/fsl_secure_boot.h> 870 871 #endif /* __CONFIG_H */ 872