1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/config_mpc85xx.h> 15 #define CONFIG_NAND_FSL_IFC 16 17 #ifdef CONFIG_SDCARD 18 #define CONFIG_SPL_MMC_MINIMAL 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 21 #define CONFIG_SYS_TEXT_BASE 0x11001000 22 #define CONFIG_SPL_TEXT_BASE 0xD0001000 23 #define CONFIG_SPL_PAD_TO 0x18000 24 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 25 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 31 #define CONFIG_SPL_MMC_BOOT 32 #ifdef CONFIG_SPL_BUILD 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #endif 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #ifdef CONFIG_SECURE_BOOT 39 #define CONFIG_RAMBOOT_SPIFLASH 40 #define CONFIG_SYS_TEXT_BASE 0x11000000 41 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 42 #else 43 #define CONFIG_SPL_SPI_FLASH_MINIMAL 44 #define CONFIG_SPL_FLUSH_IMAGE 45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 46 #define CONFIG_SYS_TEXT_BASE 0x11001000 47 #define CONFIG_SPL_TEXT_BASE 0xD0001000 48 #define CONFIG_SPL_PAD_TO 0x18000 49 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 56 #define CONFIG_SPL_SPI_BOOT 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #endif 60 #endif 61 #endif 62 63 #ifdef CONFIG_NAND 64 #ifdef CONFIG_SECURE_BOOT 65 #define CONFIG_SPL_INIT_MINIMAL 66 #define CONFIG_SPL_NAND_BOOT 67 #define CONFIG_SPL_FLUSH_IMAGE 68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 69 70 #define CONFIG_SYS_TEXT_BASE 0x00201000 71 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 72 #define CONFIG_SPL_MAX_SIZE 8192 73 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 74 #define CONFIG_SPL_RELOC_STACK 0x00100000 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 76 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 77 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 78 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 80 #else 81 #ifdef CONFIG_TPL_BUILD 82 #define CONFIG_SPL_NAND_BOOT 83 #define CONFIG_SPL_FLUSH_IMAGE 84 #define CONFIG_SPL_NAND_INIT 85 #define CONFIG_SPL_COMMON_INIT_DDR 86 #define CONFIG_SPL_MAX_SIZE (128 << 10) 87 #define CONFIG_SPL_TEXT_BASE 0xD0001000 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 90 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 91 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 92 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 93 #elif defined(CONFIG_SPL_BUILD) 94 #define CONFIG_SPL_INIT_MINIMAL 95 #define CONFIG_SPL_NAND_MINIMAL 96 #define CONFIG_SPL_FLUSH_IMAGE 97 #define CONFIG_SPL_TEXT_BASE 0xff800000 98 #define CONFIG_SPL_MAX_SIZE 8192 99 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 100 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 101 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 103 #endif 104 #define CONFIG_SPL_PAD_TO 0x20000 105 #define CONFIG_TPL_PAD_TO 0x20000 106 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 107 #define CONFIG_SYS_TEXT_BASE 0x11001000 108 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 109 #endif 110 #endif 111 112 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 113 #define CONFIG_RAMBOOT_NAND 114 #define CONFIG_SYS_TEXT_BASE 0x11000000 115 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 116 #endif 117 118 #ifndef CONFIG_SYS_TEXT_BASE 119 #define CONFIG_SYS_TEXT_BASE 0xeff40000 120 #endif 121 122 #ifndef CONFIG_RESET_VECTOR_ADDRESS 123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 124 #endif 125 126 #ifdef CONFIG_SPL_BUILD 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 128 #else 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 #endif 131 132 /* High Level Configuration Options */ 133 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 134 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 135 136 #if defined(CONFIG_PCI) 137 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 138 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 139 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 140 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 141 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 142 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 143 144 #define CONFIG_CMD_PCI 145 146 /* 147 * PCI Windows 148 * Memory space is mapped 1-1, but I/O space must start from 0. 149 */ 150 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 151 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 152 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 155 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 156 #else 157 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 158 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 159 #endif 160 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 161 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 162 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 163 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 164 #ifdef CONFIG_PHYS_64BIT 165 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 166 #else 167 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 168 #endif 169 170 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 171 #if defined(CONFIG_TARGET_P1010RDB_PA) 172 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 173 #elif defined(CONFIG_TARGET_P1010RDB_PB) 174 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 175 #endif 176 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 177 #ifdef CONFIG_PHYS_64BIT 178 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 179 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 180 #else 181 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 182 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 183 #endif 184 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 185 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 186 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 187 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 188 #ifdef CONFIG_PHYS_64BIT 189 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 190 #else 191 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 192 #endif 193 194 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 195 #endif 196 197 #define CONFIG_TSEC_ENET 198 #define CONFIG_ENV_OVERWRITE 199 200 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 201 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 202 203 #define CONFIG_MISC_INIT_R 204 #define CONFIG_HWCONFIG 205 /* 206 * These can be toggled for performance analysis, otherwise use default. 207 */ 208 #define CONFIG_L2_CACHE /* toggle L2 cache */ 209 #define CONFIG_BTB /* toggle branch predition */ 210 211 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 212 213 #define CONFIG_ENABLE_36BIT_PHYS 214 215 #ifdef CONFIG_PHYS_64BIT 216 #define CONFIG_ADDR_MAP 1 217 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 218 #endif 219 220 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 221 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 222 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 223 224 /* DDR Setup */ 225 #define CONFIG_SYS_DDR_RAW_TIMING 226 #define CONFIG_DDR_SPD 227 #define CONFIG_SYS_SPD_BUS_NUM 1 228 #define SPD_EEPROM_ADDRESS 0x52 229 230 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 231 232 #ifndef __ASSEMBLY__ 233 extern unsigned long get_sdram_size(void); 234 #endif 235 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 236 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 237 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 238 239 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 240 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 241 242 /* DDR3 Controller Settings */ 243 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 244 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 245 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 246 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 247 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 248 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 249 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 250 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 251 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 252 #define CONFIG_SYS_DDR_RCW_1 0x00000000 253 #define CONFIG_SYS_DDR_RCW_2 0x00000000 254 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 255 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 256 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 257 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 258 259 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 260 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 261 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 262 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 263 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 264 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 265 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 266 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 267 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 268 269 /* settings for DDR3 at 667MT/s */ 270 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 271 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 272 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 273 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 274 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 275 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 276 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 277 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 278 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 279 280 #define CONFIG_SYS_CCSRBAR 0xffe00000 281 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 282 283 /* Don't relocate CCSRBAR while in NAND_SPL */ 284 #ifdef CONFIG_SPL_BUILD 285 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 286 #endif 287 288 /* 289 * Memory map 290 * 291 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 292 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 293 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 294 * 295 * Localbus non-cacheable 296 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 297 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 298 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 299 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 300 */ 301 302 /* 303 * IFC Definitions 304 */ 305 /* NOR Flash on IFC */ 306 #ifdef CONFIG_SPL_BUILD 307 #define CONFIG_SYS_NO_FLASH 308 #endif 309 310 #define CONFIG_SYS_FLASH_BASE 0xee000000 311 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 312 313 #ifdef CONFIG_PHYS_64BIT 314 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 315 #else 316 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 317 #endif 318 319 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 320 CSPR_PORT_SIZE_16 | \ 321 CSPR_MSEL_NOR | \ 322 CSPR_V) 323 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 324 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 325 /* NOR Flash Timing Params */ 326 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 327 FTIM0_NOR_TEADC(0x5) | \ 328 FTIM0_NOR_TEAHC(0x5) 329 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 330 FTIM1_NOR_TRAD_NOR(0x0f) 331 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 332 FTIM2_NOR_TCH(0x4) | \ 333 FTIM2_NOR_TWP(0x1c) 334 #define CONFIG_SYS_NOR_FTIM3 0x0 335 336 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 337 #define CONFIG_SYS_FLASH_QUIET_TEST 338 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 339 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 340 341 #undef CONFIG_SYS_FLASH_CHECKSUM 342 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 343 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 344 345 /* CFI for NOR Flash */ 346 #define CONFIG_FLASH_CFI_DRIVER 347 #define CONFIG_SYS_FLASH_CFI 348 #define CONFIG_SYS_FLASH_EMPTY_INFO 349 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 350 351 /* NAND Flash on IFC */ 352 #define CONFIG_SYS_NAND_BASE 0xff800000 353 #ifdef CONFIG_PHYS_64BIT 354 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 355 #else 356 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 357 #endif 358 359 #define CONFIG_MTD_DEVICE 360 #define CONFIG_MTD_PARTITION 361 #define CONFIG_CMD_MTDPARTS 362 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 363 #define MTDPARTS_DEFAULT \ 364 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 365 366 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 367 | CSPR_PORT_SIZE_8 \ 368 | CSPR_MSEL_NAND \ 369 | CSPR_V) 370 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 371 372 #if defined(CONFIG_TARGET_P1010RDB_PA) 373 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 374 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 375 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 376 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 377 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 378 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 379 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 380 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 381 382 #elif defined(CONFIG_TARGET_P1010RDB_PB) 383 #define CONFIG_SYS_NAND_ONFI_DETECTION 384 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 385 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 386 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 387 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 388 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 389 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 390 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 391 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 392 #endif 393 394 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 395 #define CONFIG_SYS_MAX_NAND_DEVICE 1 396 #define CONFIG_CMD_NAND 397 398 #if defined(CONFIG_TARGET_P1010RDB_PA) 399 /* NAND Flash Timing Params */ 400 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 401 FTIM0_NAND_TWP(0x0C) | \ 402 FTIM0_NAND_TWCHT(0x04) | \ 403 FTIM0_NAND_TWH(0x05) 404 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 405 FTIM1_NAND_TWBE(0x1d) | \ 406 FTIM1_NAND_TRR(0x07) | \ 407 FTIM1_NAND_TRP(0x0c) 408 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 409 FTIM2_NAND_TREH(0x05) | \ 410 FTIM2_NAND_TWHRE(0x0f) 411 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 412 413 #elif defined(CONFIG_TARGET_P1010RDB_PB) 414 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 415 /* ONFI NAND Flash mode0 Timing Params */ 416 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 417 FTIM0_NAND_TWP(0x18) | \ 418 FTIM0_NAND_TWCHT(0x07) | \ 419 FTIM0_NAND_TWH(0x0a)) 420 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 421 FTIM1_NAND_TWBE(0x39) | \ 422 FTIM1_NAND_TRR(0x0e) | \ 423 FTIM1_NAND_TRP(0x18)) 424 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 425 FTIM2_NAND_TREH(0x0a) | \ 426 FTIM2_NAND_TWHRE(0x1e)) 427 #define CONFIG_SYS_NAND_FTIM3 0x0 428 #endif 429 430 #define CONFIG_SYS_NAND_DDR_LAW 11 431 432 /* Set up IFC registers for boot location NOR/NAND */ 433 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 434 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 435 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 436 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 437 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 438 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 439 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 440 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 441 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 442 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 443 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 444 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 445 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 446 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 447 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 448 #else 449 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 450 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 451 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 452 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 453 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 454 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 455 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 456 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 457 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 458 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 459 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 460 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 461 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 462 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 463 #endif 464 465 /* CPLD on IFC */ 466 #define CONFIG_SYS_CPLD_BASE 0xffb00000 467 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 470 #else 471 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 472 #endif 473 474 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 475 | CSPR_PORT_SIZE_8 \ 476 | CSPR_MSEL_GPCM \ 477 | CSPR_V) 478 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 479 #define CONFIG_SYS_CSOR3 0x0 480 /* CPLD Timing parameters for IFC CS3 */ 481 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 482 FTIM0_GPCM_TEADC(0x0e) | \ 483 FTIM0_GPCM_TEAHC(0x0e)) 484 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 485 FTIM1_GPCM_TRAD(0x1f)) 486 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 487 FTIM2_GPCM_TCH(0x8) | \ 488 FTIM2_GPCM_TWP(0x1f)) 489 #define CONFIG_SYS_CS3_FTIM3 0x0 490 491 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 492 defined(CONFIG_RAMBOOT_NAND) 493 #define CONFIG_SYS_RAMBOOT 494 #define CONFIG_SYS_EXTRA_ENV_RELOC 495 #else 496 #undef CONFIG_SYS_RAMBOOT 497 #endif 498 499 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 500 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 501 #define CONFIG_A003399_NOR_WORKAROUND 502 #endif 503 #endif 504 505 #define CONFIG_BOARD_EARLY_INIT_R 506 507 #define CONFIG_SYS_INIT_RAM_LOCK 508 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 509 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 510 511 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 512 - GENERATED_GBL_DATA_SIZE) 513 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 514 515 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 516 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 517 518 /* 519 * Config the L2 Cache as L2 SRAM 520 */ 521 #if defined(CONFIG_SPL_BUILD) 522 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 523 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 524 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 525 #define CONFIG_SYS_L2_SIZE (256 << 10) 526 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 527 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 528 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 529 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 530 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 531 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 532 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 533 #elif defined(CONFIG_NAND) 534 #ifdef CONFIG_TPL_BUILD 535 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 536 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 537 #define CONFIG_SYS_L2_SIZE (256 << 10) 538 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 539 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 540 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 541 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 542 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 543 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 544 #else 545 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 546 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 547 #define CONFIG_SYS_L2_SIZE (256 << 10) 548 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 549 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 550 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 551 #endif 552 #endif 553 #endif 554 555 /* Serial Port */ 556 #define CONFIG_CONS_INDEX 1 557 #undef CONFIG_SERIAL_SOFTWARE_FIFO 558 #define CONFIG_SYS_NS16550_SERIAL 559 #define CONFIG_SYS_NS16550_REG_SIZE 1 560 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 561 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 562 #define CONFIG_NS16550_MIN_FUNCTIONS 563 #endif 564 565 #define CONFIG_SYS_BAUDRATE_TABLE \ 566 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 567 568 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 569 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 570 571 /* I2C */ 572 #define CONFIG_SYS_I2C 573 #define CONFIG_SYS_I2C_FSL 574 #define CONFIG_SYS_FSL_I2C_SPEED 400000 575 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 576 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 577 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 578 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 579 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 580 #define I2C_PCA9557_ADDR1 0x18 581 #define I2C_PCA9557_ADDR2 0x19 582 #define I2C_PCA9557_BUS_NUM 0 583 584 /* I2C EEPROM */ 585 #if defined(CONFIG_TARGET_P1010RDB_PB) 586 #define CONFIG_ID_EEPROM 587 #ifdef CONFIG_ID_EEPROM 588 #define CONFIG_SYS_I2C_EEPROM_NXID 589 #endif 590 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 591 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 592 #define CONFIG_SYS_EEPROM_BUS_NUM 0 593 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 594 #endif 595 /* enable read and write access to EEPROM */ 596 #define CONFIG_CMD_EEPROM 597 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 598 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 599 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 600 601 /* RTC */ 602 #define CONFIG_RTC_PT7C4338 603 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 604 605 /* 606 * SPI interface will not be available in case of NAND boot SPI CS0 will be 607 * used for SLIC 608 */ 609 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 610 /* eSPI - Enhanced SPI */ 611 #define CONFIG_SF_DEFAULT_SPEED 10000000 612 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 613 #endif 614 615 #if defined(CONFIG_TSEC_ENET) 616 #define CONFIG_MII /* MII PHY management */ 617 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 618 #define CONFIG_TSEC1 1 619 #define CONFIG_TSEC1_NAME "eTSEC1" 620 #define CONFIG_TSEC2 1 621 #define CONFIG_TSEC2_NAME "eTSEC2" 622 #define CONFIG_TSEC3 1 623 #define CONFIG_TSEC3_NAME "eTSEC3" 624 625 #define TSEC1_PHY_ADDR 1 626 #define TSEC2_PHY_ADDR 0 627 #define TSEC3_PHY_ADDR 2 628 629 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 630 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 631 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 632 633 #define TSEC1_PHYIDX 0 634 #define TSEC2_PHYIDX 0 635 #define TSEC3_PHYIDX 0 636 637 #define CONFIG_ETHPRIME "eTSEC1" 638 639 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 640 641 /* TBI PHY configuration for SGMII mode */ 642 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 643 TBICR_PHY_RESET \ 644 | TBICR_ANEG_ENABLE \ 645 | TBICR_FULL_DUPLEX \ 646 | TBICR_SPEED1_SET \ 647 ) 648 649 #endif /* CONFIG_TSEC_ENET */ 650 651 /* SATA */ 652 #define CONFIG_FSL_SATA 653 #define CONFIG_FSL_SATA_V2 654 #define CONFIG_LIBATA 655 656 #ifdef CONFIG_FSL_SATA 657 #define CONFIG_SYS_SATA_MAX_DEVICE 2 658 #define CONFIG_SATA1 659 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 660 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 661 #define CONFIG_SATA2 662 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 663 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 664 665 #define CONFIG_CMD_SATA 666 #define CONFIG_LBA48 667 #endif /* #ifdef CONFIG_FSL_SATA */ 668 669 #ifdef CONFIG_MMC 670 #define CONFIG_FSL_ESDHC 671 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 672 #endif 673 674 #define CONFIG_HAS_FSL_DR_USB 675 676 #if defined(CONFIG_HAS_FSL_DR_USB) 677 #define CONFIG_USB_EHCI 678 679 #ifdef CONFIG_USB_EHCI 680 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 681 #define CONFIG_USB_EHCI_FSL 682 #endif 683 #endif 684 685 /* 686 * Environment 687 */ 688 #if defined(CONFIG_SDCARD) 689 #define CONFIG_ENV_IS_IN_MMC 690 #define CONFIG_FSL_FIXED_MMC_LOCATION 691 #define CONFIG_SYS_MMC_ENV_DEV 0 692 #define CONFIG_ENV_SIZE 0x2000 693 #elif defined(CONFIG_SPIFLASH) 694 #define CONFIG_ENV_IS_IN_SPI_FLASH 695 #define CONFIG_ENV_SPI_BUS 0 696 #define CONFIG_ENV_SPI_CS 0 697 #define CONFIG_ENV_SPI_MAX_HZ 10000000 698 #define CONFIG_ENV_SPI_MODE 0 699 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 700 #define CONFIG_ENV_SECT_SIZE 0x10000 701 #define CONFIG_ENV_SIZE 0x2000 702 #elif defined(CONFIG_NAND) 703 #define CONFIG_ENV_IS_IN_NAND 704 #ifdef CONFIG_TPL_BUILD 705 #define CONFIG_ENV_SIZE 0x2000 706 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 707 #else 708 #if defined(CONFIG_TARGET_P1010RDB_PA) 709 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 710 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 711 #elif defined(CONFIG_TARGET_P1010RDB_PB) 712 #define CONFIG_ENV_SIZE (16 * 1024) 713 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 714 #endif 715 #endif 716 #define CONFIG_ENV_OFFSET (1024 * 1024) 717 #elif defined(CONFIG_SYS_RAMBOOT) 718 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 719 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 720 #define CONFIG_ENV_SIZE 0x2000 721 #else 722 #define CONFIG_ENV_IS_IN_FLASH 723 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 724 #define CONFIG_ENV_SIZE 0x2000 725 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 726 #endif 727 728 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 729 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 730 731 /* 732 * Command line configuration. 733 */ 734 #define CONFIG_CMD_DATE 735 #define CONFIG_CMD_ERRATA 736 #define CONFIG_CMD_IRQ 737 #define CONFIG_CMD_REGINFO 738 739 #undef CONFIG_WATCHDOG /* watchdog disabled */ 740 741 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 742 || defined(CONFIG_FSL_SATA) 743 #endif 744 745 /* Hash command with SHA acceleration supported in hardware */ 746 #ifdef CONFIG_FSL_CAAM 747 #define CONFIG_CMD_HASH 748 #define CONFIG_SHA_HW_ACCEL 749 #endif 750 751 /* 752 * Miscellaneous configurable options 753 */ 754 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 755 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 756 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 757 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 758 759 #if defined(CONFIG_CMD_KGDB) 760 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 761 #else 762 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 763 #endif 764 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 765 /* Print Buffer Size */ 766 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 767 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 768 769 /* 770 * For booting Linux, the board info and command line data 771 * have to be in the first 64 MB of memory, since this is 772 * the maximum mapped by the Linux kernel during initialization. 773 */ 774 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 775 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 776 777 #if defined(CONFIG_CMD_KGDB) 778 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 779 #endif 780 781 /* 782 * Environment Configuration 783 */ 784 785 #if defined(CONFIG_TSEC_ENET) 786 #define CONFIG_HAS_ETH0 787 #define CONFIG_HAS_ETH1 788 #define CONFIG_HAS_ETH2 789 #endif 790 791 #define CONFIG_ROOTPATH "/opt/nfsroot" 792 #define CONFIG_BOOTFILE "uImage" 793 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 794 795 /* default location for tftp and bootm */ 796 #define CONFIG_LOADADDR 1000000 797 798 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 799 800 #define CONFIG_BAUDRATE 115200 801 802 #define CONFIG_EXTRA_ENV_SETTINGS \ 803 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 804 "netdev=eth0\0" \ 805 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 806 "loadaddr=1000000\0" \ 807 "consoledev=ttyS0\0" \ 808 "ramdiskaddr=2000000\0" \ 809 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 810 "fdtaddr=1e00000\0" \ 811 "fdtfile=p1010rdb.dtb\0" \ 812 "bdev=sda1\0" \ 813 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 814 "othbootargs=ramdisk_size=600000\0" \ 815 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 816 "console=$consoledev,$baudrate $othbootargs; " \ 817 "usb start;" \ 818 "fatload usb 0:2 $loadaddr $bootfile;" \ 819 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 820 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 821 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 822 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 823 "console=$consoledev,$baudrate $othbootargs; " \ 824 "usb start;" \ 825 "ext2load usb 0:4 $loadaddr $bootfile;" \ 826 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 827 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 828 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 829 CONFIG_BOOTMODE 830 831 #if defined(CONFIG_TARGET_P1010RDB_PA) 832 #define CONFIG_BOOTMODE \ 833 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 834 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 835 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 836 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 837 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 838 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 839 840 #elif defined(CONFIG_TARGET_P1010RDB_PB) 841 #define CONFIG_BOOTMODE \ 842 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 843 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 844 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 845 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 846 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 847 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 848 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 849 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 850 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 851 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 852 #endif 853 854 #define CONFIG_RAMBOOTCOMMAND \ 855 "setenv bootargs root=/dev/ram rw " \ 856 "console=$consoledev,$baudrate $othbootargs; " \ 857 "tftp $ramdiskaddr $ramdiskfile;" \ 858 "tftp $loadaddr $bootfile;" \ 859 "tftp $fdtaddr $fdtfile;" \ 860 "bootm $loadaddr $ramdiskaddr $fdtaddr" 861 862 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 863 864 #include <asm/fsl_secure_boot.h> 865 866 #endif /* __CONFIG_H */ 867