1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_E500 /* BOOKE e500 family */ 15 #include <asm/config_mpc85xx.h> 16 #define CONFIG_NAND_FSL_IFC 17 18 #ifdef CONFIG_SDCARD 19 #define CONFIG_SPL_MMC_MINIMAL 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_FSL_LAW /* Use common FSL init code */ 23 #define CONFIG_SYS_TEXT_BASE 0x11001000 24 #define CONFIG_SPL_TEXT_BASE 0xD0001000 25 #define CONFIG_SPL_PAD_TO 0x18000 26 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 27 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 28 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 29 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 30 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 31 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 32 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 33 #define CONFIG_SPL_MMC_BOOT 34 #ifdef CONFIG_SPL_BUILD 35 #define CONFIG_SPL_COMMON_INIT_DDR 36 #endif 37 #endif 38 39 #ifdef CONFIG_SPIFLASH 40 #ifdef CONFIG_SECURE_BOOT 41 #define CONFIG_RAMBOOT_SPIFLASH 42 #define CONFIG_SYS_TEXT_BASE 0x11000000 43 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 44 #else 45 #define CONFIG_SPL_SPI_FLASH_MINIMAL 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 #define CONFIG_FSL_LAW /* Use common FSL init code */ 49 #define CONFIG_SYS_TEXT_BASE 0x11001000 50 #define CONFIG_SPL_TEXT_BASE 0xD0001000 51 #define CONFIG_SPL_PAD_TO 0x18000 52 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 57 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 59 #define CONFIG_SPL_SPI_BOOT 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SPL_COMMON_INIT_DDR 62 #endif 63 #endif 64 #endif 65 66 #ifdef CONFIG_NAND 67 #ifdef CONFIG_SECURE_BOOT 68 #define CONFIG_SPL_INIT_MINIMAL 69 #define CONFIG_SPL_NAND_BOOT 70 #define CONFIG_SPL_FLUSH_IMAGE 71 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 72 73 #define CONFIG_SYS_TEXT_BASE 0x00201000 74 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 75 #define CONFIG_SPL_MAX_SIZE 8192 76 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 77 #define CONFIG_SPL_RELOC_STACK 0x00100000 78 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 79 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 80 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 81 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 83 #else 84 #ifdef CONFIG_TPL_BUILD 85 #define CONFIG_SPL_NAND_BOOT 86 #define CONFIG_SPL_FLUSH_IMAGE 87 #define CONFIG_SPL_NAND_INIT 88 #define CONFIG_SPL_COMMON_INIT_DDR 89 #define CONFIG_SPL_MAX_SIZE (128 << 10) 90 #define CONFIG_SPL_TEXT_BASE 0xD0001000 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 93 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 94 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 95 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 96 #elif defined(CONFIG_SPL_BUILD) 97 #define CONFIG_SPL_INIT_MINIMAL 98 #define CONFIG_SPL_NAND_MINIMAL 99 #define CONFIG_SPL_FLUSH_IMAGE 100 #define CONFIG_SPL_TEXT_BASE 0xff800000 101 #define CONFIG_SPL_MAX_SIZE 8192 102 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 103 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 104 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 105 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 106 #endif 107 #define CONFIG_SPL_PAD_TO 0x20000 108 #define CONFIG_TPL_PAD_TO 0x20000 109 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 110 #define CONFIG_SYS_TEXT_BASE 0x11001000 111 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 112 #endif 113 #endif 114 115 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 116 #define CONFIG_RAMBOOT_NAND 117 #define CONFIG_SYS_TEXT_BASE 0x11000000 118 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 119 #endif 120 121 #ifndef CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_TEXT_BASE 0xeff40000 123 #endif 124 125 #ifndef CONFIG_RESET_VECTOR_ADDRESS 126 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 127 #endif 128 129 #ifdef CONFIG_SPL_BUILD 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 131 #else 132 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 133 #endif 134 135 /* High Level Configuration Options */ 136 #define CONFIG_BOOKE /* BOOKE */ 137 #define CONFIG_E500 /* BOOKE e500 family */ 138 #define CONFIG_FSL_IFC /* Enable IFC Support */ 139 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 140 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 141 142 #if defined(CONFIG_PCI) 143 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 144 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 145 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 146 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 147 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 148 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 149 150 #define CONFIG_CMD_PCI 151 152 /* 153 * PCI Windows 154 * Memory space is mapped 1-1, but I/O space must start from 0. 155 */ 156 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 157 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 158 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 159 #ifdef CONFIG_PHYS_64BIT 160 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 161 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 162 #else 163 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 164 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 165 #endif 166 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 167 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 168 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 169 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 170 #ifdef CONFIG_PHYS_64BIT 171 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 172 #else 173 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 174 #endif 175 176 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 177 #if defined(CONFIG_TARGET_P1010RDB_PA) 178 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 179 #elif defined(CONFIG_TARGET_P1010RDB_PB) 180 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 181 #endif 182 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 183 #ifdef CONFIG_PHYS_64BIT 184 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 185 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 186 #else 187 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 188 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 189 #endif 190 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 191 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 192 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 193 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 194 #ifdef CONFIG_PHYS_64BIT 195 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 196 #else 197 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 198 #endif 199 200 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 201 #define CONFIG_DOS_PARTITION 202 #endif 203 204 #define CONFIG_FSL_LAW /* Use common FSL init code */ 205 #define CONFIG_TSEC_ENET 206 #define CONFIG_ENV_OVERWRITE 207 208 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 209 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 210 211 #define CONFIG_MISC_INIT_R 212 #define CONFIG_HWCONFIG 213 /* 214 * These can be toggled for performance analysis, otherwise use default. 215 */ 216 #define CONFIG_L2_CACHE /* toggle L2 cache */ 217 #define CONFIG_BTB /* toggle branch predition */ 218 219 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 220 221 #define CONFIG_ENABLE_36BIT_PHYS 222 223 #ifdef CONFIG_PHYS_64BIT 224 #define CONFIG_ADDR_MAP 1 225 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 226 #endif 227 228 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 229 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 230 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 231 232 /* DDR Setup */ 233 #define CONFIG_SYS_FSL_DDR3 234 #define CONFIG_SYS_DDR_RAW_TIMING 235 #define CONFIG_DDR_SPD 236 #define CONFIG_SYS_SPD_BUS_NUM 1 237 #define SPD_EEPROM_ADDRESS 0x52 238 239 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 240 241 #ifndef __ASSEMBLY__ 242 extern unsigned long get_sdram_size(void); 243 #endif 244 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 245 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 246 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 247 248 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 249 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 250 251 /* DDR3 Controller Settings */ 252 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 253 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 254 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 255 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 256 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 257 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 258 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 259 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 260 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 261 #define CONFIG_SYS_DDR_RCW_1 0x00000000 262 #define CONFIG_SYS_DDR_RCW_2 0x00000000 263 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 264 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 265 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 266 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 267 268 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 269 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 270 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 271 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 272 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 273 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 274 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 275 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 276 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 277 278 /* settings for DDR3 at 667MT/s */ 279 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 280 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 281 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 282 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 283 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 284 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 285 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 286 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 287 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 288 289 #define CONFIG_SYS_CCSRBAR 0xffe00000 290 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 291 292 /* Don't relocate CCSRBAR while in NAND_SPL */ 293 #ifdef CONFIG_SPL_BUILD 294 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 295 #endif 296 297 /* 298 * Memory map 299 * 300 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 301 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 302 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 303 * 304 * Localbus non-cacheable 305 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 306 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 307 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 308 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 309 */ 310 311 /* 312 * IFC Definitions 313 */ 314 /* NOR Flash on IFC */ 315 #ifdef CONFIG_SPL_BUILD 316 #define CONFIG_SYS_NO_FLASH 317 #endif 318 319 #define CONFIG_SYS_FLASH_BASE 0xee000000 320 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 321 322 #ifdef CONFIG_PHYS_64BIT 323 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 324 #else 325 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 326 #endif 327 328 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 329 CSPR_PORT_SIZE_16 | \ 330 CSPR_MSEL_NOR | \ 331 CSPR_V) 332 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 333 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 334 /* NOR Flash Timing Params */ 335 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 336 FTIM0_NOR_TEADC(0x5) | \ 337 FTIM0_NOR_TEAHC(0x5) 338 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 339 FTIM1_NOR_TRAD_NOR(0x0f) 340 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 341 FTIM2_NOR_TCH(0x4) | \ 342 FTIM2_NOR_TWP(0x1c) 343 #define CONFIG_SYS_NOR_FTIM3 0x0 344 345 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 346 #define CONFIG_SYS_FLASH_QUIET_TEST 347 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 348 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 349 350 #undef CONFIG_SYS_FLASH_CHECKSUM 351 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 352 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 353 354 /* CFI for NOR Flash */ 355 #define CONFIG_FLASH_CFI_DRIVER 356 #define CONFIG_SYS_FLASH_CFI 357 #define CONFIG_SYS_FLASH_EMPTY_INFO 358 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 359 360 /* NAND Flash on IFC */ 361 #define CONFIG_SYS_NAND_BASE 0xff800000 362 #ifdef CONFIG_PHYS_64BIT 363 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 364 #else 365 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 366 #endif 367 368 #define CONFIG_MTD_DEVICE 369 #define CONFIG_MTD_PARTITION 370 #define CONFIG_CMD_MTDPARTS 371 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 372 #define MTDPARTS_DEFAULT \ 373 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 374 375 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 376 | CSPR_PORT_SIZE_8 \ 377 | CSPR_MSEL_NAND \ 378 | CSPR_V) 379 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 380 381 #if defined(CONFIG_TARGET_P1010RDB_PA) 382 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 383 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 384 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 385 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 386 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 387 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 388 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 389 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 390 391 #elif defined(CONFIG_TARGET_P1010RDB_PB) 392 #define CONFIG_SYS_NAND_ONFI_DETECTION 393 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 394 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 395 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 396 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 397 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 398 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 399 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 400 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 401 #endif 402 403 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 404 #define CONFIG_SYS_MAX_NAND_DEVICE 1 405 #define CONFIG_CMD_NAND 406 407 #if defined(CONFIG_TARGET_P1010RDB_PA) 408 /* NAND Flash Timing Params */ 409 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 410 FTIM0_NAND_TWP(0x0C) | \ 411 FTIM0_NAND_TWCHT(0x04) | \ 412 FTIM0_NAND_TWH(0x05) 413 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 414 FTIM1_NAND_TWBE(0x1d) | \ 415 FTIM1_NAND_TRR(0x07) | \ 416 FTIM1_NAND_TRP(0x0c) 417 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 418 FTIM2_NAND_TREH(0x05) | \ 419 FTIM2_NAND_TWHRE(0x0f) 420 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 421 422 #elif defined(CONFIG_TARGET_P1010RDB_PB) 423 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 424 /* ONFI NAND Flash mode0 Timing Params */ 425 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 426 FTIM0_NAND_TWP(0x18) | \ 427 FTIM0_NAND_TWCHT(0x07) | \ 428 FTIM0_NAND_TWH(0x0a)) 429 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 430 FTIM1_NAND_TWBE(0x39) | \ 431 FTIM1_NAND_TRR(0x0e) | \ 432 FTIM1_NAND_TRP(0x18)) 433 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 434 FTIM2_NAND_TREH(0x0a) | \ 435 FTIM2_NAND_TWHRE(0x1e)) 436 #define CONFIG_SYS_NAND_FTIM3 0x0 437 #endif 438 439 #define CONFIG_SYS_NAND_DDR_LAW 11 440 441 /* Set up IFC registers for boot location NOR/NAND */ 442 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 443 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 444 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 445 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 446 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 447 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 448 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 449 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 450 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 451 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 452 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 453 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 454 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 455 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 456 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 457 #else 458 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 459 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 460 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 461 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 462 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 463 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 464 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 465 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 466 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 467 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 468 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 469 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 470 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 471 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 472 #endif 473 474 /* CPLD on IFC */ 475 #define CONFIG_SYS_CPLD_BASE 0xffb00000 476 477 #ifdef CONFIG_PHYS_64BIT 478 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 479 #else 480 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 481 #endif 482 483 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 484 | CSPR_PORT_SIZE_8 \ 485 | CSPR_MSEL_GPCM \ 486 | CSPR_V) 487 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 488 #define CONFIG_SYS_CSOR3 0x0 489 /* CPLD Timing parameters for IFC CS3 */ 490 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 491 FTIM0_GPCM_TEADC(0x0e) | \ 492 FTIM0_GPCM_TEAHC(0x0e)) 493 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 494 FTIM1_GPCM_TRAD(0x1f)) 495 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 496 FTIM2_GPCM_TCH(0x8) | \ 497 FTIM2_GPCM_TWP(0x1f)) 498 #define CONFIG_SYS_CS3_FTIM3 0x0 499 500 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 501 defined(CONFIG_RAMBOOT_NAND) 502 #define CONFIG_SYS_RAMBOOT 503 #define CONFIG_SYS_EXTRA_ENV_RELOC 504 #else 505 #undef CONFIG_SYS_RAMBOOT 506 #endif 507 508 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 509 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 510 #define CONFIG_A003399_NOR_WORKAROUND 511 #endif 512 #endif 513 514 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 515 #define CONFIG_BOARD_EARLY_INIT_R 516 517 #define CONFIG_SYS_INIT_RAM_LOCK 518 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 519 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 520 521 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 522 - GENERATED_GBL_DATA_SIZE) 523 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 524 525 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 526 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 527 528 /* 529 * Config the L2 Cache as L2 SRAM 530 */ 531 #if defined(CONFIG_SPL_BUILD) 532 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 533 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 534 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 535 #define CONFIG_SYS_L2_SIZE (256 << 10) 536 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 537 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 538 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 539 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 540 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 541 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 542 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 543 #elif defined(CONFIG_NAND) 544 #ifdef CONFIG_TPL_BUILD 545 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 546 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 547 #define CONFIG_SYS_L2_SIZE (256 << 10) 548 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 549 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 550 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 551 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 552 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 553 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 554 #else 555 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 556 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 557 #define CONFIG_SYS_L2_SIZE (256 << 10) 558 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 559 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 560 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 561 #endif 562 #endif 563 #endif 564 565 /* Serial Port */ 566 #define CONFIG_CONS_INDEX 1 567 #undef CONFIG_SERIAL_SOFTWARE_FIFO 568 #define CONFIG_SYS_NS16550_SERIAL 569 #define CONFIG_SYS_NS16550_REG_SIZE 1 570 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 571 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 572 #define CONFIG_NS16550_MIN_FUNCTIONS 573 #endif 574 575 #define CONFIG_SYS_BAUDRATE_TABLE \ 576 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 577 578 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 579 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 580 581 /* I2C */ 582 #define CONFIG_SYS_I2C 583 #define CONFIG_SYS_I2C_FSL 584 #define CONFIG_SYS_FSL_I2C_SPEED 400000 585 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 586 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 587 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 588 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 589 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 590 #define I2C_PCA9557_ADDR1 0x18 591 #define I2C_PCA9557_ADDR2 0x19 592 #define I2C_PCA9557_BUS_NUM 0 593 594 /* I2C EEPROM */ 595 #if defined(CONFIG_TARGET_P1010RDB_PB) 596 #define CONFIG_ID_EEPROM 597 #ifdef CONFIG_ID_EEPROM 598 #define CONFIG_SYS_I2C_EEPROM_NXID 599 #endif 600 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 601 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 602 #define CONFIG_SYS_EEPROM_BUS_NUM 0 603 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 604 #endif 605 /* enable read and write access to EEPROM */ 606 #define CONFIG_CMD_EEPROM 607 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 608 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 609 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 610 611 /* RTC */ 612 #define CONFIG_RTC_PT7C4338 613 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 614 615 /* 616 * SPI interface will not be available in case of NAND boot SPI CS0 will be 617 * used for SLIC 618 */ 619 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 620 /* eSPI - Enhanced SPI */ 621 #define CONFIG_SF_DEFAULT_SPEED 10000000 622 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 623 #endif 624 625 #if defined(CONFIG_TSEC_ENET) 626 #define CONFIG_MII /* MII PHY management */ 627 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 628 #define CONFIG_TSEC1 1 629 #define CONFIG_TSEC1_NAME "eTSEC1" 630 #define CONFIG_TSEC2 1 631 #define CONFIG_TSEC2_NAME "eTSEC2" 632 #define CONFIG_TSEC3 1 633 #define CONFIG_TSEC3_NAME "eTSEC3" 634 635 #define TSEC1_PHY_ADDR 1 636 #define TSEC2_PHY_ADDR 0 637 #define TSEC3_PHY_ADDR 2 638 639 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 640 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 641 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 642 643 #define TSEC1_PHYIDX 0 644 #define TSEC2_PHYIDX 0 645 #define TSEC3_PHYIDX 0 646 647 #define CONFIG_ETHPRIME "eTSEC1" 648 649 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 650 651 /* TBI PHY configuration for SGMII mode */ 652 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 653 TBICR_PHY_RESET \ 654 | TBICR_ANEG_ENABLE \ 655 | TBICR_FULL_DUPLEX \ 656 | TBICR_SPEED1_SET \ 657 ) 658 659 #endif /* CONFIG_TSEC_ENET */ 660 661 /* SATA */ 662 #define CONFIG_FSL_SATA 663 #define CONFIG_FSL_SATA_V2 664 #define CONFIG_LIBATA 665 666 #ifdef CONFIG_FSL_SATA 667 #define CONFIG_SYS_SATA_MAX_DEVICE 2 668 #define CONFIG_SATA1 669 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 670 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 671 #define CONFIG_SATA2 672 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 673 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 674 675 #define CONFIG_CMD_SATA 676 #define CONFIG_LBA48 677 #endif /* #ifdef CONFIG_FSL_SATA */ 678 679 #define CONFIG_MMC 680 #ifdef CONFIG_MMC 681 #define CONFIG_DOS_PARTITION 682 #define CONFIG_FSL_ESDHC 683 #define CONFIG_GENERIC_MMC 684 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 685 #endif 686 687 #define CONFIG_HAS_FSL_DR_USB 688 689 #if defined(CONFIG_HAS_FSL_DR_USB) 690 #define CONFIG_USB_EHCI 691 692 #ifdef CONFIG_USB_EHCI 693 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 694 #define CONFIG_USB_EHCI_FSL 695 #endif 696 #endif 697 698 /* 699 * Environment 700 */ 701 #if defined(CONFIG_SDCARD) 702 #define CONFIG_ENV_IS_IN_MMC 703 #define CONFIG_FSL_FIXED_MMC_LOCATION 704 #define CONFIG_SYS_MMC_ENV_DEV 0 705 #define CONFIG_ENV_SIZE 0x2000 706 #elif defined(CONFIG_SPIFLASH) 707 #define CONFIG_ENV_IS_IN_SPI_FLASH 708 #define CONFIG_ENV_SPI_BUS 0 709 #define CONFIG_ENV_SPI_CS 0 710 #define CONFIG_ENV_SPI_MAX_HZ 10000000 711 #define CONFIG_ENV_SPI_MODE 0 712 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 713 #define CONFIG_ENV_SECT_SIZE 0x10000 714 #define CONFIG_ENV_SIZE 0x2000 715 #elif defined(CONFIG_NAND) 716 #define CONFIG_ENV_IS_IN_NAND 717 #ifdef CONFIG_TPL_BUILD 718 #define CONFIG_ENV_SIZE 0x2000 719 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 720 #else 721 #if defined(CONFIG_TARGET_P1010RDB_PA) 722 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 723 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 724 #elif defined(CONFIG_TARGET_P1010RDB_PB) 725 #define CONFIG_ENV_SIZE (16 * 1024) 726 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 727 #endif 728 #endif 729 #define CONFIG_ENV_OFFSET (1024 * 1024) 730 #elif defined(CONFIG_SYS_RAMBOOT) 731 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 732 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 733 #define CONFIG_ENV_SIZE 0x2000 734 #else 735 #define CONFIG_ENV_IS_IN_FLASH 736 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 737 #define CONFIG_ENV_SIZE 0x2000 738 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 739 #endif 740 741 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 742 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 743 744 /* 745 * Command line configuration. 746 */ 747 #define CONFIG_CMD_DATE 748 #define CONFIG_CMD_ERRATA 749 #define CONFIG_CMD_IRQ 750 #define CONFIG_CMD_REGINFO 751 752 #undef CONFIG_WATCHDOG /* watchdog disabled */ 753 754 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 755 || defined(CONFIG_FSL_SATA) 756 #define CONFIG_DOS_PARTITION 757 #endif 758 759 /* Hash command with SHA acceleration supported in hardware */ 760 #ifdef CONFIG_FSL_CAAM 761 #define CONFIG_CMD_HASH 762 #define CONFIG_SHA_HW_ACCEL 763 #endif 764 765 /* 766 * Miscellaneous configurable options 767 */ 768 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 769 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 770 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 771 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 772 773 #if defined(CONFIG_CMD_KGDB) 774 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 775 #else 776 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 777 #endif 778 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 779 /* Print Buffer Size */ 780 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 781 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 782 783 /* 784 * For booting Linux, the board info and command line data 785 * have to be in the first 64 MB of memory, since this is 786 * the maximum mapped by the Linux kernel during initialization. 787 */ 788 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 789 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 790 791 #if defined(CONFIG_CMD_KGDB) 792 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 793 #endif 794 795 /* 796 * Environment Configuration 797 */ 798 799 #if defined(CONFIG_TSEC_ENET) 800 #define CONFIG_HAS_ETH0 801 #define CONFIG_HAS_ETH1 802 #define CONFIG_HAS_ETH2 803 #endif 804 805 #define CONFIG_ROOTPATH "/opt/nfsroot" 806 #define CONFIG_BOOTFILE "uImage" 807 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 808 809 /* default location for tftp and bootm */ 810 #define CONFIG_LOADADDR 1000000 811 812 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 813 814 #define CONFIG_BAUDRATE 115200 815 816 #define CONFIG_EXTRA_ENV_SETTINGS \ 817 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 818 "netdev=eth0\0" \ 819 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 820 "loadaddr=1000000\0" \ 821 "consoledev=ttyS0\0" \ 822 "ramdiskaddr=2000000\0" \ 823 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 824 "fdtaddr=1e00000\0" \ 825 "fdtfile=p1010rdb.dtb\0" \ 826 "bdev=sda1\0" \ 827 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 828 "othbootargs=ramdisk_size=600000\0" \ 829 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 830 "console=$consoledev,$baudrate $othbootargs; " \ 831 "usb start;" \ 832 "fatload usb 0:2 $loadaddr $bootfile;" \ 833 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 834 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 835 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 836 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 837 "console=$consoledev,$baudrate $othbootargs; " \ 838 "usb start;" \ 839 "ext2load usb 0:4 $loadaddr $bootfile;" \ 840 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 841 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 842 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 843 CONFIG_BOOTMODE 844 845 #if defined(CONFIG_TARGET_P1010RDB_PA) 846 #define CONFIG_BOOTMODE \ 847 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 848 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 849 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 850 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 851 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 852 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 853 854 #elif defined(CONFIG_TARGET_P1010RDB_PB) 855 #define CONFIG_BOOTMODE \ 856 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 857 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 858 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 859 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 860 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 861 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 862 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 863 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 864 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 865 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 866 #endif 867 868 #define CONFIG_RAMBOOTCOMMAND \ 869 "setenv bootargs root=/dev/ram rw " \ 870 "console=$consoledev,$baudrate $othbootargs; " \ 871 "tftp $ramdiskaddr $ramdiskfile;" \ 872 "tftp $loadaddr $bootfile;" \ 873 "tftp $fdtaddr $fdtfile;" \ 874 "bootm $loadaddr $ramdiskaddr $fdtaddr" 875 876 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 877 878 #include <asm/fsl_secure_boot.h> 879 880 #endif /* __CONFIG_H */ 881