1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #define CONFIG_P1010 19 #define CONFIG_E500 /* BOOKE e500 family */ 20 #include <asm/config_mpc85xx.h> 21 #define CONFIG_NAND_FSL_IFC 22 23 #ifdef CONFIG_SDCARD 24 #define CONFIG_RAMBOOT_SDCARD 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 27 #endif 28 29 #ifdef CONFIG_SPIFLASH 30 #define CONFIG_RAMBOOT_SPIFLASH 31 #define CONFIG_SYS_TEXT_BASE 0x11000000 32 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 33 #endif 34 35 #ifdef CONFIG_NAND 36 #define CONFIG_SPL 37 #define CONFIG_SPL_INIT_MINIMAL 38 #define CONFIG_SPL_SERIAL_SUPPORT 39 #define CONFIG_SPL_NAND_SUPPORT 40 #define CONFIG_SPL_NAND_MINIMAL 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 46 #define CONFIG_SPL_MAX_SIZE 8192 47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 48 #define CONFIG_SPL_RELOC_STACK 0x00100000 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #endif 55 56 57 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 58 #define CONFIG_RAMBOOT_NAND 59 #define CONFIG_SYS_TEXT_BASE 0x11000000 60 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 61 #endif 62 63 #ifndef CONFIG_SYS_TEXT_BASE 64 #define CONFIG_SYS_TEXT_BASE 0xeff80000 65 #endif 66 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 69 #endif 70 71 #ifdef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 73 #else 74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 75 #endif 76 77 /* High Level Configuration Options */ 78 #define CONFIG_BOOKE /* BOOKE */ 79 #define CONFIG_E500 /* BOOKE e500 family */ 80 #define CONFIG_MPC85xx 81 #define CONFIG_FSL_IFC /* Enable IFC Support */ 82 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 83 84 #define CONFIG_PCI /* Enable PCI/PCIE */ 85 #if defined(CONFIG_PCI) 86 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 87 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 89 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 90 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 92 93 #define CONFIG_CMD_NET 94 #define CONFIG_CMD_PCI 95 96 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 97 98 /* 99 * PCI Windows 100 * Memory space is mapped 1-1, but I/O space must start from 0. 101 */ 102 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 103 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 104 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 105 #ifdef CONFIG_PHYS_64BIT 106 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 107 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 108 #else 109 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 110 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 111 #endif 112 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 113 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 114 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 115 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 118 #else 119 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 120 #endif 121 122 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 123 #if defined(CONFIG_P1010RDB_PA) 124 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 125 #elif defined(CONFIG_P1010RDB_PB) 126 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 127 #endif 128 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 131 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 132 #else 133 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 134 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 135 #endif 136 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 137 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 138 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 139 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 142 #else 143 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 144 #endif 145 146 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 147 148 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 149 #define CONFIG_DOS_PARTITION 150 #endif 151 152 #define CONFIG_FSL_LAW /* Use common FSL init code */ 153 #define CONFIG_TSEC_ENET 154 #define CONFIG_ENV_OVERWRITE 155 156 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 157 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 158 159 #define CONFIG_MISC_INIT_R 160 #define CONFIG_HWCONFIG 161 /* 162 * These can be toggled for performance analysis, otherwise use default. 163 */ 164 #define CONFIG_L2_CACHE /* toggle L2 cache */ 165 #define CONFIG_BTB /* toggle branch predition */ 166 167 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 168 169 #define CONFIG_ENABLE_36BIT_PHYS 170 171 #ifdef CONFIG_PHYS_64BIT 172 #define CONFIG_ADDR_MAP 1 173 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 174 #endif 175 176 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 177 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 178 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 179 180 /* DDR Setup */ 181 #define CONFIG_SYS_FSL_DDR3 182 #define CONFIG_SYS_DDR_RAW_TIMING 183 #define CONFIG_DDR_SPD 184 #define CONFIG_SYS_SPD_BUS_NUM 1 185 #define SPD_EEPROM_ADDRESS 0x52 186 187 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 188 189 #ifndef __ASSEMBLY__ 190 extern unsigned long get_sdram_size(void); 191 #endif 192 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 193 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 194 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 195 196 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 197 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 198 199 /* DDR3 Controller Settings */ 200 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 201 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 202 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 203 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 204 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 205 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 206 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 207 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 208 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 209 #define CONFIG_SYS_DDR_RCW_1 0x00000000 210 #define CONFIG_SYS_DDR_RCW_2 0x00000000 211 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 212 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 213 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 214 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 215 216 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 217 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 218 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 219 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 220 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 221 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 222 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 223 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 224 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 225 226 /* settings for DDR3 at 667MT/s */ 227 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 228 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 229 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 230 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 231 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 232 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 233 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 234 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 235 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 236 237 #define CONFIG_SYS_CCSRBAR 0xffe00000 238 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 239 240 /* Don't relocate CCSRBAR while in NAND_SPL */ 241 #ifdef CONFIG_SPL_BUILD 242 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 243 #endif 244 245 /* 246 * Memory map 247 * 248 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 249 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 250 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 251 * 252 * Localbus non-cacheable 253 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 254 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 255 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 256 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 257 */ 258 259 /* 260 * IFC Definitions 261 */ 262 /* NOR Flash on IFC */ 263 #ifdef CONFIG_SPL_BUILD 264 #define CONFIG_SYS_NO_FLASH 265 #endif 266 267 #define CONFIG_SYS_FLASH_BASE 0xee000000 268 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 269 270 #ifdef CONFIG_PHYS_64BIT 271 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 272 #else 273 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 274 #endif 275 276 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 277 CSPR_PORT_SIZE_16 | \ 278 CSPR_MSEL_NOR | \ 279 CSPR_V) 280 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 281 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 282 /* NOR Flash Timing Params */ 283 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 284 FTIM0_NOR_TEADC(0x5) | \ 285 FTIM0_NOR_TEAHC(0x5) 286 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 287 FTIM1_NOR_TRAD_NOR(0x0f) 288 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 289 FTIM2_NOR_TCH(0x4) | \ 290 FTIM2_NOR_TWP(0x1c) 291 #define CONFIG_SYS_NOR_FTIM3 0x0 292 293 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 294 #define CONFIG_SYS_FLASH_QUIET_TEST 295 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 296 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 297 298 #undef CONFIG_SYS_FLASH_CHECKSUM 299 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 300 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 301 302 /* CFI for NOR Flash */ 303 #define CONFIG_FLASH_CFI_DRIVER 304 #define CONFIG_SYS_FLASH_CFI 305 #define CONFIG_SYS_FLASH_EMPTY_INFO 306 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 307 308 /* NAND Flash on IFC */ 309 #define CONFIG_SYS_NAND_BASE 0xff800000 310 #ifdef CONFIG_PHYS_64BIT 311 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 312 #else 313 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 314 #endif 315 316 #define CONFIG_MTD_DEVICE 317 #define CONFIG_MTD_PARTITION 318 #define CONFIG_CMD_MTDPARTS 319 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 320 #define MTDPARTS_DEFAULT \ 321 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 322 323 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 324 | CSPR_PORT_SIZE_8 \ 325 | CSPR_MSEL_NAND \ 326 | CSPR_V) 327 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 328 329 #if defined(CONFIG_P1010RDB_PA) 330 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 331 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 332 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 333 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 334 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 335 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 336 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 337 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 338 339 #elif defined(CONFIG_P1010RDB_PB) 340 #define CONFIG_SYS_NAND_ONFI_DETECTION 341 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 342 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 343 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 344 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 345 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 346 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 347 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 348 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 349 #endif 350 351 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 352 #define CONFIG_SYS_MAX_NAND_DEVICE 1 353 #define CONFIG_MTD_NAND_VERIFY_WRITE 354 #define CONFIG_CMD_NAND 355 356 #if defined(CONFIG_P1010RDB_PA) 357 /* NAND Flash Timing Params */ 358 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 359 FTIM0_NAND_TWP(0x0C) | \ 360 FTIM0_NAND_TWCHT(0x04) | \ 361 FTIM0_NAND_TWH(0x05) 362 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 363 FTIM1_NAND_TWBE(0x1d) | \ 364 FTIM1_NAND_TRR(0x07) | \ 365 FTIM1_NAND_TRP(0x0c) 366 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 367 FTIM2_NAND_TREH(0x05) | \ 368 FTIM2_NAND_TWHRE(0x0f) 369 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 370 371 #elif defined(CONFIG_P1010RDB_PB) 372 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 373 /* ONFI NAND Flash mode0 Timing Params */ 374 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 375 FTIM0_NAND_TWP(0x18) | \ 376 FTIM0_NAND_TWCHT(0x07) | \ 377 FTIM0_NAND_TWH(0x0a)) 378 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 379 FTIM1_NAND_TWBE(0x39) | \ 380 FTIM1_NAND_TRR(0x0e) | \ 381 FTIM1_NAND_TRP(0x18)) 382 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 383 FTIM2_NAND_TREH(0x0a) | \ 384 FTIM2_NAND_TWHRE(0x1e)) 385 #define CONFIG_SYS_NAND_FTIM3 0x0 386 #endif 387 388 #define CONFIG_SYS_NAND_DDR_LAW 11 389 390 /* Set up IFC registers for boot location NOR/NAND */ 391 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 392 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 393 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 394 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 395 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 396 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 397 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 398 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 399 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 400 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 401 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 402 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 403 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 404 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 405 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 406 #else 407 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 408 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 409 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 410 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 411 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 412 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 413 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 414 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 415 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 416 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 417 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 418 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 419 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 420 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 421 #endif 422 423 /* CPLD on IFC */ 424 #define CONFIG_SYS_CPLD_BASE 0xffb00000 425 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 428 #else 429 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 430 #endif 431 432 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 433 | CSPR_PORT_SIZE_8 \ 434 | CSPR_MSEL_GPCM \ 435 | CSPR_V) 436 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 437 #define CONFIG_SYS_CSOR3 0x0 438 /* CPLD Timing parameters for IFC CS3 */ 439 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 440 FTIM0_GPCM_TEADC(0x0e) | \ 441 FTIM0_GPCM_TEAHC(0x0e)) 442 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 443 FTIM1_GPCM_TRAD(0x1f)) 444 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 445 FTIM2_GPCM_TCH(0x0) | \ 446 FTIM2_GPCM_TWP(0x1f)) 447 #define CONFIG_SYS_CS3_FTIM3 0x0 448 449 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 450 #define CONFIG_SYS_RAMBOOT 451 #define CONFIG_SYS_EXTRA_ENV_RELOC 452 #else 453 #undef CONFIG_SYS_RAMBOOT 454 #endif 455 456 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 457 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ 458 && !defined(CONFIG_SECURE_BOOT) 459 #define CONFIG_A003399_NOR_WORKAROUND 460 #endif 461 #endif 462 463 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 464 #define CONFIG_BOARD_EARLY_INIT_R 465 466 #define CONFIG_SYS_INIT_RAM_LOCK 467 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 468 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 469 470 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 471 - GENERATED_GBL_DATA_SIZE) 472 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 473 474 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 475 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 476 477 /* Serial Port */ 478 #define CONFIG_CONS_INDEX 1 479 #undef CONFIG_SERIAL_SOFTWARE_FIFO 480 #define CONFIG_SYS_NS16550 481 #define CONFIG_SYS_NS16550_SERIAL 482 #define CONFIG_SYS_NS16550_REG_SIZE 1 483 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 484 #ifdef CONFIG_SPL_BUILD 485 #define CONFIG_NS16550_MIN_FUNCTIONS 486 #endif 487 488 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 489 490 #define CONFIG_SYS_BAUDRATE_TABLE \ 491 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 492 493 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 494 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 495 496 /* Use the HUSH parser */ 497 #define CONFIG_SYS_HUSH_PARSER 498 499 /* 500 * Pass open firmware flat tree 501 */ 502 #define CONFIG_OF_LIBFDT 503 #define CONFIG_OF_BOARD_SETUP 504 #define CONFIG_OF_STDOUT_VIA_ALIAS 505 506 /* new uImage format support */ 507 #define CONFIG_FIT 508 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 509 510 /* I2C */ 511 #define CONFIG_SYS_I2C 512 #define CONFIG_SYS_I2C_FSL 513 #define CONFIG_SYS_FSL_I2C_SPEED 400000 514 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 515 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 516 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 517 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 518 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 519 #define I2C_PCA9557_ADDR1 0x18 520 #define I2C_PCA9557_ADDR2 0x19 521 #define I2C_PCA9557_BUS_NUM 0 522 523 /* I2C EEPROM */ 524 #if defined(CONFIG_P1010RDB_PB) 525 #define CONFIG_ID_EEPROM 526 #ifdef CONFIG_ID_EEPROM 527 #define CONFIG_SYS_I2C_EEPROM_NXID 528 #endif 529 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 530 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 531 #define CONFIG_SYS_EEPROM_BUS_NUM 0 532 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 533 #endif 534 /* enable read and write access to EEPROM */ 535 #define CONFIG_CMD_EEPROM 536 #define CONFIG_SYS_I2C_MULTI_EEPROMS 537 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 538 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 539 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 540 541 /* RTC */ 542 #define CONFIG_RTC_PT7C4338 543 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 544 545 #define CONFIG_CMD_I2C 546 547 /* 548 * SPI interface will not be available in case of NAND boot SPI CS0 will be 549 * used for SLIC 550 */ 551 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 552 /* eSPI - Enhanced SPI */ 553 #define CONFIG_FSL_ESPI 554 #define CONFIG_SPI_FLASH 555 #define CONFIG_SPI_FLASH_SPANSION 556 #define CONFIG_CMD_SF 557 #define CONFIG_SF_DEFAULT_SPEED 10000000 558 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 559 #endif 560 561 #if defined(CONFIG_TSEC_ENET) 562 #define CONFIG_MII /* MII PHY management */ 563 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 564 #define CONFIG_TSEC1 1 565 #define CONFIG_TSEC1_NAME "eTSEC1" 566 #define CONFIG_TSEC2 1 567 #define CONFIG_TSEC2_NAME "eTSEC2" 568 #define CONFIG_TSEC3 1 569 #define CONFIG_TSEC3_NAME "eTSEC3" 570 571 #define TSEC1_PHY_ADDR 1 572 #define TSEC2_PHY_ADDR 0 573 #define TSEC3_PHY_ADDR 2 574 575 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 576 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 577 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 578 579 #define TSEC1_PHYIDX 0 580 #define TSEC2_PHYIDX 0 581 #define TSEC3_PHYIDX 0 582 583 #define CONFIG_ETHPRIME "eTSEC1" 584 585 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 586 587 /* TBI PHY configuration for SGMII mode */ 588 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 589 TBICR_PHY_RESET \ 590 | TBICR_ANEG_ENABLE \ 591 | TBICR_FULL_DUPLEX \ 592 | TBICR_SPEED1_SET \ 593 ) 594 595 #endif /* CONFIG_TSEC_ENET */ 596 597 598 /* SATA */ 599 #define CONFIG_FSL_SATA 600 #define CONFIG_FSL_SATA_V2 601 #define CONFIG_LIBATA 602 603 #ifdef CONFIG_FSL_SATA 604 #define CONFIG_SYS_SATA_MAX_DEVICE 2 605 #define CONFIG_SATA1 606 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 607 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 608 #define CONFIG_SATA2 609 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 610 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 611 612 #define CONFIG_CMD_SATA 613 #define CONFIG_LBA48 614 #endif /* #ifdef CONFIG_FSL_SATA */ 615 616 #define CONFIG_MMC 617 #ifdef CONFIG_MMC 618 #define CONFIG_CMD_MMC 619 #define CONFIG_DOS_PARTITION 620 #define CONFIG_FSL_ESDHC 621 #define CONFIG_GENERIC_MMC 622 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 623 #endif 624 625 #define CONFIG_HAS_FSL_DR_USB 626 627 #if defined(CONFIG_HAS_FSL_DR_USB) 628 #define CONFIG_USB_EHCI 629 630 #ifdef CONFIG_USB_EHCI 631 #define CONFIG_CMD_USB 632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 633 #define CONFIG_USB_EHCI_FSL 634 #define CONFIG_USB_STORAGE 635 #endif 636 #endif 637 638 /* 639 * Environment 640 */ 641 #if defined(CONFIG_RAMBOOT_SDCARD) 642 #define CONFIG_ENV_IS_IN_MMC 643 #define CONFIG_FSL_FIXED_MMC_LOCATION 644 #define CONFIG_SYS_MMC_ENV_DEV 0 645 #define CONFIG_ENV_SIZE 0x2000 646 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 647 #define CONFIG_ENV_IS_IN_SPI_FLASH 648 #define CONFIG_ENV_SPI_BUS 0 649 #define CONFIG_ENV_SPI_CS 0 650 #define CONFIG_ENV_SPI_MAX_HZ 10000000 651 #define CONFIG_ENV_SPI_MODE 0 652 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 653 #define CONFIG_ENV_SECT_SIZE 0x10000 654 #define CONFIG_ENV_SIZE 0x2000 655 #elif defined(CONFIG_NAND) 656 #define CONFIG_ENV_IS_IN_NAND 657 #if defined(CONFIG_P1010RDB_PA) 658 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 659 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 660 #elif defined(CONFIG_P1010RDB_PB) 661 #define CONFIG_ENV_SIZE (16 * 1024) 662 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 663 #endif 664 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 665 #elif defined(CONFIG_SYS_RAMBOOT) 666 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 667 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 668 #define CONFIG_ENV_SIZE 0x2000 669 #else 670 #define CONFIG_ENV_IS_IN_FLASH 671 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 672 #define CONFIG_ENV_ADDR 0xfff80000 673 #else 674 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 675 #endif 676 #define CONFIG_ENV_SIZE 0x2000 677 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 678 #endif 679 680 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 681 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 682 683 /* 684 * Command line configuration. 685 */ 686 #include <config_cmd_default.h> 687 688 #define CONFIG_CMD_DATE 689 #define CONFIG_CMD_ERRATA 690 #define CONFIG_CMD_ELF 691 #define CONFIG_CMD_IRQ 692 #define CONFIG_CMD_MII 693 #define CONFIG_CMD_PING 694 #define CONFIG_CMD_SETEXPR 695 #define CONFIG_CMD_REGINFO 696 697 #undef CONFIG_WATCHDOG /* watchdog disabled */ 698 699 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 700 || defined(CONFIG_FSL_SATA) 701 #define CONFIG_CMD_EXT2 702 #define CONFIG_CMD_FAT 703 #define CONFIG_DOS_PARTITION 704 #endif 705 706 /* 707 * Miscellaneous configurable options 708 */ 709 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 710 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 711 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 712 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 713 714 #if defined(CONFIG_CMD_KGDB) 715 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 716 #else 717 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 718 #endif 719 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 720 /* Print Buffer Size */ 721 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 722 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 723 724 /* 725 * Internal Definitions 726 * 727 * Boot Flags 728 */ 729 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 730 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 731 732 /* 733 * For booting Linux, the board info and command line data 734 * have to be in the first 64 MB of memory, since this is 735 * the maximum mapped by the Linux kernel during initialization. 736 */ 737 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 738 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 739 740 #if defined(CONFIG_CMD_KGDB) 741 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 742 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 743 #endif 744 745 /* 746 * Environment Configuration 747 */ 748 749 #if defined(CONFIG_TSEC_ENET) 750 #define CONFIG_HAS_ETH0 751 #define CONFIG_HAS_ETH1 752 #define CONFIG_HAS_ETH2 753 #endif 754 755 #define CONFIG_ROOTPATH "/opt/nfsroot" 756 #define CONFIG_BOOTFILE "uImage" 757 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 758 759 /* default location for tftp and bootm */ 760 #define CONFIG_LOADADDR 1000000 761 762 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 763 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 764 765 #define CONFIG_BAUDRATE 115200 766 767 #define CONFIG_EXTRA_ENV_SETTINGS \ 768 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 769 "netdev=eth0\0" \ 770 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 771 "loadaddr=1000000\0" \ 772 "consoledev=ttyS0\0" \ 773 "ramdiskaddr=2000000\0" \ 774 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 775 "fdtaddr=c00000\0" \ 776 "fdtfile=p1010rdb.dtb\0" \ 777 "bdev=sda1\0" \ 778 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 779 "othbootargs=ramdisk_size=600000\0" \ 780 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 781 "console=$consoledev,$baudrate $othbootargs; " \ 782 "usb start;" \ 783 "fatload usb 0:2 $loadaddr $bootfile;" \ 784 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 785 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 786 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 787 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 788 "console=$consoledev,$baudrate $othbootargs; " \ 789 "usb start;" \ 790 "ext2load usb 0:4 $loadaddr $bootfile;" \ 791 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 792 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 793 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 794 CONFIG_BOOTMODE 795 796 #if defined(CONFIG_P1010RDB_PA) 797 #define CONFIG_BOOTMODE \ 798 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 799 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 800 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 801 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 802 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 803 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 804 805 #elif defined(CONFIG_P1010RDB_PB) 806 #define CONFIG_BOOTMODE \ 807 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 808 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 809 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 810 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 811 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 812 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 813 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 814 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 815 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 816 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 817 #endif 818 819 #define CONFIG_RAMBOOTCOMMAND \ 820 "setenv bootargs root=/dev/ram rw " \ 821 "console=$consoledev,$baudrate $othbootargs; " \ 822 "tftp $ramdiskaddr $ramdiskfile;" \ 823 "tftp $loadaddr $bootfile;" \ 824 "tftp $fdtaddr $fdtfile;" \ 825 "bootm $loadaddr $ramdiskaddr $fdtaddr" 826 827 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 828 829 #include <asm/fsl_secure_boot.h> 830 831 #endif /* __CONFIG_H */ 832