1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #define CONFIG_P1010 19 #define CONFIG_E500 /* BOOKE e500 family */ 20 #include <asm/config_mpc85xx.h> 21 #define CONFIG_NAND_FSL_IFC 22 23 #ifdef CONFIG_SDCARD 24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 25 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 26 #define CONFIG_SPL_ENV_SUPPORT 27 #define CONFIG_SPL_SERIAL_SUPPORT 28 #define CONFIG_SPL_MMC_SUPPORT 29 #define CONFIG_SPL_MMC_MINIMAL 30 #define CONFIG_SPL_FLUSH_IMAGE 31 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 32 #define CONFIG_SPL_LIBGENERIC_SUPPORT 33 #define CONFIG_SPL_LIBCOMMON_SUPPORT 34 #define CONFIG_SPL_I2C_SUPPORT 35 #define CONFIG_FSL_LAW /* Use common FSL init code */ 36 #define CONFIG_SYS_TEXT_BASE 0x11001000 37 #define CONFIG_SPL_TEXT_BASE 0xD0001000 38 #define CONFIG_SPL_PAD_TO 0x18000 39 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 40 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 41 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 42 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 43 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 44 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 45 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 46 #define CONFIG_SPL_MMC_BOOT 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_COMMON_INIT_DDR 49 #endif 50 #endif 51 52 #ifdef CONFIG_SPIFLASH 53 #ifdef CONFIG_SECURE_BOOT 54 #define CONFIG_RAMBOOT_SPIFLASH 55 #define CONFIG_SYS_TEXT_BASE 0x11000000 56 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 57 #else 58 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 59 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 60 #define CONFIG_SPL_ENV_SUPPORT 61 #define CONFIG_SPL_SERIAL_SUPPORT 62 #define CONFIG_SPL_SPI_SUPPORT 63 #define CONFIG_SPL_SPI_FLASH_SUPPORT 64 #define CONFIG_SPL_SPI_FLASH_MINIMAL 65 #define CONFIG_SPL_FLUSH_IMAGE 66 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 67 #define CONFIG_SPL_LIBGENERIC_SUPPORT 68 #define CONFIG_SPL_LIBCOMMON_SUPPORT 69 #define CONFIG_SPL_I2C_SUPPORT 70 #define CONFIG_FSL_LAW /* Use common FSL init code */ 71 #define CONFIG_SYS_TEXT_BASE 0x11001000 72 #define CONFIG_SPL_TEXT_BASE 0xD0001000 73 #define CONFIG_SPL_PAD_TO 0x18000 74 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 81 #define CONFIG_SPL_SPI_BOOT 82 #ifdef CONFIG_SPL_BUILD 83 #define CONFIG_SPL_COMMON_INIT_DDR 84 #endif 85 #endif 86 #endif 87 88 #ifdef CONFIG_NAND 89 #ifdef CONFIG_SECURE_BOOT 90 #define CONFIG_SPL_INIT_MINIMAL 91 #define CONFIG_SPL_SERIAL_SUPPORT 92 #define CONFIG_SPL_NAND_SUPPORT 93 #define CONFIG_SPL_NAND_BOOT 94 #define CONFIG_SPL_FLUSH_IMAGE 95 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 96 97 #define CONFIG_SYS_TEXT_BASE 0x00201000 98 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 99 #define CONFIG_SPL_MAX_SIZE 8192 100 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 101 #define CONFIG_SPL_RELOC_STACK 0x00100000 102 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 103 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 104 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 105 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 106 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 107 #else 108 #ifdef CONFIG_TPL_BUILD 109 #define CONFIG_SPL_NAND_BOOT 110 #define CONFIG_SPL_FLUSH_IMAGE 111 #define CONFIG_SPL_ENV_SUPPORT 112 #define CONFIG_SPL_NAND_INIT 113 #define CONFIG_SPL_SERIAL_SUPPORT 114 #define CONFIG_SPL_LIBGENERIC_SUPPORT 115 #define CONFIG_SPL_LIBCOMMON_SUPPORT 116 #define CONFIG_SPL_I2C_SUPPORT 117 #define CONFIG_SPL_NAND_SUPPORT 118 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 119 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 120 #define CONFIG_SPL_COMMON_INIT_DDR 121 #define CONFIG_SPL_MAX_SIZE (128 << 10) 122 #define CONFIG_SPL_TEXT_BASE 0xD0001000 123 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 124 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 125 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 126 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 127 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 128 #elif defined(CONFIG_SPL_BUILD) 129 #define CONFIG_SPL_INIT_MINIMAL 130 #define CONFIG_SPL_SERIAL_SUPPORT 131 #define CONFIG_SPL_NAND_SUPPORT 132 #define CONFIG_SPL_NAND_MINIMAL 133 #define CONFIG_SPL_FLUSH_IMAGE 134 #define CONFIG_SPL_TEXT_BASE 0xff800000 135 #define CONFIG_SPL_MAX_SIZE 8192 136 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 137 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 138 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 139 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 140 #endif 141 #define CONFIG_SPL_PAD_TO 0x20000 142 #define CONFIG_TPL_PAD_TO 0x20000 143 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 144 #define CONFIG_SYS_TEXT_BASE 0x11001000 145 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 146 #endif 147 #endif 148 149 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 150 #define CONFIG_RAMBOOT_NAND 151 #define CONFIG_SYS_TEXT_BASE 0x11000000 152 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 153 #endif 154 155 #ifndef CONFIG_SYS_TEXT_BASE 156 #define CONFIG_SYS_TEXT_BASE 0xeff40000 157 #endif 158 159 #ifndef CONFIG_RESET_VECTOR_ADDRESS 160 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 161 #endif 162 163 #ifdef CONFIG_SPL_BUILD 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 165 #else 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 167 #endif 168 169 /* High Level Configuration Options */ 170 #define CONFIG_BOOKE /* BOOKE */ 171 #define CONFIG_E500 /* BOOKE e500 family */ 172 #define CONFIG_FSL_IFC /* Enable IFC Support */ 173 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 174 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 175 176 #define CONFIG_PCI /* Enable PCI/PCIE */ 177 #if defined(CONFIG_PCI) 178 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 179 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 180 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 181 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 182 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 183 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 184 185 #define CONFIG_CMD_NET 186 #define CONFIG_CMD_PCI 187 188 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 189 190 /* 191 * PCI Windows 192 * Memory space is mapped 1-1, but I/O space must start from 0. 193 */ 194 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 195 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 196 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 197 #ifdef CONFIG_PHYS_64BIT 198 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 199 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 200 #else 201 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 202 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 203 #endif 204 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 205 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 206 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 207 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 208 #ifdef CONFIG_PHYS_64BIT 209 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 210 #else 211 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 212 #endif 213 214 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 215 #if defined(CONFIG_P1010RDB_PA) 216 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 217 #elif defined(CONFIG_P1010RDB_PB) 218 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 219 #endif 220 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 221 #ifdef CONFIG_PHYS_64BIT 222 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 223 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 224 #else 225 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 226 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 227 #endif 228 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 229 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 230 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 231 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 232 #ifdef CONFIG_PHYS_64BIT 233 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 234 #else 235 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 236 #endif 237 238 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 239 240 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 241 #define CONFIG_DOS_PARTITION 242 #endif 243 244 #define CONFIG_FSL_LAW /* Use common FSL init code */ 245 #define CONFIG_TSEC_ENET 246 #define CONFIG_ENV_OVERWRITE 247 248 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 249 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 250 251 #define CONFIG_MISC_INIT_R 252 #define CONFIG_HWCONFIG 253 /* 254 * These can be toggled for performance analysis, otherwise use default. 255 */ 256 #define CONFIG_L2_CACHE /* toggle L2 cache */ 257 #define CONFIG_BTB /* toggle branch predition */ 258 259 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 260 261 #define CONFIG_ENABLE_36BIT_PHYS 262 263 #ifdef CONFIG_PHYS_64BIT 264 #define CONFIG_ADDR_MAP 1 265 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 266 #endif 267 268 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 269 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 270 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 271 272 /* DDR Setup */ 273 #define CONFIG_SYS_FSL_DDR3 274 #define CONFIG_SYS_DDR_RAW_TIMING 275 #define CONFIG_DDR_SPD 276 #define CONFIG_SYS_SPD_BUS_NUM 1 277 #define SPD_EEPROM_ADDRESS 0x52 278 279 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 280 281 #ifndef __ASSEMBLY__ 282 extern unsigned long get_sdram_size(void); 283 #endif 284 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 285 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 286 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 287 288 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 289 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 290 291 /* DDR3 Controller Settings */ 292 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 293 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 294 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 295 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 296 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 297 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 298 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 299 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 300 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 301 #define CONFIG_SYS_DDR_RCW_1 0x00000000 302 #define CONFIG_SYS_DDR_RCW_2 0x00000000 303 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 304 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 305 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 306 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 307 308 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 309 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 310 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 311 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 312 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 313 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 314 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 315 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 316 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 317 318 /* settings for DDR3 at 667MT/s */ 319 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 320 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 321 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 322 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 323 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 324 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 325 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 326 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 327 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 328 329 #define CONFIG_SYS_CCSRBAR 0xffe00000 330 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 331 332 /* Don't relocate CCSRBAR while in NAND_SPL */ 333 #ifdef CONFIG_SPL_BUILD 334 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 335 #endif 336 337 /* 338 * Memory map 339 * 340 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 341 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 342 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 343 * 344 * Localbus non-cacheable 345 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 346 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 347 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 348 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 349 */ 350 351 /* 352 * IFC Definitions 353 */ 354 /* NOR Flash on IFC */ 355 #ifdef CONFIG_SPL_BUILD 356 #define CONFIG_SYS_NO_FLASH 357 #endif 358 359 #define CONFIG_SYS_FLASH_BASE 0xee000000 360 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 361 362 #ifdef CONFIG_PHYS_64BIT 363 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 364 #else 365 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 366 #endif 367 368 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 369 CSPR_PORT_SIZE_16 | \ 370 CSPR_MSEL_NOR | \ 371 CSPR_V) 372 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 373 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 374 /* NOR Flash Timing Params */ 375 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 376 FTIM0_NOR_TEADC(0x5) | \ 377 FTIM0_NOR_TEAHC(0x5) 378 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 379 FTIM1_NOR_TRAD_NOR(0x0f) 380 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 381 FTIM2_NOR_TCH(0x4) | \ 382 FTIM2_NOR_TWP(0x1c) 383 #define CONFIG_SYS_NOR_FTIM3 0x0 384 385 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 386 #define CONFIG_SYS_FLASH_QUIET_TEST 387 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 388 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 389 390 #undef CONFIG_SYS_FLASH_CHECKSUM 391 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 392 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 393 394 /* CFI for NOR Flash */ 395 #define CONFIG_FLASH_CFI_DRIVER 396 #define CONFIG_SYS_FLASH_CFI 397 #define CONFIG_SYS_FLASH_EMPTY_INFO 398 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 399 400 /* NAND Flash on IFC */ 401 #define CONFIG_SYS_NAND_BASE 0xff800000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 404 #else 405 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 406 #endif 407 408 #define CONFIG_MTD_DEVICE 409 #define CONFIG_MTD_PARTITION 410 #define CONFIG_CMD_MTDPARTS 411 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 412 #define MTDPARTS_DEFAULT \ 413 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 414 415 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 416 | CSPR_PORT_SIZE_8 \ 417 | CSPR_MSEL_NAND \ 418 | CSPR_V) 419 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 420 421 #if defined(CONFIG_P1010RDB_PA) 422 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 423 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 424 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 425 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 426 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 427 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 428 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 429 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 430 431 #elif defined(CONFIG_P1010RDB_PB) 432 #define CONFIG_SYS_NAND_ONFI_DETECTION 433 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 434 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 435 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 436 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 437 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 438 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 439 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 440 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 441 #endif 442 443 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 444 #define CONFIG_SYS_MAX_NAND_DEVICE 1 445 #define CONFIG_MTD_NAND_VERIFY_WRITE 446 #define CONFIG_CMD_NAND 447 448 #if defined(CONFIG_P1010RDB_PA) 449 /* NAND Flash Timing Params */ 450 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 451 FTIM0_NAND_TWP(0x0C) | \ 452 FTIM0_NAND_TWCHT(0x04) | \ 453 FTIM0_NAND_TWH(0x05) 454 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 455 FTIM1_NAND_TWBE(0x1d) | \ 456 FTIM1_NAND_TRR(0x07) | \ 457 FTIM1_NAND_TRP(0x0c) 458 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 459 FTIM2_NAND_TREH(0x05) | \ 460 FTIM2_NAND_TWHRE(0x0f) 461 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 462 463 #elif defined(CONFIG_P1010RDB_PB) 464 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 465 /* ONFI NAND Flash mode0 Timing Params */ 466 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 467 FTIM0_NAND_TWP(0x18) | \ 468 FTIM0_NAND_TWCHT(0x07) | \ 469 FTIM0_NAND_TWH(0x0a)) 470 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 471 FTIM1_NAND_TWBE(0x39) | \ 472 FTIM1_NAND_TRR(0x0e) | \ 473 FTIM1_NAND_TRP(0x18)) 474 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 475 FTIM2_NAND_TREH(0x0a) | \ 476 FTIM2_NAND_TWHRE(0x1e)) 477 #define CONFIG_SYS_NAND_FTIM3 0x0 478 #endif 479 480 #define CONFIG_SYS_NAND_DDR_LAW 11 481 482 /* Set up IFC registers for boot location NOR/NAND */ 483 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 484 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 485 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 486 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 487 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 488 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 489 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 490 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 491 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 492 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 493 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 494 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 495 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 496 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 497 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 498 #else 499 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 500 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 501 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 502 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 503 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 504 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 505 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 506 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 507 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 508 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 509 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 510 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 511 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 512 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 513 #endif 514 515 /* CPLD on IFC */ 516 #define CONFIG_SYS_CPLD_BASE 0xffb00000 517 518 #ifdef CONFIG_PHYS_64BIT 519 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 520 #else 521 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 522 #endif 523 524 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 525 | CSPR_PORT_SIZE_8 \ 526 | CSPR_MSEL_GPCM \ 527 | CSPR_V) 528 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 529 #define CONFIG_SYS_CSOR3 0x0 530 /* CPLD Timing parameters for IFC CS3 */ 531 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 532 FTIM0_GPCM_TEADC(0x0e) | \ 533 FTIM0_GPCM_TEAHC(0x0e)) 534 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 535 FTIM1_GPCM_TRAD(0x1f)) 536 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 537 FTIM2_GPCM_TCH(0x8) | \ 538 FTIM2_GPCM_TWP(0x1f)) 539 #define CONFIG_SYS_CS3_FTIM3 0x0 540 541 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 542 defined(CONFIG_RAMBOOT_NAND) 543 #define CONFIG_SYS_RAMBOOT 544 #define CONFIG_SYS_EXTRA_ENV_RELOC 545 #else 546 #undef CONFIG_SYS_RAMBOOT 547 #endif 548 549 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 550 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 551 #define CONFIG_A003399_NOR_WORKAROUND 552 #endif 553 #endif 554 555 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 556 #define CONFIG_BOARD_EARLY_INIT_R 557 558 #define CONFIG_SYS_INIT_RAM_LOCK 559 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 560 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 561 562 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 563 - GENERATED_GBL_DATA_SIZE) 564 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 565 566 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 567 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 568 569 /* 570 * Config the L2 Cache as L2 SRAM 571 */ 572 #if defined(CONFIG_SPL_BUILD) 573 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 574 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 575 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 576 #define CONFIG_SYS_L2_SIZE (256 << 10) 577 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 578 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 579 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 580 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 581 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 582 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 583 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 584 #elif defined(CONFIG_NAND) 585 #ifdef CONFIG_TPL_BUILD 586 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 587 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 588 #define CONFIG_SYS_L2_SIZE (256 << 10) 589 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 590 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 591 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 592 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 593 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 594 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 595 #else 596 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 597 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 598 #define CONFIG_SYS_L2_SIZE (256 << 10) 599 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 600 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 601 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 602 #endif 603 #endif 604 #endif 605 606 /* Serial Port */ 607 #define CONFIG_CONS_INDEX 1 608 #undef CONFIG_SERIAL_SOFTWARE_FIFO 609 #define CONFIG_SYS_NS16550 610 #define CONFIG_SYS_NS16550_SERIAL 611 #define CONFIG_SYS_NS16550_REG_SIZE 1 612 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 613 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 614 #define CONFIG_NS16550_MIN_FUNCTIONS 615 #endif 616 617 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 618 619 #define CONFIG_SYS_BAUDRATE_TABLE \ 620 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 621 622 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 623 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 624 625 /* Use the HUSH parser */ 626 #define CONFIG_SYS_HUSH_PARSER 627 628 /* 629 * Pass open firmware flat tree 630 */ 631 #define CONFIG_OF_LIBFDT 632 #define CONFIG_OF_BOARD_SETUP 633 #define CONFIG_OF_STDOUT_VIA_ALIAS 634 635 /* new uImage format support */ 636 #define CONFIG_FIT 637 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 638 639 /* I2C */ 640 #define CONFIG_SYS_I2C 641 #define CONFIG_SYS_I2C_FSL 642 #define CONFIG_SYS_FSL_I2C_SPEED 400000 643 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 644 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 645 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 646 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 647 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 648 #define I2C_PCA9557_ADDR1 0x18 649 #define I2C_PCA9557_ADDR2 0x19 650 #define I2C_PCA9557_BUS_NUM 0 651 652 /* I2C EEPROM */ 653 #if defined(CONFIG_P1010RDB_PB) 654 #define CONFIG_ID_EEPROM 655 #ifdef CONFIG_ID_EEPROM 656 #define CONFIG_SYS_I2C_EEPROM_NXID 657 #endif 658 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 659 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 660 #define CONFIG_SYS_EEPROM_BUS_NUM 0 661 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 662 #endif 663 /* enable read and write access to EEPROM */ 664 #define CONFIG_CMD_EEPROM 665 #define CONFIG_SYS_I2C_MULTI_EEPROMS 666 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 667 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 668 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 669 670 /* RTC */ 671 #define CONFIG_RTC_PT7C4338 672 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 673 674 #define CONFIG_CMD_I2C 675 676 /* 677 * SPI interface will not be available in case of NAND boot SPI CS0 will be 678 * used for SLIC 679 */ 680 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 681 /* eSPI - Enhanced SPI */ 682 #define CONFIG_FSL_ESPI 683 #define CONFIG_SPI_FLASH 684 #define CONFIG_SPI_FLASH_SPANSION 685 #define CONFIG_CMD_SF 686 #define CONFIG_SF_DEFAULT_SPEED 10000000 687 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 688 #endif 689 690 #if defined(CONFIG_TSEC_ENET) 691 #define CONFIG_MII /* MII PHY management */ 692 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 693 #define CONFIG_TSEC1 1 694 #define CONFIG_TSEC1_NAME "eTSEC1" 695 #define CONFIG_TSEC2 1 696 #define CONFIG_TSEC2_NAME "eTSEC2" 697 #define CONFIG_TSEC3 1 698 #define CONFIG_TSEC3_NAME "eTSEC3" 699 700 #define TSEC1_PHY_ADDR 1 701 #define TSEC2_PHY_ADDR 0 702 #define TSEC3_PHY_ADDR 2 703 704 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 705 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 706 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 707 708 #define TSEC1_PHYIDX 0 709 #define TSEC2_PHYIDX 0 710 #define TSEC3_PHYIDX 0 711 712 #define CONFIG_ETHPRIME "eTSEC1" 713 714 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 715 716 /* TBI PHY configuration for SGMII mode */ 717 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 718 TBICR_PHY_RESET \ 719 | TBICR_ANEG_ENABLE \ 720 | TBICR_FULL_DUPLEX \ 721 | TBICR_SPEED1_SET \ 722 ) 723 724 #endif /* CONFIG_TSEC_ENET */ 725 726 727 /* SATA */ 728 #define CONFIG_FSL_SATA 729 #define CONFIG_FSL_SATA_V2 730 #define CONFIG_LIBATA 731 732 #ifdef CONFIG_FSL_SATA 733 #define CONFIG_SYS_SATA_MAX_DEVICE 2 734 #define CONFIG_SATA1 735 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 736 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 737 #define CONFIG_SATA2 738 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 739 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 740 741 #define CONFIG_CMD_SATA 742 #define CONFIG_LBA48 743 #endif /* #ifdef CONFIG_FSL_SATA */ 744 745 #define CONFIG_MMC 746 #ifdef CONFIG_MMC 747 #define CONFIG_CMD_MMC 748 #define CONFIG_DOS_PARTITION 749 #define CONFIG_FSL_ESDHC 750 #define CONFIG_GENERIC_MMC 751 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 752 #endif 753 754 #define CONFIG_HAS_FSL_DR_USB 755 756 #if defined(CONFIG_HAS_FSL_DR_USB) 757 #define CONFIG_USB_EHCI 758 759 #ifdef CONFIG_USB_EHCI 760 #define CONFIG_CMD_USB 761 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 762 #define CONFIG_USB_EHCI_FSL 763 #define CONFIG_USB_STORAGE 764 #endif 765 #endif 766 767 /* 768 * Environment 769 */ 770 #if defined(CONFIG_SDCARD) 771 #define CONFIG_ENV_IS_IN_MMC 772 #define CONFIG_FSL_FIXED_MMC_LOCATION 773 #define CONFIG_SYS_MMC_ENV_DEV 0 774 #define CONFIG_ENV_SIZE 0x2000 775 #elif defined(CONFIG_SPIFLASH) 776 #define CONFIG_ENV_IS_IN_SPI_FLASH 777 #define CONFIG_ENV_SPI_BUS 0 778 #define CONFIG_ENV_SPI_CS 0 779 #define CONFIG_ENV_SPI_MAX_HZ 10000000 780 #define CONFIG_ENV_SPI_MODE 0 781 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 782 #define CONFIG_ENV_SECT_SIZE 0x10000 783 #define CONFIG_ENV_SIZE 0x2000 784 #elif defined(CONFIG_NAND) 785 #define CONFIG_ENV_IS_IN_NAND 786 #ifdef CONFIG_TPL_BUILD 787 #define CONFIG_ENV_SIZE 0x2000 788 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 789 #else 790 #if defined(CONFIG_P1010RDB_PA) 791 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 792 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 793 #elif defined(CONFIG_P1010RDB_PB) 794 #define CONFIG_ENV_SIZE (16 * 1024) 795 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 796 #endif 797 #endif 798 #define CONFIG_ENV_OFFSET (1024 * 1024) 799 #elif defined(CONFIG_SYS_RAMBOOT) 800 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 801 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 802 #define CONFIG_ENV_SIZE 0x2000 803 #else 804 #define CONFIG_ENV_IS_IN_FLASH 805 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 806 #define CONFIG_ENV_SIZE 0x2000 807 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 808 #endif 809 810 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 811 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 812 813 /* 814 * Command line configuration. 815 */ 816 #include <config_cmd_default.h> 817 818 #define CONFIG_CMD_DATE 819 #define CONFIG_CMD_ERRATA 820 #define CONFIG_CMD_ELF 821 #define CONFIG_CMD_IRQ 822 #define CONFIG_CMD_MII 823 #define CONFIG_CMD_PING 824 #define CONFIG_CMD_SETEXPR 825 #define CONFIG_CMD_REGINFO 826 827 #undef CONFIG_WATCHDOG /* watchdog disabled */ 828 829 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 830 || defined(CONFIG_FSL_SATA) 831 #define CONFIG_CMD_EXT2 832 #define CONFIG_CMD_FAT 833 #define CONFIG_DOS_PARTITION 834 #endif 835 836 /* Hash command with SHA acceleration supported in hardware */ 837 #ifdef CONFIG_FSL_CAAM 838 #define CONFIG_CMD_HASH 839 #define CONFIG_SHA_HW_ACCEL 840 #endif 841 842 /* 843 * Miscellaneous configurable options 844 */ 845 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 846 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 847 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 848 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 849 850 #if defined(CONFIG_CMD_KGDB) 851 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 852 #else 853 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 854 #endif 855 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 856 /* Print Buffer Size */ 857 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 858 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 859 860 /* 861 * Internal Definitions 862 * 863 * Boot Flags 864 */ 865 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 866 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 867 868 /* 869 * For booting Linux, the board info and command line data 870 * have to be in the first 64 MB of memory, since this is 871 * the maximum mapped by the Linux kernel during initialization. 872 */ 873 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 874 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 875 876 #if defined(CONFIG_CMD_KGDB) 877 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 878 #endif 879 880 /* 881 * Environment Configuration 882 */ 883 884 #if defined(CONFIG_TSEC_ENET) 885 #define CONFIG_HAS_ETH0 886 #define CONFIG_HAS_ETH1 887 #define CONFIG_HAS_ETH2 888 #endif 889 890 #define CONFIG_ROOTPATH "/opt/nfsroot" 891 #define CONFIG_BOOTFILE "uImage" 892 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 893 894 /* default location for tftp and bootm */ 895 #define CONFIG_LOADADDR 1000000 896 897 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 898 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 899 900 #define CONFIG_BAUDRATE 115200 901 902 #define CONFIG_EXTRA_ENV_SETTINGS \ 903 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 904 "netdev=eth0\0" \ 905 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 906 "loadaddr=1000000\0" \ 907 "consoledev=ttyS0\0" \ 908 "ramdiskaddr=2000000\0" \ 909 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 910 "fdtaddr=c00000\0" \ 911 "fdtfile=p1010rdb.dtb\0" \ 912 "bdev=sda1\0" \ 913 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 914 "othbootargs=ramdisk_size=600000\0" \ 915 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 916 "console=$consoledev,$baudrate $othbootargs; " \ 917 "usb start;" \ 918 "fatload usb 0:2 $loadaddr $bootfile;" \ 919 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 920 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 921 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 922 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 923 "console=$consoledev,$baudrate $othbootargs; " \ 924 "usb start;" \ 925 "ext2load usb 0:4 $loadaddr $bootfile;" \ 926 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 927 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 928 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 929 CONFIG_BOOTMODE 930 931 #if defined(CONFIG_P1010RDB_PA) 932 #define CONFIG_BOOTMODE \ 933 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 934 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 935 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 936 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 937 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 938 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 939 940 #elif defined(CONFIG_P1010RDB_PB) 941 #define CONFIG_BOOTMODE \ 942 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 943 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 944 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 945 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 946 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 947 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 948 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 949 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 950 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 951 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 952 #endif 953 954 #define CONFIG_RAMBOOTCOMMAND \ 955 "setenv bootargs root=/dev/ram rw " \ 956 "console=$consoledev,$baudrate $othbootargs; " \ 957 "tftp $ramdiskaddr $ramdiskfile;" \ 958 "tftp $loadaddr $bootfile;" \ 959 "tftp $fdtaddr $fdtfile;" \ 960 "bootm $loadaddr $ramdiskaddr $fdtaddr" 961 962 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 963 964 #include <asm/fsl_secure_boot.h> 965 966 #ifdef CONFIG_SECURE_BOOT 967 #define CONFIG_CMD_BLOB 968 #endif 969 970 #endif /* __CONFIG_H */ 971