1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #define CONFIG_P1010 19 #define CONFIG_E500 /* BOOKE e500 family */ 20 #include <asm/config_mpc85xx.h> 21 #define CONFIG_NAND_FSL_IFC 22 23 #ifdef CONFIG_SDCARD 24 #define CONFIG_SPL 25 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 26 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 27 #define CONFIG_SPL_ENV_SUPPORT 28 #define CONFIG_SPL_SERIAL_SUPPORT 29 #define CONFIG_SPL_MMC_SUPPORT 30 #define CONFIG_SPL_MMC_MINIMAL 31 #define CONFIG_SPL_FLUSH_IMAGE 32 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 33 #define CONFIG_SPL_LIBGENERIC_SUPPORT 34 #define CONFIG_SPL_LIBCOMMON_SUPPORT 35 #define CONFIG_SPL_I2C_SUPPORT 36 #define CONFIG_FSL_LAW /* Use common FSL init code */ 37 #define CONFIG_SYS_TEXT_BASE 0x11001000 38 #define CONFIG_SPL_TEXT_BASE 0xD0001000 39 #define CONFIG_SPL_PAD_TO 0x18000 40 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 41 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 42 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 43 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 44 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 45 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 47 #define CONFIG_SPL_MMC_BOOT 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #endif 51 #endif 52 53 #ifdef CONFIG_SPIFLASH 54 #ifdef CONFIG_SECURE_BOOT 55 #define CONFIG_RAMBOOT_SPIFLASH 56 #define CONFIG_SYS_TEXT_BASE 0x11000000 57 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 58 #else 59 #define CONFIG_SPL 60 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 61 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 62 #define CONFIG_SPL_ENV_SUPPORT 63 #define CONFIG_SPL_SERIAL_SUPPORT 64 #define CONFIG_SPL_SPI_SUPPORT 65 #define CONFIG_SPL_SPI_FLASH_SUPPORT 66 #define CONFIG_SPL_SPI_FLASH_MINIMAL 67 #define CONFIG_SPL_FLUSH_IMAGE 68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 69 #define CONFIG_SPL_LIBGENERIC_SUPPORT 70 #define CONFIG_SPL_LIBCOMMON_SUPPORT 71 #define CONFIG_SPL_I2C_SUPPORT 72 #define CONFIG_FSL_LAW /* Use common FSL init code */ 73 #define CONFIG_SYS_TEXT_BASE 0x11001000 74 #define CONFIG_SPL_TEXT_BASE 0xD0001000 75 #define CONFIG_SPL_PAD_TO 0x18000 76 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #define CONFIG_SPL_SPI_BOOT 84 #ifdef CONFIG_SPL_BUILD 85 #define CONFIG_SPL_COMMON_INIT_DDR 86 #endif 87 #endif 88 #endif 89 90 #ifdef CONFIG_NAND 91 #define CONFIG_SPL 92 #ifdef CONFIG_SECURE_BOOT 93 #define CONFIG_SPL_INIT_MINIMAL 94 #define CONFIG_SPL_SERIAL_SUPPORT 95 #define CONFIG_SPL_NAND_SUPPORT 96 #define CONFIG_SPL_NAND_BOOT 97 #define CONFIG_SPL_FLUSH_IMAGE 98 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 99 100 #define CONFIG_SYS_TEXT_BASE 0x00201000 101 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 102 #define CONFIG_SPL_MAX_SIZE 8192 103 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 104 #define CONFIG_SPL_RELOC_STACK 0x00100000 105 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 106 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 107 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 108 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 109 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 110 #else 111 #define CONFIG_TPL 112 #ifdef CONFIG_TPL_BUILD 113 #define CONFIG_SPL_NAND_BOOT 114 #define CONFIG_SPL_FLUSH_IMAGE 115 #define CONFIG_SPL_ENV_SUPPORT 116 #define CONFIG_SPL_NAND_INIT 117 #define CONFIG_SPL_SERIAL_SUPPORT 118 #define CONFIG_SPL_LIBGENERIC_SUPPORT 119 #define CONFIG_SPL_LIBCOMMON_SUPPORT 120 #define CONFIG_SPL_I2C_SUPPORT 121 #define CONFIG_SPL_NAND_SUPPORT 122 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 123 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 124 #define CONFIG_SPL_COMMON_INIT_DDR 125 #define CONFIG_SPL_MAX_SIZE (128 << 10) 126 #define CONFIG_SPL_TEXT_BASE 0xD0001000 127 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 128 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 129 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 130 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 131 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 132 #elif defined(CONFIG_SPL_BUILD) 133 #define CONFIG_SPL_INIT_MINIMAL 134 #define CONFIG_SPL_SERIAL_SUPPORT 135 #define CONFIG_SPL_NAND_SUPPORT 136 #define CONFIG_SPL_NAND_MINIMAL 137 #define CONFIG_SPL_FLUSH_IMAGE 138 #define CONFIG_SPL_TEXT_BASE 0xff800000 139 #define CONFIG_SPL_MAX_SIZE 8192 140 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 141 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 142 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 143 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 144 #endif 145 #define CONFIG_SPL_PAD_TO 0x20000 146 #define CONFIG_TPL_PAD_TO 0x20000 147 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 148 #define CONFIG_SYS_TEXT_BASE 0x11001000 149 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 150 #endif 151 #endif 152 153 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 154 #define CONFIG_RAMBOOT_NAND 155 #define CONFIG_SYS_TEXT_BASE 0x11000000 156 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 157 #endif 158 159 #ifndef CONFIG_SYS_TEXT_BASE 160 #define CONFIG_SYS_TEXT_BASE 0xeff40000 161 #endif 162 163 #ifndef CONFIG_RESET_VECTOR_ADDRESS 164 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 165 #endif 166 167 #ifdef CONFIG_SPL_BUILD 168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 169 #else 170 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 171 #endif 172 173 /* High Level Configuration Options */ 174 #define CONFIG_BOOKE /* BOOKE */ 175 #define CONFIG_E500 /* BOOKE e500 family */ 176 #define CONFIG_FSL_IFC /* Enable IFC Support */ 177 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 178 179 #define CONFIG_PCI /* Enable PCI/PCIE */ 180 #if defined(CONFIG_PCI) 181 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 182 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 183 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 184 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 185 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 186 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 187 188 #define CONFIG_CMD_NET 189 #define CONFIG_CMD_PCI 190 191 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 192 193 /* 194 * PCI Windows 195 * Memory space is mapped 1-1, but I/O space must start from 0. 196 */ 197 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 198 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 199 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 200 #ifdef CONFIG_PHYS_64BIT 201 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 202 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 203 #else 204 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 205 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 206 #endif 207 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 208 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 209 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 210 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 211 #ifdef CONFIG_PHYS_64BIT 212 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 213 #else 214 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 215 #endif 216 217 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 218 #if defined(CONFIG_P1010RDB_PA) 219 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 220 #elif defined(CONFIG_P1010RDB_PB) 221 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 222 #endif 223 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 224 #ifdef CONFIG_PHYS_64BIT 225 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 226 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 227 #else 228 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 229 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 230 #endif 231 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 232 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 233 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 234 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 235 #ifdef CONFIG_PHYS_64BIT 236 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 237 #else 238 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 239 #endif 240 241 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 242 243 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 244 #define CONFIG_DOS_PARTITION 245 #endif 246 247 #define CONFIG_FSL_LAW /* Use common FSL init code */ 248 #define CONFIG_TSEC_ENET 249 #define CONFIG_ENV_OVERWRITE 250 251 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 252 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 253 254 #define CONFIG_MISC_INIT_R 255 #define CONFIG_HWCONFIG 256 /* 257 * These can be toggled for performance analysis, otherwise use default. 258 */ 259 #define CONFIG_L2_CACHE /* toggle L2 cache */ 260 #define CONFIG_BTB /* toggle branch predition */ 261 262 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 263 264 #define CONFIG_ENABLE_36BIT_PHYS 265 266 #ifdef CONFIG_PHYS_64BIT 267 #define CONFIG_ADDR_MAP 1 268 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 269 #endif 270 271 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 272 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 273 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 274 275 /* DDR Setup */ 276 #define CONFIG_SYS_FSL_DDR3 277 #define CONFIG_SYS_DDR_RAW_TIMING 278 #define CONFIG_DDR_SPD 279 #define CONFIG_SYS_SPD_BUS_NUM 1 280 #define SPD_EEPROM_ADDRESS 0x52 281 282 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 283 284 #ifndef __ASSEMBLY__ 285 extern unsigned long get_sdram_size(void); 286 #endif 287 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 288 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 289 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 290 291 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 292 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 293 294 /* DDR3 Controller Settings */ 295 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 296 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 297 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 298 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 299 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 300 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 301 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 302 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 303 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 304 #define CONFIG_SYS_DDR_RCW_1 0x00000000 305 #define CONFIG_SYS_DDR_RCW_2 0x00000000 306 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 307 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 308 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 309 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 310 311 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 312 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 313 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 314 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 315 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 316 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 317 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 318 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 319 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 320 321 /* settings for DDR3 at 667MT/s */ 322 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 323 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 324 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 325 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 326 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 327 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 328 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 329 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 330 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 331 332 #define CONFIG_SYS_CCSRBAR 0xffe00000 333 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 334 335 /* Don't relocate CCSRBAR while in NAND_SPL */ 336 #ifdef CONFIG_SPL_BUILD 337 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 338 #endif 339 340 /* 341 * Memory map 342 * 343 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 344 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 345 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 346 * 347 * Localbus non-cacheable 348 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 349 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 350 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 351 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 352 */ 353 354 /* 355 * IFC Definitions 356 */ 357 /* NOR Flash on IFC */ 358 #ifdef CONFIG_SPL_BUILD 359 #define CONFIG_SYS_NO_FLASH 360 #endif 361 362 #define CONFIG_SYS_FLASH_BASE 0xee000000 363 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 364 365 #ifdef CONFIG_PHYS_64BIT 366 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 367 #else 368 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 369 #endif 370 371 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 372 CSPR_PORT_SIZE_16 | \ 373 CSPR_MSEL_NOR | \ 374 CSPR_V) 375 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 376 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 377 /* NOR Flash Timing Params */ 378 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 379 FTIM0_NOR_TEADC(0x5) | \ 380 FTIM0_NOR_TEAHC(0x5) 381 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 382 FTIM1_NOR_TRAD_NOR(0x0f) 383 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 384 FTIM2_NOR_TCH(0x4) | \ 385 FTIM2_NOR_TWP(0x1c) 386 #define CONFIG_SYS_NOR_FTIM3 0x0 387 388 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 389 #define CONFIG_SYS_FLASH_QUIET_TEST 390 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 391 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 392 393 #undef CONFIG_SYS_FLASH_CHECKSUM 394 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 395 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 396 397 /* CFI for NOR Flash */ 398 #define CONFIG_FLASH_CFI_DRIVER 399 #define CONFIG_SYS_FLASH_CFI 400 #define CONFIG_SYS_FLASH_EMPTY_INFO 401 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 402 403 /* NAND Flash on IFC */ 404 #define CONFIG_SYS_NAND_BASE 0xff800000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 407 #else 408 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 409 #endif 410 411 #define CONFIG_MTD_DEVICE 412 #define CONFIG_MTD_PARTITION 413 #define CONFIG_CMD_MTDPARTS 414 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 415 #define MTDPARTS_DEFAULT \ 416 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 417 418 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 419 | CSPR_PORT_SIZE_8 \ 420 | CSPR_MSEL_NAND \ 421 | CSPR_V) 422 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 423 424 #if defined(CONFIG_P1010RDB_PA) 425 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 426 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 427 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 428 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 429 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 430 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 431 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 432 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 433 434 #elif defined(CONFIG_P1010RDB_PB) 435 #define CONFIG_SYS_NAND_ONFI_DETECTION 436 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 437 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 438 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 439 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 440 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 441 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 442 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 443 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 444 #endif 445 446 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 447 #define CONFIG_SYS_MAX_NAND_DEVICE 1 448 #define CONFIG_MTD_NAND_VERIFY_WRITE 449 #define CONFIG_CMD_NAND 450 451 #if defined(CONFIG_P1010RDB_PA) 452 /* NAND Flash Timing Params */ 453 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 454 FTIM0_NAND_TWP(0x0C) | \ 455 FTIM0_NAND_TWCHT(0x04) | \ 456 FTIM0_NAND_TWH(0x05) 457 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 458 FTIM1_NAND_TWBE(0x1d) | \ 459 FTIM1_NAND_TRR(0x07) | \ 460 FTIM1_NAND_TRP(0x0c) 461 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 462 FTIM2_NAND_TREH(0x05) | \ 463 FTIM2_NAND_TWHRE(0x0f) 464 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 465 466 #elif defined(CONFIG_P1010RDB_PB) 467 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 468 /* ONFI NAND Flash mode0 Timing Params */ 469 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 470 FTIM0_NAND_TWP(0x18) | \ 471 FTIM0_NAND_TWCHT(0x07) | \ 472 FTIM0_NAND_TWH(0x0a)) 473 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 474 FTIM1_NAND_TWBE(0x39) | \ 475 FTIM1_NAND_TRR(0x0e) | \ 476 FTIM1_NAND_TRP(0x18)) 477 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 478 FTIM2_NAND_TREH(0x0a) | \ 479 FTIM2_NAND_TWHRE(0x1e)) 480 #define CONFIG_SYS_NAND_FTIM3 0x0 481 #endif 482 483 #define CONFIG_SYS_NAND_DDR_LAW 11 484 485 /* Set up IFC registers for boot location NOR/NAND */ 486 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 487 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 488 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 489 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 490 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 491 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 492 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 493 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 494 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 495 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 496 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 497 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 498 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 499 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 500 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 501 #else 502 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 503 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 504 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 505 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 506 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 507 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 508 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 509 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 510 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 511 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 512 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 513 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 514 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 515 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 516 #endif 517 518 /* CPLD on IFC */ 519 #define CONFIG_SYS_CPLD_BASE 0xffb00000 520 521 #ifdef CONFIG_PHYS_64BIT 522 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 523 #else 524 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 525 #endif 526 527 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 528 | CSPR_PORT_SIZE_8 \ 529 | CSPR_MSEL_GPCM \ 530 | CSPR_V) 531 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 532 #define CONFIG_SYS_CSOR3 0x0 533 /* CPLD Timing parameters for IFC CS3 */ 534 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 535 FTIM0_GPCM_TEADC(0x0e) | \ 536 FTIM0_GPCM_TEAHC(0x0e)) 537 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 538 FTIM1_GPCM_TRAD(0x1f)) 539 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 540 FTIM2_GPCM_TCH(0x0) | \ 541 FTIM2_GPCM_TWP(0x1f)) 542 #define CONFIG_SYS_CS3_FTIM3 0x0 543 544 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 545 defined(CONFIG_RAMBOOT_NAND) 546 #define CONFIG_SYS_RAMBOOT 547 #define CONFIG_SYS_EXTRA_ENV_RELOC 548 #else 549 #undef CONFIG_SYS_RAMBOOT 550 #endif 551 552 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 553 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 554 #define CONFIG_A003399_NOR_WORKAROUND 555 #endif 556 #endif 557 558 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 559 #define CONFIG_BOARD_EARLY_INIT_R 560 561 #define CONFIG_SYS_INIT_RAM_LOCK 562 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 563 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 564 565 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 566 - GENERATED_GBL_DATA_SIZE) 567 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 568 569 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 570 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 571 572 /* 573 * Config the L2 Cache as L2 SRAM 574 */ 575 #if defined(CONFIG_SPL_BUILD) 576 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 577 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 578 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 579 #define CONFIG_SYS_L2_SIZE (256 << 10) 580 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 581 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 582 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 583 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 584 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 585 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 586 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 587 #elif defined(CONFIG_NAND) 588 #ifdef CONFIG_TPL_BUILD 589 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 590 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 591 #define CONFIG_SYS_L2_SIZE (256 << 10) 592 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 593 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 594 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 595 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 596 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 597 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 598 #else 599 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 600 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 601 #define CONFIG_SYS_L2_SIZE (256 << 10) 602 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 603 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 604 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 605 #endif 606 #endif 607 #endif 608 609 /* Serial Port */ 610 #define CONFIG_CONS_INDEX 1 611 #undef CONFIG_SERIAL_SOFTWARE_FIFO 612 #define CONFIG_SYS_NS16550 613 #define CONFIG_SYS_NS16550_SERIAL 614 #define CONFIG_SYS_NS16550_REG_SIZE 1 615 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 616 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 617 #define CONFIG_NS16550_MIN_FUNCTIONS 618 #endif 619 620 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 621 622 #define CONFIG_SYS_BAUDRATE_TABLE \ 623 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 624 625 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 626 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 627 628 /* Use the HUSH parser */ 629 #define CONFIG_SYS_HUSH_PARSER 630 631 /* 632 * Pass open firmware flat tree 633 */ 634 #define CONFIG_OF_LIBFDT 635 #define CONFIG_OF_BOARD_SETUP 636 #define CONFIG_OF_STDOUT_VIA_ALIAS 637 638 /* new uImage format support */ 639 #define CONFIG_FIT 640 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 641 642 /* I2C */ 643 #define CONFIG_SYS_I2C 644 #define CONFIG_SYS_I2C_FSL 645 #define CONFIG_SYS_FSL_I2C_SPEED 400000 646 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 647 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 648 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 649 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 650 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 651 #define I2C_PCA9557_ADDR1 0x18 652 #define I2C_PCA9557_ADDR2 0x19 653 #define I2C_PCA9557_BUS_NUM 0 654 655 /* I2C EEPROM */ 656 #if defined(CONFIG_P1010RDB_PB) 657 #define CONFIG_ID_EEPROM 658 #ifdef CONFIG_ID_EEPROM 659 #define CONFIG_SYS_I2C_EEPROM_NXID 660 #endif 661 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 662 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 663 #define CONFIG_SYS_EEPROM_BUS_NUM 0 664 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 665 #endif 666 /* enable read and write access to EEPROM */ 667 #define CONFIG_CMD_EEPROM 668 #define CONFIG_SYS_I2C_MULTI_EEPROMS 669 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 670 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 671 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 672 673 /* RTC */ 674 #define CONFIG_RTC_PT7C4338 675 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 676 677 #define CONFIG_CMD_I2C 678 679 /* 680 * SPI interface will not be available in case of NAND boot SPI CS0 will be 681 * used for SLIC 682 */ 683 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 684 /* eSPI - Enhanced SPI */ 685 #define CONFIG_FSL_ESPI 686 #define CONFIG_SPI_FLASH 687 #define CONFIG_SPI_FLASH_SPANSION 688 #define CONFIG_CMD_SF 689 #define CONFIG_SF_DEFAULT_SPEED 10000000 690 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 691 #endif 692 693 #if defined(CONFIG_TSEC_ENET) 694 #define CONFIG_MII /* MII PHY management */ 695 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 696 #define CONFIG_TSEC1 1 697 #define CONFIG_TSEC1_NAME "eTSEC1" 698 #define CONFIG_TSEC2 1 699 #define CONFIG_TSEC2_NAME "eTSEC2" 700 #define CONFIG_TSEC3 1 701 #define CONFIG_TSEC3_NAME "eTSEC3" 702 703 #define TSEC1_PHY_ADDR 1 704 #define TSEC2_PHY_ADDR 0 705 #define TSEC3_PHY_ADDR 2 706 707 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 708 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 709 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 710 711 #define TSEC1_PHYIDX 0 712 #define TSEC2_PHYIDX 0 713 #define TSEC3_PHYIDX 0 714 715 #define CONFIG_ETHPRIME "eTSEC1" 716 717 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 718 719 /* TBI PHY configuration for SGMII mode */ 720 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 721 TBICR_PHY_RESET \ 722 | TBICR_ANEG_ENABLE \ 723 | TBICR_FULL_DUPLEX \ 724 | TBICR_SPEED1_SET \ 725 ) 726 727 #endif /* CONFIG_TSEC_ENET */ 728 729 730 /* SATA */ 731 #define CONFIG_FSL_SATA 732 #define CONFIG_FSL_SATA_V2 733 #define CONFIG_LIBATA 734 735 #ifdef CONFIG_FSL_SATA 736 #define CONFIG_SYS_SATA_MAX_DEVICE 2 737 #define CONFIG_SATA1 738 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 739 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 740 #define CONFIG_SATA2 741 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 742 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 743 744 #define CONFIG_CMD_SATA 745 #define CONFIG_LBA48 746 #endif /* #ifdef CONFIG_FSL_SATA */ 747 748 #define CONFIG_MMC 749 #ifdef CONFIG_MMC 750 #define CONFIG_CMD_MMC 751 #define CONFIG_DOS_PARTITION 752 #define CONFIG_FSL_ESDHC 753 #define CONFIG_GENERIC_MMC 754 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 755 #endif 756 757 #define CONFIG_HAS_FSL_DR_USB 758 759 #if defined(CONFIG_HAS_FSL_DR_USB) 760 #define CONFIG_USB_EHCI 761 762 #ifdef CONFIG_USB_EHCI 763 #define CONFIG_CMD_USB 764 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 765 #define CONFIG_USB_EHCI_FSL 766 #define CONFIG_USB_STORAGE 767 #endif 768 #endif 769 770 /* 771 * Environment 772 */ 773 #if defined(CONFIG_SDCARD) 774 #define CONFIG_ENV_IS_IN_MMC 775 #define CONFIG_FSL_FIXED_MMC_LOCATION 776 #define CONFIG_SYS_MMC_ENV_DEV 0 777 #define CONFIG_ENV_SIZE 0x2000 778 #elif defined(CONFIG_SPIFLASH) 779 #define CONFIG_ENV_IS_IN_SPI_FLASH 780 #define CONFIG_ENV_SPI_BUS 0 781 #define CONFIG_ENV_SPI_CS 0 782 #define CONFIG_ENV_SPI_MAX_HZ 10000000 783 #define CONFIG_ENV_SPI_MODE 0 784 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 785 #define CONFIG_ENV_SECT_SIZE 0x10000 786 #define CONFIG_ENV_SIZE 0x2000 787 #elif defined(CONFIG_NAND) 788 #define CONFIG_ENV_IS_IN_NAND 789 #ifdef CONFIG_TPL_BUILD 790 #define CONFIG_ENV_SIZE 0x2000 791 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 792 #else 793 #if defined(CONFIG_P1010RDB_PA) 794 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 795 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 796 #elif defined(CONFIG_P1010RDB_PB) 797 #define CONFIG_ENV_SIZE (16 * 1024) 798 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 799 #endif 800 #endif 801 #define CONFIG_ENV_OFFSET (1024 * 1024) 802 #elif defined(CONFIG_SYS_RAMBOOT) 803 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 804 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 805 #define CONFIG_ENV_SIZE 0x2000 806 #else 807 #define CONFIG_ENV_IS_IN_FLASH 808 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 809 #define CONFIG_ENV_SIZE 0x2000 810 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 811 #endif 812 813 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 814 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 815 816 /* 817 * Command line configuration. 818 */ 819 #include <config_cmd_default.h> 820 821 #define CONFIG_CMD_DATE 822 #define CONFIG_CMD_ERRATA 823 #define CONFIG_CMD_ELF 824 #define CONFIG_CMD_IRQ 825 #define CONFIG_CMD_MII 826 #define CONFIG_CMD_PING 827 #define CONFIG_CMD_SETEXPR 828 #define CONFIG_CMD_REGINFO 829 830 #undef CONFIG_WATCHDOG /* watchdog disabled */ 831 832 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 833 || defined(CONFIG_FSL_SATA) 834 #define CONFIG_CMD_EXT2 835 #define CONFIG_CMD_FAT 836 #define CONFIG_DOS_PARTITION 837 #endif 838 839 /* 840 * Miscellaneous configurable options 841 */ 842 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 843 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 844 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 845 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 846 847 #if defined(CONFIG_CMD_KGDB) 848 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 849 #else 850 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 851 #endif 852 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 853 /* Print Buffer Size */ 854 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 855 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 856 857 /* 858 * Internal Definitions 859 * 860 * Boot Flags 861 */ 862 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 863 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 864 865 /* 866 * For booting Linux, the board info and command line data 867 * have to be in the first 64 MB of memory, since this is 868 * the maximum mapped by the Linux kernel during initialization. 869 */ 870 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 871 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 872 873 #if defined(CONFIG_CMD_KGDB) 874 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 875 #endif 876 877 /* 878 * Environment Configuration 879 */ 880 881 #if defined(CONFIG_TSEC_ENET) 882 #define CONFIG_HAS_ETH0 883 #define CONFIG_HAS_ETH1 884 #define CONFIG_HAS_ETH2 885 #endif 886 887 #define CONFIG_ROOTPATH "/opt/nfsroot" 888 #define CONFIG_BOOTFILE "uImage" 889 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 890 891 /* default location for tftp and bootm */ 892 #define CONFIG_LOADADDR 1000000 893 894 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 895 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 896 897 #define CONFIG_BAUDRATE 115200 898 899 #define CONFIG_EXTRA_ENV_SETTINGS \ 900 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 901 "netdev=eth0\0" \ 902 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 903 "loadaddr=1000000\0" \ 904 "consoledev=ttyS0\0" \ 905 "ramdiskaddr=2000000\0" \ 906 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 907 "fdtaddr=c00000\0" \ 908 "fdtfile=p1010rdb.dtb\0" \ 909 "bdev=sda1\0" \ 910 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 911 "othbootargs=ramdisk_size=600000\0" \ 912 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 913 "console=$consoledev,$baudrate $othbootargs; " \ 914 "usb start;" \ 915 "fatload usb 0:2 $loadaddr $bootfile;" \ 916 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 917 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 918 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 919 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 920 "console=$consoledev,$baudrate $othbootargs; " \ 921 "usb start;" \ 922 "ext2load usb 0:4 $loadaddr $bootfile;" \ 923 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 924 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 925 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 926 CONFIG_BOOTMODE 927 928 #if defined(CONFIG_P1010RDB_PA) 929 #define CONFIG_BOOTMODE \ 930 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 931 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 932 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 933 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 934 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 935 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 936 937 #elif defined(CONFIG_P1010RDB_PB) 938 #define CONFIG_BOOTMODE \ 939 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 940 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 941 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 942 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 943 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 944 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 945 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 946 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 947 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 948 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 949 #endif 950 951 #define CONFIG_RAMBOOTCOMMAND \ 952 "setenv bootargs root=/dev/ram rw " \ 953 "console=$consoledev,$baudrate $othbootargs; " \ 954 "tftp $ramdiskaddr $ramdiskfile;" \ 955 "tftp $loadaddr $bootfile;" \ 956 "tftp $fdtaddr $fdtfile;" \ 957 "bootm $loadaddr $ramdiskaddr $fdtaddr" 958 959 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 960 961 #include <asm/fsl_secure_boot.h> 962 963 #endif /* __CONFIG_H */ 964