1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_P1010 15 #define CONFIG_E500 /* BOOKE e500 family */ 16 #include <asm/config_mpc85xx.h> 17 #define CONFIG_NAND_FSL_IFC 18 19 #ifdef CONFIG_SDCARD 20 #define CONFIG_SPL_MMC_MINIMAL 21 #define CONFIG_SPL_FLUSH_IMAGE 22 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 23 #define CONFIG_FSL_LAW /* Use common FSL init code */ 24 #define CONFIG_SYS_TEXT_BASE 0x11001000 25 #define CONFIG_SPL_TEXT_BASE 0xD0001000 26 #define CONFIG_SPL_PAD_TO 0x18000 27 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 28 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 29 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 30 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 31 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 32 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 33 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 34 #define CONFIG_SPL_MMC_BOOT 35 #ifdef CONFIG_SPL_BUILD 36 #define CONFIG_SPL_COMMON_INIT_DDR 37 #endif 38 #endif 39 40 #ifdef CONFIG_SPIFLASH 41 #ifdef CONFIG_SECURE_BOOT 42 #define CONFIG_RAMBOOT_SPIFLASH 43 #define CONFIG_SYS_TEXT_BASE 0x11000000 44 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 45 #else 46 #define CONFIG_SPL_SPI_FLASH_MINIMAL 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 49 #define CONFIG_FSL_LAW /* Use common FSL init code */ 50 #define CONFIG_SYS_TEXT_BASE 0x11001000 51 #define CONFIG_SPL_TEXT_BASE 0xD0001000 52 #define CONFIG_SPL_PAD_TO 0x18000 53 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 58 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 60 #define CONFIG_SPL_SPI_BOOT 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_COMMON_INIT_DDR 63 #endif 64 #endif 65 #endif 66 67 #ifdef CONFIG_NAND 68 #ifdef CONFIG_SECURE_BOOT 69 #define CONFIG_SPL_INIT_MINIMAL 70 #define CONFIG_SPL_NAND_BOOT 71 #define CONFIG_SPL_FLUSH_IMAGE 72 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 73 74 #define CONFIG_SYS_TEXT_BASE 0x00201000 75 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 76 #define CONFIG_SPL_MAX_SIZE 8192 77 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 78 #define CONFIG_SPL_RELOC_STACK 0x00100000 79 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 80 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 81 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 82 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 84 #else 85 #ifdef CONFIG_TPL_BUILD 86 #define CONFIG_SPL_NAND_BOOT 87 #define CONFIG_SPL_FLUSH_IMAGE 88 #define CONFIG_SPL_NAND_INIT 89 #define CONFIG_SPL_COMMON_INIT_DDR 90 #define CONFIG_SPL_MAX_SIZE (128 << 10) 91 #define CONFIG_SPL_TEXT_BASE 0xD0001000 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 94 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 95 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 96 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 97 #elif defined(CONFIG_SPL_BUILD) 98 #define CONFIG_SPL_INIT_MINIMAL 99 #define CONFIG_SPL_NAND_MINIMAL 100 #define CONFIG_SPL_FLUSH_IMAGE 101 #define CONFIG_SPL_TEXT_BASE 0xff800000 102 #define CONFIG_SPL_MAX_SIZE 8192 103 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 104 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 105 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 106 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 107 #endif 108 #define CONFIG_SPL_PAD_TO 0x20000 109 #define CONFIG_TPL_PAD_TO 0x20000 110 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 111 #define CONFIG_SYS_TEXT_BASE 0x11001000 112 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 113 #endif 114 #endif 115 116 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 117 #define CONFIG_RAMBOOT_NAND 118 #define CONFIG_SYS_TEXT_BASE 0x11000000 119 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 120 #endif 121 122 #ifndef CONFIG_SYS_TEXT_BASE 123 #define CONFIG_SYS_TEXT_BASE 0xeff40000 124 #endif 125 126 #ifndef CONFIG_RESET_VECTOR_ADDRESS 127 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 128 #endif 129 130 #ifdef CONFIG_SPL_BUILD 131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 132 #else 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 134 #endif 135 136 /* High Level Configuration Options */ 137 #define CONFIG_BOOKE /* BOOKE */ 138 #define CONFIG_E500 /* BOOKE e500 family */ 139 #define CONFIG_FSL_IFC /* Enable IFC Support */ 140 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 141 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 142 143 #if defined(CONFIG_PCI) 144 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 145 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 146 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 147 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 148 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 149 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 150 151 #define CONFIG_CMD_PCI 152 153 /* 154 * PCI Windows 155 * Memory space is mapped 1-1, but I/O space must start from 0. 156 */ 157 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 158 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 159 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 162 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 163 #else 164 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 165 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 166 #endif 167 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 168 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 169 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 170 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 171 #ifdef CONFIG_PHYS_64BIT 172 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 173 #else 174 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 175 #endif 176 177 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 178 #if defined(CONFIG_P1010RDB_PA) 179 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 180 #elif defined(CONFIG_P1010RDB_PB) 181 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 182 #endif 183 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 184 #ifdef CONFIG_PHYS_64BIT 185 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 186 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 187 #else 188 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 189 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 190 #endif 191 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 192 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 193 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 194 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 195 #ifdef CONFIG_PHYS_64BIT 196 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 197 #else 198 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 199 #endif 200 201 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 202 #define CONFIG_DOS_PARTITION 203 #endif 204 205 #define CONFIG_FSL_LAW /* Use common FSL init code */ 206 #define CONFIG_TSEC_ENET 207 #define CONFIG_ENV_OVERWRITE 208 209 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 210 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 211 212 #define CONFIG_MISC_INIT_R 213 #define CONFIG_HWCONFIG 214 /* 215 * These can be toggled for performance analysis, otherwise use default. 216 */ 217 #define CONFIG_L2_CACHE /* toggle L2 cache */ 218 #define CONFIG_BTB /* toggle branch predition */ 219 220 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 221 222 #define CONFIG_ENABLE_36BIT_PHYS 223 224 #ifdef CONFIG_PHYS_64BIT 225 #define CONFIG_ADDR_MAP 1 226 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 227 #endif 228 229 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 230 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 231 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 232 233 /* DDR Setup */ 234 #define CONFIG_SYS_FSL_DDR3 235 #define CONFIG_SYS_DDR_RAW_TIMING 236 #define CONFIG_DDR_SPD 237 #define CONFIG_SYS_SPD_BUS_NUM 1 238 #define SPD_EEPROM_ADDRESS 0x52 239 240 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 241 242 #ifndef __ASSEMBLY__ 243 extern unsigned long get_sdram_size(void); 244 #endif 245 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 246 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 247 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 248 249 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 250 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 251 252 /* DDR3 Controller Settings */ 253 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 254 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 255 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 256 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 257 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 258 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 259 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 260 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 261 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 262 #define CONFIG_SYS_DDR_RCW_1 0x00000000 263 #define CONFIG_SYS_DDR_RCW_2 0x00000000 264 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 265 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 266 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 267 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 268 269 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 270 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 271 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 272 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 273 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 274 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 275 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 276 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 277 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 278 279 /* settings for DDR3 at 667MT/s */ 280 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 281 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 282 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 283 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 284 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 285 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 286 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 287 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 288 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 289 290 #define CONFIG_SYS_CCSRBAR 0xffe00000 291 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 292 293 /* Don't relocate CCSRBAR while in NAND_SPL */ 294 #ifdef CONFIG_SPL_BUILD 295 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 296 #endif 297 298 /* 299 * Memory map 300 * 301 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 302 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 303 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 304 * 305 * Localbus non-cacheable 306 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 307 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 308 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 309 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 310 */ 311 312 /* 313 * IFC Definitions 314 */ 315 /* NOR Flash on IFC */ 316 #ifdef CONFIG_SPL_BUILD 317 #define CONFIG_SYS_NO_FLASH 318 #endif 319 320 #define CONFIG_SYS_FLASH_BASE 0xee000000 321 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 322 323 #ifdef CONFIG_PHYS_64BIT 324 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 325 #else 326 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 327 #endif 328 329 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 330 CSPR_PORT_SIZE_16 | \ 331 CSPR_MSEL_NOR | \ 332 CSPR_V) 333 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 334 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 335 /* NOR Flash Timing Params */ 336 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 337 FTIM0_NOR_TEADC(0x5) | \ 338 FTIM0_NOR_TEAHC(0x5) 339 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 340 FTIM1_NOR_TRAD_NOR(0x0f) 341 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 342 FTIM2_NOR_TCH(0x4) | \ 343 FTIM2_NOR_TWP(0x1c) 344 #define CONFIG_SYS_NOR_FTIM3 0x0 345 346 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 347 #define CONFIG_SYS_FLASH_QUIET_TEST 348 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 349 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 350 351 #undef CONFIG_SYS_FLASH_CHECKSUM 352 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 353 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 354 355 /* CFI for NOR Flash */ 356 #define CONFIG_FLASH_CFI_DRIVER 357 #define CONFIG_SYS_FLASH_CFI 358 #define CONFIG_SYS_FLASH_EMPTY_INFO 359 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 360 361 /* NAND Flash on IFC */ 362 #define CONFIG_SYS_NAND_BASE 0xff800000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 365 #else 366 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 367 #endif 368 369 #define CONFIG_MTD_DEVICE 370 #define CONFIG_MTD_PARTITION 371 #define CONFIG_CMD_MTDPARTS 372 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 373 #define MTDPARTS_DEFAULT \ 374 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 375 376 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 377 | CSPR_PORT_SIZE_8 \ 378 | CSPR_MSEL_NAND \ 379 | CSPR_V) 380 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 381 382 #if defined(CONFIG_P1010RDB_PA) 383 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 384 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 385 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 386 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 387 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 388 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 389 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 390 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 391 392 #elif defined(CONFIG_P1010RDB_PB) 393 #define CONFIG_SYS_NAND_ONFI_DETECTION 394 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 395 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 396 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 397 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 398 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 399 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 400 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 401 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 402 #endif 403 404 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 405 #define CONFIG_SYS_MAX_NAND_DEVICE 1 406 #define CONFIG_CMD_NAND 407 408 #if defined(CONFIG_P1010RDB_PA) 409 /* NAND Flash Timing Params */ 410 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 411 FTIM0_NAND_TWP(0x0C) | \ 412 FTIM0_NAND_TWCHT(0x04) | \ 413 FTIM0_NAND_TWH(0x05) 414 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 415 FTIM1_NAND_TWBE(0x1d) | \ 416 FTIM1_NAND_TRR(0x07) | \ 417 FTIM1_NAND_TRP(0x0c) 418 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 419 FTIM2_NAND_TREH(0x05) | \ 420 FTIM2_NAND_TWHRE(0x0f) 421 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 422 423 #elif defined(CONFIG_P1010RDB_PB) 424 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 425 /* ONFI NAND Flash mode0 Timing Params */ 426 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 427 FTIM0_NAND_TWP(0x18) | \ 428 FTIM0_NAND_TWCHT(0x07) | \ 429 FTIM0_NAND_TWH(0x0a)) 430 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 431 FTIM1_NAND_TWBE(0x39) | \ 432 FTIM1_NAND_TRR(0x0e) | \ 433 FTIM1_NAND_TRP(0x18)) 434 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 435 FTIM2_NAND_TREH(0x0a) | \ 436 FTIM2_NAND_TWHRE(0x1e)) 437 #define CONFIG_SYS_NAND_FTIM3 0x0 438 #endif 439 440 #define CONFIG_SYS_NAND_DDR_LAW 11 441 442 /* Set up IFC registers for boot location NOR/NAND */ 443 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 444 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 445 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 446 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 447 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 448 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 449 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 450 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 451 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 452 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 453 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 454 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 455 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 456 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 457 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 458 #else 459 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 460 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 461 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 462 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 463 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 464 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 465 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 466 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 467 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 468 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 469 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 470 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 471 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 472 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 473 #endif 474 475 /* CPLD on IFC */ 476 #define CONFIG_SYS_CPLD_BASE 0xffb00000 477 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 480 #else 481 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 482 #endif 483 484 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 485 | CSPR_PORT_SIZE_8 \ 486 | CSPR_MSEL_GPCM \ 487 | CSPR_V) 488 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 489 #define CONFIG_SYS_CSOR3 0x0 490 /* CPLD Timing parameters for IFC CS3 */ 491 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 492 FTIM0_GPCM_TEADC(0x0e) | \ 493 FTIM0_GPCM_TEAHC(0x0e)) 494 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 495 FTIM1_GPCM_TRAD(0x1f)) 496 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 497 FTIM2_GPCM_TCH(0x8) | \ 498 FTIM2_GPCM_TWP(0x1f)) 499 #define CONFIG_SYS_CS3_FTIM3 0x0 500 501 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 502 defined(CONFIG_RAMBOOT_NAND) 503 #define CONFIG_SYS_RAMBOOT 504 #define CONFIG_SYS_EXTRA_ENV_RELOC 505 #else 506 #undef CONFIG_SYS_RAMBOOT 507 #endif 508 509 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 510 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 511 #define CONFIG_A003399_NOR_WORKAROUND 512 #endif 513 #endif 514 515 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 516 #define CONFIG_BOARD_EARLY_INIT_R 517 518 #define CONFIG_SYS_INIT_RAM_LOCK 519 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 520 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 521 522 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 523 - GENERATED_GBL_DATA_SIZE) 524 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 525 526 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 527 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 528 529 /* 530 * Config the L2 Cache as L2 SRAM 531 */ 532 #if defined(CONFIG_SPL_BUILD) 533 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 534 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 535 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 536 #define CONFIG_SYS_L2_SIZE (256 << 10) 537 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 538 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 539 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 540 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 541 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 542 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 543 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 544 #elif defined(CONFIG_NAND) 545 #ifdef CONFIG_TPL_BUILD 546 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 547 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 548 #define CONFIG_SYS_L2_SIZE (256 << 10) 549 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 550 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 551 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 552 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 553 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 554 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 555 #else 556 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 557 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 558 #define CONFIG_SYS_L2_SIZE (256 << 10) 559 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 560 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 561 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 562 #endif 563 #endif 564 #endif 565 566 /* Serial Port */ 567 #define CONFIG_CONS_INDEX 1 568 #undef CONFIG_SERIAL_SOFTWARE_FIFO 569 #define CONFIG_SYS_NS16550_SERIAL 570 #define CONFIG_SYS_NS16550_REG_SIZE 1 571 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 572 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 573 #define CONFIG_NS16550_MIN_FUNCTIONS 574 #endif 575 576 #define CONFIG_SYS_BAUDRATE_TABLE \ 577 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 578 579 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 580 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 581 582 /* I2C */ 583 #define CONFIG_SYS_I2C 584 #define CONFIG_SYS_I2C_FSL 585 #define CONFIG_SYS_FSL_I2C_SPEED 400000 586 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 587 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 588 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 589 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 590 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 591 #define I2C_PCA9557_ADDR1 0x18 592 #define I2C_PCA9557_ADDR2 0x19 593 #define I2C_PCA9557_BUS_NUM 0 594 595 /* I2C EEPROM */ 596 #if defined(CONFIG_P1010RDB_PB) 597 #define CONFIG_ID_EEPROM 598 #ifdef CONFIG_ID_EEPROM 599 #define CONFIG_SYS_I2C_EEPROM_NXID 600 #endif 601 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 602 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 603 #define CONFIG_SYS_EEPROM_BUS_NUM 0 604 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 605 #endif 606 /* enable read and write access to EEPROM */ 607 #define CONFIG_CMD_EEPROM 608 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 609 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 610 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 611 612 /* RTC */ 613 #define CONFIG_RTC_PT7C4338 614 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 615 616 /* 617 * SPI interface will not be available in case of NAND boot SPI CS0 will be 618 * used for SLIC 619 */ 620 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 621 /* eSPI - Enhanced SPI */ 622 #define CONFIG_SF_DEFAULT_SPEED 10000000 623 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 624 #endif 625 626 #if defined(CONFIG_TSEC_ENET) 627 #define CONFIG_MII /* MII PHY management */ 628 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 629 #define CONFIG_TSEC1 1 630 #define CONFIG_TSEC1_NAME "eTSEC1" 631 #define CONFIG_TSEC2 1 632 #define CONFIG_TSEC2_NAME "eTSEC2" 633 #define CONFIG_TSEC3 1 634 #define CONFIG_TSEC3_NAME "eTSEC3" 635 636 #define TSEC1_PHY_ADDR 1 637 #define TSEC2_PHY_ADDR 0 638 #define TSEC3_PHY_ADDR 2 639 640 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 641 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 642 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 643 644 #define TSEC1_PHYIDX 0 645 #define TSEC2_PHYIDX 0 646 #define TSEC3_PHYIDX 0 647 648 #define CONFIG_ETHPRIME "eTSEC1" 649 650 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 651 652 /* TBI PHY configuration for SGMII mode */ 653 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 654 TBICR_PHY_RESET \ 655 | TBICR_ANEG_ENABLE \ 656 | TBICR_FULL_DUPLEX \ 657 | TBICR_SPEED1_SET \ 658 ) 659 660 #endif /* CONFIG_TSEC_ENET */ 661 662 /* SATA */ 663 #define CONFIG_FSL_SATA 664 #define CONFIG_FSL_SATA_V2 665 #define CONFIG_LIBATA 666 667 #ifdef CONFIG_FSL_SATA 668 #define CONFIG_SYS_SATA_MAX_DEVICE 2 669 #define CONFIG_SATA1 670 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 671 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 672 #define CONFIG_SATA2 673 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 674 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 675 676 #define CONFIG_CMD_SATA 677 #define CONFIG_LBA48 678 #endif /* #ifdef CONFIG_FSL_SATA */ 679 680 #define CONFIG_MMC 681 #ifdef CONFIG_MMC 682 #define CONFIG_DOS_PARTITION 683 #define CONFIG_FSL_ESDHC 684 #define CONFIG_GENERIC_MMC 685 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 686 #endif 687 688 #define CONFIG_HAS_FSL_DR_USB 689 690 #if defined(CONFIG_HAS_FSL_DR_USB) 691 #define CONFIG_USB_EHCI 692 693 #ifdef CONFIG_USB_EHCI 694 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 695 #define CONFIG_USB_EHCI_FSL 696 #endif 697 #endif 698 699 /* 700 * Environment 701 */ 702 #if defined(CONFIG_SDCARD) 703 #define CONFIG_ENV_IS_IN_MMC 704 #define CONFIG_FSL_FIXED_MMC_LOCATION 705 #define CONFIG_SYS_MMC_ENV_DEV 0 706 #define CONFIG_ENV_SIZE 0x2000 707 #elif defined(CONFIG_SPIFLASH) 708 #define CONFIG_ENV_IS_IN_SPI_FLASH 709 #define CONFIG_ENV_SPI_BUS 0 710 #define CONFIG_ENV_SPI_CS 0 711 #define CONFIG_ENV_SPI_MAX_HZ 10000000 712 #define CONFIG_ENV_SPI_MODE 0 713 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 714 #define CONFIG_ENV_SECT_SIZE 0x10000 715 #define CONFIG_ENV_SIZE 0x2000 716 #elif defined(CONFIG_NAND) 717 #define CONFIG_ENV_IS_IN_NAND 718 #ifdef CONFIG_TPL_BUILD 719 #define CONFIG_ENV_SIZE 0x2000 720 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 721 #else 722 #if defined(CONFIG_P1010RDB_PA) 723 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 724 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 725 #elif defined(CONFIG_P1010RDB_PB) 726 #define CONFIG_ENV_SIZE (16 * 1024) 727 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 728 #endif 729 #endif 730 #define CONFIG_ENV_OFFSET (1024 * 1024) 731 #elif defined(CONFIG_SYS_RAMBOOT) 732 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 733 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 734 #define CONFIG_ENV_SIZE 0x2000 735 #else 736 #define CONFIG_ENV_IS_IN_FLASH 737 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 738 #define CONFIG_ENV_SIZE 0x2000 739 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 740 #endif 741 742 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 743 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 744 745 /* 746 * Command line configuration. 747 */ 748 #define CONFIG_CMD_DATE 749 #define CONFIG_CMD_ERRATA 750 #define CONFIG_CMD_IRQ 751 #define CONFIG_CMD_REGINFO 752 753 #undef CONFIG_WATCHDOG /* watchdog disabled */ 754 755 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 756 || defined(CONFIG_FSL_SATA) 757 #define CONFIG_DOS_PARTITION 758 #endif 759 760 /* Hash command with SHA acceleration supported in hardware */ 761 #ifdef CONFIG_FSL_CAAM 762 #define CONFIG_CMD_HASH 763 #define CONFIG_SHA_HW_ACCEL 764 #endif 765 766 /* 767 * Miscellaneous configurable options 768 */ 769 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 770 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 771 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 772 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 773 774 #if defined(CONFIG_CMD_KGDB) 775 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 776 #else 777 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 778 #endif 779 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 780 /* Print Buffer Size */ 781 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 782 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 783 784 /* 785 * For booting Linux, the board info and command line data 786 * have to be in the first 64 MB of memory, since this is 787 * the maximum mapped by the Linux kernel during initialization. 788 */ 789 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 790 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 791 792 #if defined(CONFIG_CMD_KGDB) 793 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 794 #endif 795 796 /* 797 * Environment Configuration 798 */ 799 800 #if defined(CONFIG_TSEC_ENET) 801 #define CONFIG_HAS_ETH0 802 #define CONFIG_HAS_ETH1 803 #define CONFIG_HAS_ETH2 804 #endif 805 806 #define CONFIG_ROOTPATH "/opt/nfsroot" 807 #define CONFIG_BOOTFILE "uImage" 808 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 809 810 /* default location for tftp and bootm */ 811 #define CONFIG_LOADADDR 1000000 812 813 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 814 815 #define CONFIG_BAUDRATE 115200 816 817 #define CONFIG_EXTRA_ENV_SETTINGS \ 818 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 819 "netdev=eth0\0" \ 820 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 821 "loadaddr=1000000\0" \ 822 "consoledev=ttyS0\0" \ 823 "ramdiskaddr=2000000\0" \ 824 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 825 "fdtaddr=1e00000\0" \ 826 "fdtfile=p1010rdb.dtb\0" \ 827 "bdev=sda1\0" \ 828 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 829 "othbootargs=ramdisk_size=600000\0" \ 830 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 831 "console=$consoledev,$baudrate $othbootargs; " \ 832 "usb start;" \ 833 "fatload usb 0:2 $loadaddr $bootfile;" \ 834 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 835 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 836 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 837 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 838 "console=$consoledev,$baudrate $othbootargs; " \ 839 "usb start;" \ 840 "ext2load usb 0:4 $loadaddr $bootfile;" \ 841 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 842 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 843 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 844 CONFIG_BOOTMODE 845 846 #if defined(CONFIG_P1010RDB_PA) 847 #define CONFIG_BOOTMODE \ 848 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 849 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 850 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 851 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 852 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 853 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 854 855 #elif defined(CONFIG_P1010RDB_PB) 856 #define CONFIG_BOOTMODE \ 857 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 858 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 859 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 860 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 861 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 862 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 863 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 864 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 865 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 866 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 867 #endif 868 869 #define CONFIG_RAMBOOTCOMMAND \ 870 "setenv bootargs root=/dev/ram rw " \ 871 "console=$consoledev,$baudrate $othbootargs; " \ 872 "tftp $ramdiskaddr $ramdiskfile;" \ 873 "tftp $loadaddr $bootfile;" \ 874 "tftp $fdtaddr $fdtfile;" \ 875 "bootm $loadaddr $ramdiskaddr $fdtaddr" 876 877 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 878 879 #include <asm/fsl_secure_boot.h> 880 881 #endif /* __CONFIG_H */ 882