1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * P010 RDB board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/config_mpc85xx.h> 14 #define CONFIG_NAND_FSL_IFC 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_FLUSH_IMAGE 18 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 19 #define CONFIG_SPL_TEXT_BASE 0xD0001000 20 #define CONFIG_SPL_PAD_TO 0x18000 21 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 27 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 28 #define CONFIG_SPL_MMC_BOOT 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #endif 32 #endif 33 34 #ifdef CONFIG_SPIFLASH 35 #ifdef CONFIG_SECURE_BOOT 36 #define CONFIG_RAMBOOT_SPIFLASH 37 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 38 #else 39 #define CONFIG_SPL_SPI_FLASH_MINIMAL 40 #define CONFIG_SPL_FLUSH_IMAGE 41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 42 #define CONFIG_SPL_TEXT_BASE 0xD0001000 43 #define CONFIG_SPL_PAD_TO 0x18000 44 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 49 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 51 #define CONFIG_SPL_SPI_BOOT 52 #ifdef CONFIG_SPL_BUILD 53 #define CONFIG_SPL_COMMON_INIT_DDR 54 #endif 55 #endif 56 #endif 57 58 #ifdef CONFIG_NAND 59 #ifdef CONFIG_SECURE_BOOT 60 #define CONFIG_SPL_INIT_MINIMAL 61 #define CONFIG_SPL_NAND_BOOT 62 #define CONFIG_SPL_FLUSH_IMAGE 63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 64 65 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 66 #define CONFIG_SPL_MAX_SIZE 8192 67 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 68 #define CONFIG_SPL_RELOC_STACK 0x00100000 69 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 70 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 71 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 72 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 74 #else 75 #ifdef CONFIG_TPL_BUILD 76 #define CONFIG_SPL_NAND_BOOT 77 #define CONFIG_SPL_FLUSH_IMAGE 78 #define CONFIG_SPL_NAND_INIT 79 #define CONFIG_SPL_COMMON_INIT_DDR 80 #define CONFIG_SPL_MAX_SIZE (128 << 10) 81 #define CONFIG_SPL_TEXT_BASE 0xD0001000 82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 83 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 84 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 85 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 86 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 87 #elif defined(CONFIG_SPL_BUILD) 88 #define CONFIG_SPL_INIT_MINIMAL 89 #define CONFIG_SPL_NAND_MINIMAL 90 #define CONFIG_SPL_FLUSH_IMAGE 91 #define CONFIG_SPL_TEXT_BASE 0xff800000 92 #define CONFIG_SPL_MAX_SIZE 8192 93 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 94 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 95 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 96 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 97 #endif 98 #define CONFIG_SPL_PAD_TO 0x20000 99 #define CONFIG_TPL_PAD_TO 0x20000 100 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 101 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 102 #endif 103 #endif 104 105 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 106 #define CONFIG_RAMBOOT_NAND 107 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 108 #endif 109 110 #ifndef CONFIG_RESET_VECTOR_ADDRESS 111 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 112 #endif 113 114 #ifdef CONFIG_SPL_BUILD 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 116 #else 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 118 #endif 119 120 /* High Level Configuration Options */ 121 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 122 123 #if defined(CONFIG_PCI) 124 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 125 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 126 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 127 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 128 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 129 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 130 131 /* 132 * PCI Windows 133 * Memory space is mapped 1-1, but I/O space must start from 0. 134 */ 135 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 136 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 137 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 138 #ifdef CONFIG_PHYS_64BIT 139 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 140 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 141 #else 142 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 143 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 144 #endif 145 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 146 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 147 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 148 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 149 #ifdef CONFIG_PHYS_64BIT 150 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 151 #else 152 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 153 #endif 154 155 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 156 #if defined(CONFIG_TARGET_P1010RDB_PA) 157 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 158 #elif defined(CONFIG_TARGET_P1010RDB_PB) 159 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 160 #endif 161 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 162 #ifdef CONFIG_PHYS_64BIT 163 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 164 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 165 #else 166 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 167 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 168 #endif 169 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 170 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 171 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 172 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 173 #ifdef CONFIG_PHYS_64BIT 174 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 175 #else 176 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 177 #endif 178 179 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 180 #endif 181 182 #define CONFIG_ENV_OVERWRITE 183 184 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 185 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 186 187 #define CONFIG_HWCONFIG 188 /* 189 * These can be toggled for performance analysis, otherwise use default. 190 */ 191 #define CONFIG_L2_CACHE /* toggle L2 cache */ 192 #define CONFIG_BTB /* toggle branch predition */ 193 194 195 #define CONFIG_ENABLE_36BIT_PHYS 196 197 #ifdef CONFIG_PHYS_64BIT 198 #define CONFIG_ADDR_MAP 1 199 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 200 #endif 201 202 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 203 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 204 205 /* DDR Setup */ 206 #define CONFIG_SYS_DDR_RAW_TIMING 207 #define CONFIG_DDR_SPD 208 #define CONFIG_SYS_SPD_BUS_NUM 1 209 #define SPD_EEPROM_ADDRESS 0x52 210 211 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 212 213 #ifndef __ASSEMBLY__ 214 extern unsigned long get_sdram_size(void); 215 #endif 216 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 217 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 218 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 219 220 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 221 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 222 223 /* DDR3 Controller Settings */ 224 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 225 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 226 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 227 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 228 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 229 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 230 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 231 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 232 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 233 #define CONFIG_SYS_DDR_RCW_1 0x00000000 234 #define CONFIG_SYS_DDR_RCW_2 0x00000000 235 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 236 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 237 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 238 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 239 240 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 241 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 242 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 243 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 244 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 245 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 246 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 247 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 248 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 249 250 /* settings for DDR3 at 667MT/s */ 251 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 252 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 253 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 254 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 255 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 256 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 257 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 258 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 259 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 260 261 #define CONFIG_SYS_CCSRBAR 0xffe00000 262 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 263 264 /* Don't relocate CCSRBAR while in NAND_SPL */ 265 #ifdef CONFIG_SPL_BUILD 266 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 267 #endif 268 269 /* 270 * Memory map 271 * 272 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 273 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 274 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 275 * 276 * Localbus non-cacheable 277 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 278 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 279 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 280 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 281 */ 282 283 /* 284 * IFC Definitions 285 */ 286 /* NOR Flash on IFC */ 287 288 #define CONFIG_SYS_FLASH_BASE 0xee000000 289 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 290 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 293 #else 294 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 295 #endif 296 297 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 298 CSPR_PORT_SIZE_16 | \ 299 CSPR_MSEL_NOR | \ 300 CSPR_V) 301 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 302 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 303 /* NOR Flash Timing Params */ 304 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 305 FTIM0_NOR_TEADC(0x5) | \ 306 FTIM0_NOR_TEAHC(0x5) 307 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 308 FTIM1_NOR_TRAD_NOR(0x0f) 309 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 310 FTIM2_NOR_TCH(0x4) | \ 311 FTIM2_NOR_TWP(0x1c) 312 #define CONFIG_SYS_NOR_FTIM3 0x0 313 314 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 315 #define CONFIG_SYS_FLASH_QUIET_TEST 316 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 317 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 318 319 #undef CONFIG_SYS_FLASH_CHECKSUM 320 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 321 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 322 323 /* CFI for NOR Flash */ 324 #define CONFIG_FLASH_CFI_DRIVER 325 #define CONFIG_SYS_FLASH_CFI 326 #define CONFIG_SYS_FLASH_EMPTY_INFO 327 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 328 329 /* NAND Flash on IFC */ 330 #define CONFIG_SYS_NAND_BASE 0xff800000 331 #ifdef CONFIG_PHYS_64BIT 332 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 333 #else 334 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 335 #endif 336 337 #define CONFIG_MTD_PARTITION 338 339 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 340 | CSPR_PORT_SIZE_8 \ 341 | CSPR_MSEL_NAND \ 342 | CSPR_V) 343 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 344 345 #if defined(CONFIG_TARGET_P1010RDB_PA) 346 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 347 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 348 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 349 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 350 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 351 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 352 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 353 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 354 355 #elif defined(CONFIG_TARGET_P1010RDB_PB) 356 #define CONFIG_SYS_NAND_ONFI_DETECTION 357 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 358 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 359 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 360 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 361 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 362 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 363 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 364 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 365 #endif 366 367 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 368 #define CONFIG_SYS_MAX_NAND_DEVICE 1 369 370 #if defined(CONFIG_TARGET_P1010RDB_PA) 371 /* NAND Flash Timing Params */ 372 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 373 FTIM0_NAND_TWP(0x0C) | \ 374 FTIM0_NAND_TWCHT(0x04) | \ 375 FTIM0_NAND_TWH(0x05) 376 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 377 FTIM1_NAND_TWBE(0x1d) | \ 378 FTIM1_NAND_TRR(0x07) | \ 379 FTIM1_NAND_TRP(0x0c) 380 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 381 FTIM2_NAND_TREH(0x05) | \ 382 FTIM2_NAND_TWHRE(0x0f) 383 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 384 385 #elif defined(CONFIG_TARGET_P1010RDB_PB) 386 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 387 /* ONFI NAND Flash mode0 Timing Params */ 388 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 389 FTIM0_NAND_TWP(0x18) | \ 390 FTIM0_NAND_TWCHT(0x07) | \ 391 FTIM0_NAND_TWH(0x0a)) 392 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 393 FTIM1_NAND_TWBE(0x39) | \ 394 FTIM1_NAND_TRR(0x0e) | \ 395 FTIM1_NAND_TRP(0x18)) 396 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 397 FTIM2_NAND_TREH(0x0a) | \ 398 FTIM2_NAND_TWHRE(0x1e)) 399 #define CONFIG_SYS_NAND_FTIM3 0x0 400 #endif 401 402 #define CONFIG_SYS_NAND_DDR_LAW 11 403 404 /* Set up IFC registers for boot location NOR/NAND */ 405 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 406 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 407 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 408 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 409 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 410 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 411 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 412 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 413 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 414 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 415 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 416 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 417 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 418 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 419 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 420 #else 421 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 422 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 423 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 424 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 425 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 426 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 427 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 428 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 429 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 430 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 431 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 432 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 433 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 434 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 435 #endif 436 437 /* CPLD on IFC */ 438 #define CONFIG_SYS_CPLD_BASE 0xffb00000 439 440 #ifdef CONFIG_PHYS_64BIT 441 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 442 #else 443 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 444 #endif 445 446 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 447 | CSPR_PORT_SIZE_8 \ 448 | CSPR_MSEL_GPCM \ 449 | CSPR_V) 450 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 451 #define CONFIG_SYS_CSOR3 0x0 452 /* CPLD Timing parameters for IFC CS3 */ 453 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 454 FTIM0_GPCM_TEADC(0x0e) | \ 455 FTIM0_GPCM_TEAHC(0x0e)) 456 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 457 FTIM1_GPCM_TRAD(0x1f)) 458 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 459 FTIM2_GPCM_TCH(0x8) | \ 460 FTIM2_GPCM_TWP(0x1f)) 461 #define CONFIG_SYS_CS3_FTIM3 0x0 462 463 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 464 defined(CONFIG_RAMBOOT_NAND) 465 #define CONFIG_SYS_RAMBOOT 466 #else 467 #undef CONFIG_SYS_RAMBOOT 468 #endif 469 470 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 471 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 472 #define CONFIG_A003399_NOR_WORKAROUND 473 #endif 474 #endif 475 476 #define CONFIG_SYS_INIT_RAM_LOCK 477 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 478 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 479 480 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 481 - GENERATED_GBL_DATA_SIZE) 482 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 483 484 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 485 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 486 487 /* 488 * Config the L2 Cache as L2 SRAM 489 */ 490 #if defined(CONFIG_SPL_BUILD) 491 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 492 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 493 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 494 #define CONFIG_SYS_L2_SIZE (256 << 10) 495 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 496 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 497 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 498 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 499 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 500 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 501 #elif defined(CONFIG_NAND) 502 #ifdef CONFIG_TPL_BUILD 503 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 504 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 505 #define CONFIG_SYS_L2_SIZE (256 << 10) 506 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 507 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 508 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 509 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 510 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 511 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 512 #else 513 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 514 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 515 #define CONFIG_SYS_L2_SIZE (256 << 10) 516 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 517 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 518 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 519 #endif 520 #endif 521 #endif 522 523 /* Serial Port */ 524 #undef CONFIG_SERIAL_SOFTWARE_FIFO 525 #define CONFIG_SYS_NS16550_SERIAL 526 #define CONFIG_SYS_NS16550_REG_SIZE 1 527 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 528 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 529 #define CONFIG_NS16550_MIN_FUNCTIONS 530 #endif 531 532 #define CONFIG_SYS_BAUDRATE_TABLE \ 533 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 534 535 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 536 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 537 538 /* I2C */ 539 #define CONFIG_SYS_I2C 540 #define CONFIG_SYS_I2C_FSL 541 #define CONFIG_SYS_FSL_I2C_SPEED 400000 542 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 543 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 544 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 545 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 546 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 547 #define I2C_PCA9557_ADDR1 0x18 548 #define I2C_PCA9557_ADDR2 0x19 549 #define I2C_PCA9557_BUS_NUM 0 550 551 /* I2C EEPROM */ 552 #if defined(CONFIG_TARGET_P1010RDB_PB) 553 #define CONFIG_ID_EEPROM 554 #ifdef CONFIG_ID_EEPROM 555 #define CONFIG_SYS_I2C_EEPROM_NXID 556 #endif 557 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 558 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 559 #define CONFIG_SYS_EEPROM_BUS_NUM 0 560 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 561 #endif 562 /* enable read and write access to EEPROM */ 563 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 564 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 565 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 566 567 /* RTC */ 568 #define CONFIG_RTC_PT7C4338 569 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 570 571 /* 572 * SPI interface will not be available in case of NAND boot SPI CS0 will be 573 * used for SLIC 574 */ 575 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 576 /* eSPI - Enhanced SPI */ 577 #define CONFIG_SF_DEFAULT_SPEED 10000000 578 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 579 #endif 580 581 #if defined(CONFIG_TSEC_ENET) 582 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 583 #define CONFIG_TSEC1 1 584 #define CONFIG_TSEC1_NAME "eTSEC1" 585 #define CONFIG_TSEC2 1 586 #define CONFIG_TSEC2_NAME "eTSEC2" 587 #define CONFIG_TSEC3 1 588 #define CONFIG_TSEC3_NAME "eTSEC3" 589 590 #define TSEC1_PHY_ADDR 1 591 #define TSEC2_PHY_ADDR 0 592 #define TSEC3_PHY_ADDR 2 593 594 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 595 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 596 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 597 598 #define TSEC1_PHYIDX 0 599 #define TSEC2_PHYIDX 0 600 #define TSEC3_PHYIDX 0 601 602 #define CONFIG_ETHPRIME "eTSEC1" 603 604 /* TBI PHY configuration for SGMII mode */ 605 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 606 TBICR_PHY_RESET \ 607 | TBICR_ANEG_ENABLE \ 608 | TBICR_FULL_DUPLEX \ 609 | TBICR_SPEED1_SET \ 610 ) 611 612 #endif /* CONFIG_TSEC_ENET */ 613 614 /* SATA */ 615 #define CONFIG_FSL_SATA_V2 616 617 #ifdef CONFIG_FSL_SATA 618 #define CONFIG_SYS_SATA_MAX_DEVICE 2 619 #define CONFIG_SATA1 620 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 621 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 622 #define CONFIG_SATA2 623 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 624 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 625 626 #define CONFIG_LBA48 627 #endif /* #ifdef CONFIG_FSL_SATA */ 628 629 #ifdef CONFIG_MMC 630 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 631 #endif 632 633 #define CONFIG_HAS_FSL_DR_USB 634 635 #if defined(CONFIG_HAS_FSL_DR_USB) 636 #ifdef CONFIG_USB_EHCI_HCD 637 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 638 #define CONFIG_USB_EHCI_FSL 639 #endif 640 #endif 641 642 /* 643 * Environment 644 */ 645 #if defined(CONFIG_SDCARD) 646 #define CONFIG_FSL_FIXED_MMC_LOCATION 647 #define CONFIG_SYS_MMC_ENV_DEV 0 648 #define CONFIG_ENV_SIZE 0x2000 649 #elif defined(CONFIG_SPIFLASH) 650 #define CONFIG_ENV_SPI_BUS 0 651 #define CONFIG_ENV_SPI_CS 0 652 #define CONFIG_ENV_SPI_MAX_HZ 10000000 653 #define CONFIG_ENV_SPI_MODE 0 654 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 655 #define CONFIG_ENV_SECT_SIZE 0x10000 656 #define CONFIG_ENV_SIZE 0x2000 657 #elif defined(CONFIG_NAND) 658 #ifdef CONFIG_TPL_BUILD 659 #define CONFIG_ENV_SIZE 0x2000 660 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 661 #else 662 #if defined(CONFIG_TARGET_P1010RDB_PA) 663 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 664 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 665 #elif defined(CONFIG_TARGET_P1010RDB_PB) 666 #define CONFIG_ENV_SIZE (16 * 1024) 667 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 668 #endif 669 #endif 670 #define CONFIG_ENV_OFFSET (1024 * 1024) 671 #elif defined(CONFIG_SYS_RAMBOOT) 672 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 673 #define CONFIG_ENV_SIZE 0x2000 674 #else 675 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 676 #define CONFIG_ENV_SIZE 0x2000 677 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 678 #endif 679 680 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 681 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 682 683 #undef CONFIG_WATCHDOG /* watchdog disabled */ 684 685 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ 686 || defined(CONFIG_FSL_SATA) 687 #endif 688 689 /* 690 * Miscellaneous configurable options 691 */ 692 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 693 694 /* 695 * For booting Linux, the board info and command line data 696 * have to be in the first 64 MB of memory, since this is 697 * the maximum mapped by the Linux kernel during initialization. 698 */ 699 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 700 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 701 702 #if defined(CONFIG_CMD_KGDB) 703 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 704 #endif 705 706 /* 707 * Environment Configuration 708 */ 709 710 #if defined(CONFIG_TSEC_ENET) 711 #define CONFIG_HAS_ETH0 712 #define CONFIG_HAS_ETH1 713 #define CONFIG_HAS_ETH2 714 #endif 715 716 #define CONFIG_ROOTPATH "/opt/nfsroot" 717 #define CONFIG_BOOTFILE "uImage" 718 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 719 720 /* default location for tftp and bootm */ 721 #define CONFIG_LOADADDR 1000000 722 723 #define CONFIG_EXTRA_ENV_SETTINGS \ 724 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 725 "netdev=eth0\0" \ 726 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 727 "loadaddr=1000000\0" \ 728 "consoledev=ttyS0\0" \ 729 "ramdiskaddr=2000000\0" \ 730 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 731 "fdtaddr=1e00000\0" \ 732 "fdtfile=p1010rdb.dtb\0" \ 733 "bdev=sda1\0" \ 734 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 735 "othbootargs=ramdisk_size=600000\0" \ 736 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 737 "console=$consoledev,$baudrate $othbootargs; " \ 738 "usb start;" \ 739 "fatload usb 0:2 $loadaddr $bootfile;" \ 740 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 741 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 742 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 743 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 744 "console=$consoledev,$baudrate $othbootargs; " \ 745 "usb start;" \ 746 "ext2load usb 0:4 $loadaddr $bootfile;" \ 747 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 748 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 749 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 750 CONFIG_BOOTMODE 751 752 #if defined(CONFIG_TARGET_P1010RDB_PA) 753 #define CONFIG_BOOTMODE \ 754 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 755 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 756 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 757 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 758 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 759 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 760 761 #elif defined(CONFIG_TARGET_P1010RDB_PB) 762 #define CONFIG_BOOTMODE \ 763 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 764 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 765 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 766 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 767 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 768 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 769 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 770 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 771 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 772 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 773 #endif 774 775 #define CONFIG_RAMBOOTCOMMAND \ 776 "setenv bootargs root=/dev/ram rw " \ 777 "console=$consoledev,$baudrate $othbootargs; " \ 778 "tftp $ramdiskaddr $ramdiskfile;" \ 779 "tftp $loadaddr $bootfile;" \ 780 "tftp $fdtaddr $fdtfile;" \ 781 "bootm $loadaddr $ramdiskaddr $fdtaddr" 782 783 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 784 785 #include <asm/fsl_secure_boot.h> 786 787 #endif /* __CONFIG_H */ 788