1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/config_mpc85xx.h> 15 #define CONFIG_NAND_FSL_IFC 16 17 #ifdef CONFIG_SDCARD 18 #define CONFIG_SPL_MMC_MINIMAL 19 #define CONFIG_SPL_FLUSH_IMAGE 20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 21 #define CONFIG_SYS_TEXT_BASE 0x11001000 22 #define CONFIG_SPL_TEXT_BASE 0xD0001000 23 #define CONFIG_SPL_PAD_TO 0x18000 24 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 25 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 29 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 31 #define CONFIG_SPL_MMC_BOOT 32 #ifdef CONFIG_SPL_BUILD 33 #define CONFIG_SPL_COMMON_INIT_DDR 34 #endif 35 #endif 36 37 #ifdef CONFIG_SPIFLASH 38 #ifdef CONFIG_SECURE_BOOT 39 #define CONFIG_RAMBOOT_SPIFLASH 40 #define CONFIG_SYS_TEXT_BASE 0x11000000 41 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 42 #else 43 #define CONFIG_SPL_SPI_FLASH_MINIMAL 44 #define CONFIG_SPL_FLUSH_IMAGE 45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 46 #define CONFIG_SYS_TEXT_BASE 0x11001000 47 #define CONFIG_SPL_TEXT_BASE 0xD0001000 48 #define CONFIG_SPL_PAD_TO 0x18000 49 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 54 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 56 #define CONFIG_SPL_SPI_BOOT 57 #ifdef CONFIG_SPL_BUILD 58 #define CONFIG_SPL_COMMON_INIT_DDR 59 #endif 60 #endif 61 #endif 62 63 #ifdef CONFIG_NAND 64 #ifdef CONFIG_SECURE_BOOT 65 #define CONFIG_SPL_INIT_MINIMAL 66 #define CONFIG_SPL_NAND_BOOT 67 #define CONFIG_SPL_FLUSH_IMAGE 68 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 69 70 #define CONFIG_SYS_TEXT_BASE 0x00201000 71 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 72 #define CONFIG_SPL_MAX_SIZE 8192 73 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 74 #define CONFIG_SPL_RELOC_STACK 0x00100000 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 76 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 77 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 78 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 80 #else 81 #ifdef CONFIG_TPL_BUILD 82 #define CONFIG_SPL_NAND_BOOT 83 #define CONFIG_SPL_FLUSH_IMAGE 84 #define CONFIG_SPL_NAND_INIT 85 #define CONFIG_SPL_COMMON_INIT_DDR 86 #define CONFIG_SPL_MAX_SIZE (128 << 10) 87 #define CONFIG_SPL_TEXT_BASE 0xD0001000 88 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 89 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 90 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 91 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 92 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 93 #elif defined(CONFIG_SPL_BUILD) 94 #define CONFIG_SPL_INIT_MINIMAL 95 #define CONFIG_SPL_NAND_MINIMAL 96 #define CONFIG_SPL_FLUSH_IMAGE 97 #define CONFIG_SPL_TEXT_BASE 0xff800000 98 #define CONFIG_SPL_MAX_SIZE 8192 99 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 100 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 101 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 102 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 103 #endif 104 #define CONFIG_SPL_PAD_TO 0x20000 105 #define CONFIG_TPL_PAD_TO 0x20000 106 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 107 #define CONFIG_SYS_TEXT_BASE 0x11001000 108 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 109 #endif 110 #endif 111 112 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 113 #define CONFIG_RAMBOOT_NAND 114 #define CONFIG_SYS_TEXT_BASE 0x11000000 115 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 116 #endif 117 118 #ifndef CONFIG_SYS_TEXT_BASE 119 #define CONFIG_SYS_TEXT_BASE 0xeff40000 120 #endif 121 122 #ifndef CONFIG_RESET_VECTOR_ADDRESS 123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 124 #endif 125 126 #ifdef CONFIG_SPL_BUILD 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 128 #else 129 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 130 #endif 131 132 /* High Level Configuration Options */ 133 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 134 135 #if defined(CONFIG_PCI) 136 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 137 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 138 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 139 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 140 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 141 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 142 143 /* 144 * PCI Windows 145 * Memory space is mapped 1-1, but I/O space must start from 0. 146 */ 147 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 148 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 149 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 150 #ifdef CONFIG_PHYS_64BIT 151 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 152 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 153 #else 154 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 155 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 156 #endif 157 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 158 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 159 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 160 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 161 #ifdef CONFIG_PHYS_64BIT 162 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 163 #else 164 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 165 #endif 166 167 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 168 #if defined(CONFIG_TARGET_P1010RDB_PA) 169 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 170 #elif defined(CONFIG_TARGET_P1010RDB_PB) 171 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 172 #endif 173 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 174 #ifdef CONFIG_PHYS_64BIT 175 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 176 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 177 #else 178 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 179 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 180 #endif 181 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 182 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 183 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 184 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 185 #ifdef CONFIG_PHYS_64BIT 186 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 187 #else 188 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 189 #endif 190 191 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 192 #endif 193 194 #define CONFIG_TSEC_ENET 195 #define CONFIG_ENV_OVERWRITE 196 197 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 198 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 199 200 #define CONFIG_MISC_INIT_R 201 #define CONFIG_HWCONFIG 202 /* 203 * These can be toggled for performance analysis, otherwise use default. 204 */ 205 #define CONFIG_L2_CACHE /* toggle L2 cache */ 206 #define CONFIG_BTB /* toggle branch predition */ 207 208 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 209 210 #define CONFIG_ENABLE_36BIT_PHYS 211 212 #ifdef CONFIG_PHYS_64BIT 213 #define CONFIG_ADDR_MAP 1 214 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 215 #endif 216 217 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 218 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 219 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 220 221 /* DDR Setup */ 222 #define CONFIG_SYS_DDR_RAW_TIMING 223 #define CONFIG_DDR_SPD 224 #define CONFIG_SYS_SPD_BUS_NUM 1 225 #define SPD_EEPROM_ADDRESS 0x52 226 227 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 228 229 #ifndef __ASSEMBLY__ 230 extern unsigned long get_sdram_size(void); 231 #endif 232 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 233 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 234 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 235 236 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 237 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 238 239 /* DDR3 Controller Settings */ 240 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 241 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 242 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 243 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 244 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 245 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 246 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 247 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 248 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 249 #define CONFIG_SYS_DDR_RCW_1 0x00000000 250 #define CONFIG_SYS_DDR_RCW_2 0x00000000 251 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 252 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 253 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 254 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 255 256 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 257 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 258 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 259 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 260 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 261 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 262 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 263 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 264 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 265 266 /* settings for DDR3 at 667MT/s */ 267 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 268 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 269 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 270 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 271 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 272 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 273 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 274 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 275 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 276 277 #define CONFIG_SYS_CCSRBAR 0xffe00000 278 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 279 280 /* Don't relocate CCSRBAR while in NAND_SPL */ 281 #ifdef CONFIG_SPL_BUILD 282 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 283 #endif 284 285 /* 286 * Memory map 287 * 288 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 289 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 290 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 291 * 292 * Localbus non-cacheable 293 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 294 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 295 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 296 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 297 */ 298 299 /* 300 * IFC Definitions 301 */ 302 /* NOR Flash on IFC */ 303 304 #define CONFIG_SYS_FLASH_BASE 0xee000000 305 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 306 307 #ifdef CONFIG_PHYS_64BIT 308 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 309 #else 310 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 311 #endif 312 313 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 314 CSPR_PORT_SIZE_16 | \ 315 CSPR_MSEL_NOR | \ 316 CSPR_V) 317 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 318 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 319 /* NOR Flash Timing Params */ 320 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 321 FTIM0_NOR_TEADC(0x5) | \ 322 FTIM0_NOR_TEAHC(0x5) 323 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 324 FTIM1_NOR_TRAD_NOR(0x0f) 325 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 326 FTIM2_NOR_TCH(0x4) | \ 327 FTIM2_NOR_TWP(0x1c) 328 #define CONFIG_SYS_NOR_FTIM3 0x0 329 330 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 331 #define CONFIG_SYS_FLASH_QUIET_TEST 332 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 333 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 334 335 #undef CONFIG_SYS_FLASH_CHECKSUM 336 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 337 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 338 339 /* CFI for NOR Flash */ 340 #define CONFIG_FLASH_CFI_DRIVER 341 #define CONFIG_SYS_FLASH_CFI 342 #define CONFIG_SYS_FLASH_EMPTY_INFO 343 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 344 345 /* NAND Flash on IFC */ 346 #define CONFIG_SYS_NAND_BASE 0xff800000 347 #ifdef CONFIG_PHYS_64BIT 348 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 349 #else 350 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 351 #endif 352 353 #define CONFIG_MTD_DEVICE 354 #define CONFIG_MTD_PARTITION 355 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 356 #define MTDPARTS_DEFAULT \ 357 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 358 359 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 360 | CSPR_PORT_SIZE_8 \ 361 | CSPR_MSEL_NAND \ 362 | CSPR_V) 363 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 364 365 #if defined(CONFIG_TARGET_P1010RDB_PA) 366 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 367 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 368 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 369 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 370 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 371 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 372 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 373 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 374 375 #elif defined(CONFIG_TARGET_P1010RDB_PB) 376 #define CONFIG_SYS_NAND_ONFI_DETECTION 377 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 378 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 379 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 380 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 381 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 382 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 383 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 384 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 385 #endif 386 387 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 388 #define CONFIG_SYS_MAX_NAND_DEVICE 1 389 390 #if defined(CONFIG_TARGET_P1010RDB_PA) 391 /* NAND Flash Timing Params */ 392 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 393 FTIM0_NAND_TWP(0x0C) | \ 394 FTIM0_NAND_TWCHT(0x04) | \ 395 FTIM0_NAND_TWH(0x05) 396 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 397 FTIM1_NAND_TWBE(0x1d) | \ 398 FTIM1_NAND_TRR(0x07) | \ 399 FTIM1_NAND_TRP(0x0c) 400 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 401 FTIM2_NAND_TREH(0x05) | \ 402 FTIM2_NAND_TWHRE(0x0f) 403 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 404 405 #elif defined(CONFIG_TARGET_P1010RDB_PB) 406 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 407 /* ONFI NAND Flash mode0 Timing Params */ 408 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 409 FTIM0_NAND_TWP(0x18) | \ 410 FTIM0_NAND_TWCHT(0x07) | \ 411 FTIM0_NAND_TWH(0x0a)) 412 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 413 FTIM1_NAND_TWBE(0x39) | \ 414 FTIM1_NAND_TRR(0x0e) | \ 415 FTIM1_NAND_TRP(0x18)) 416 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 417 FTIM2_NAND_TREH(0x0a) | \ 418 FTIM2_NAND_TWHRE(0x1e)) 419 #define CONFIG_SYS_NAND_FTIM3 0x0 420 #endif 421 422 #define CONFIG_SYS_NAND_DDR_LAW 11 423 424 /* Set up IFC registers for boot location NOR/NAND */ 425 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 426 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 427 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 428 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 429 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 430 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 431 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 432 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 433 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 434 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 435 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 436 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 437 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 438 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 439 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 440 #else 441 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 442 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 443 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 444 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 445 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 446 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 447 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 448 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 449 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 450 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 451 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 452 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 453 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 454 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 455 #endif 456 457 /* CPLD on IFC */ 458 #define CONFIG_SYS_CPLD_BASE 0xffb00000 459 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 462 #else 463 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 464 #endif 465 466 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 467 | CSPR_PORT_SIZE_8 \ 468 | CSPR_MSEL_GPCM \ 469 | CSPR_V) 470 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 471 #define CONFIG_SYS_CSOR3 0x0 472 /* CPLD Timing parameters for IFC CS3 */ 473 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 474 FTIM0_GPCM_TEADC(0x0e) | \ 475 FTIM0_GPCM_TEAHC(0x0e)) 476 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 477 FTIM1_GPCM_TRAD(0x1f)) 478 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 479 FTIM2_GPCM_TCH(0x8) | \ 480 FTIM2_GPCM_TWP(0x1f)) 481 #define CONFIG_SYS_CS3_FTIM3 0x0 482 483 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 484 defined(CONFIG_RAMBOOT_NAND) 485 #define CONFIG_SYS_RAMBOOT 486 #define CONFIG_SYS_EXTRA_ENV_RELOC 487 #else 488 #undef CONFIG_SYS_RAMBOOT 489 #endif 490 491 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 492 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 493 #define CONFIG_A003399_NOR_WORKAROUND 494 #endif 495 #endif 496 497 #define CONFIG_BOARD_EARLY_INIT_R 498 499 #define CONFIG_SYS_INIT_RAM_LOCK 500 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 501 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 502 503 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 504 - GENERATED_GBL_DATA_SIZE) 505 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 506 507 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 508 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 509 510 /* 511 * Config the L2 Cache as L2 SRAM 512 */ 513 #if defined(CONFIG_SPL_BUILD) 514 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 515 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 516 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 517 #define CONFIG_SYS_L2_SIZE (256 << 10) 518 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 519 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 520 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 521 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 522 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 523 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 524 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 525 #elif defined(CONFIG_NAND) 526 #ifdef CONFIG_TPL_BUILD 527 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 528 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 529 #define CONFIG_SYS_L2_SIZE (256 << 10) 530 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 531 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 532 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 533 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 534 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 535 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 536 #else 537 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 538 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 539 #define CONFIG_SYS_L2_SIZE (256 << 10) 540 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 541 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 542 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 543 #endif 544 #endif 545 #endif 546 547 /* Serial Port */ 548 #define CONFIG_CONS_INDEX 1 549 #undef CONFIG_SERIAL_SOFTWARE_FIFO 550 #define CONFIG_SYS_NS16550_SERIAL 551 #define CONFIG_SYS_NS16550_REG_SIZE 1 552 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 553 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 554 #define CONFIG_NS16550_MIN_FUNCTIONS 555 #endif 556 557 #define CONFIG_SYS_BAUDRATE_TABLE \ 558 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 559 560 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 561 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 562 563 /* I2C */ 564 #define CONFIG_SYS_I2C 565 #define CONFIG_SYS_I2C_FSL 566 #define CONFIG_SYS_FSL_I2C_SPEED 400000 567 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 568 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 569 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 570 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 571 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 572 #define I2C_PCA9557_ADDR1 0x18 573 #define I2C_PCA9557_ADDR2 0x19 574 #define I2C_PCA9557_BUS_NUM 0 575 576 /* I2C EEPROM */ 577 #if defined(CONFIG_TARGET_P1010RDB_PB) 578 #define CONFIG_ID_EEPROM 579 #ifdef CONFIG_ID_EEPROM 580 #define CONFIG_SYS_I2C_EEPROM_NXID 581 #endif 582 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 583 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 584 #define CONFIG_SYS_EEPROM_BUS_NUM 0 585 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 586 #endif 587 /* enable read and write access to EEPROM */ 588 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 589 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 590 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 591 592 /* RTC */ 593 #define CONFIG_RTC_PT7C4338 594 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 595 596 /* 597 * SPI interface will not be available in case of NAND boot SPI CS0 will be 598 * used for SLIC 599 */ 600 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 601 /* eSPI - Enhanced SPI */ 602 #define CONFIG_SF_DEFAULT_SPEED 10000000 603 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 604 #endif 605 606 #if defined(CONFIG_TSEC_ENET) 607 #define CONFIG_MII /* MII PHY management */ 608 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 609 #define CONFIG_TSEC1 1 610 #define CONFIG_TSEC1_NAME "eTSEC1" 611 #define CONFIG_TSEC2 1 612 #define CONFIG_TSEC2_NAME "eTSEC2" 613 #define CONFIG_TSEC3 1 614 #define CONFIG_TSEC3_NAME "eTSEC3" 615 616 #define TSEC1_PHY_ADDR 1 617 #define TSEC2_PHY_ADDR 0 618 #define TSEC3_PHY_ADDR 2 619 620 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 621 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 622 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 623 624 #define TSEC1_PHYIDX 0 625 #define TSEC2_PHYIDX 0 626 #define TSEC3_PHYIDX 0 627 628 #define CONFIG_ETHPRIME "eTSEC1" 629 630 /* TBI PHY configuration for SGMII mode */ 631 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 632 TBICR_PHY_RESET \ 633 | TBICR_ANEG_ENABLE \ 634 | TBICR_FULL_DUPLEX \ 635 | TBICR_SPEED1_SET \ 636 ) 637 638 #endif /* CONFIG_TSEC_ENET */ 639 640 /* SATA */ 641 #define CONFIG_FSL_SATA 642 #define CONFIG_FSL_SATA_V2 643 #define CONFIG_LIBATA 644 645 #ifdef CONFIG_FSL_SATA 646 #define CONFIG_SYS_SATA_MAX_DEVICE 2 647 #define CONFIG_SATA1 648 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 649 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 650 #define CONFIG_SATA2 651 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 652 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 653 654 #define CONFIG_LBA48 655 #endif /* #ifdef CONFIG_FSL_SATA */ 656 657 #ifdef CONFIG_MMC 658 #define CONFIG_FSL_ESDHC 659 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 660 #endif 661 662 #define CONFIG_HAS_FSL_DR_USB 663 664 #if defined(CONFIG_HAS_FSL_DR_USB) 665 #ifdef CONFIG_USB_EHCI_HCD 666 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 667 #define CONFIG_USB_EHCI_FSL 668 #endif 669 #endif 670 671 /* 672 * Environment 673 */ 674 #if defined(CONFIG_SDCARD) 675 #define CONFIG_FSL_FIXED_MMC_LOCATION 676 #define CONFIG_SYS_MMC_ENV_DEV 0 677 #define CONFIG_ENV_SIZE 0x2000 678 #elif defined(CONFIG_SPIFLASH) 679 #define CONFIG_ENV_SPI_BUS 0 680 #define CONFIG_ENV_SPI_CS 0 681 #define CONFIG_ENV_SPI_MAX_HZ 10000000 682 #define CONFIG_ENV_SPI_MODE 0 683 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 684 #define CONFIG_ENV_SECT_SIZE 0x10000 685 #define CONFIG_ENV_SIZE 0x2000 686 #elif defined(CONFIG_NAND) 687 #ifdef CONFIG_TPL_BUILD 688 #define CONFIG_ENV_SIZE 0x2000 689 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 690 #else 691 #if defined(CONFIG_TARGET_P1010RDB_PA) 692 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 693 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 694 #elif defined(CONFIG_TARGET_P1010RDB_PB) 695 #define CONFIG_ENV_SIZE (16 * 1024) 696 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 697 #endif 698 #endif 699 #define CONFIG_ENV_OFFSET (1024 * 1024) 700 #elif defined(CONFIG_SYS_RAMBOOT) 701 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 702 #define CONFIG_ENV_SIZE 0x2000 703 #else 704 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 705 #define CONFIG_ENV_SIZE 0x2000 706 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 707 #endif 708 709 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 710 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 711 712 #undef CONFIG_WATCHDOG /* watchdog disabled */ 713 714 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ 715 || defined(CONFIG_FSL_SATA) 716 #endif 717 718 /* 719 * Miscellaneous configurable options 720 */ 721 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 722 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 723 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 724 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 725 726 /* 727 * For booting Linux, the board info and command line data 728 * have to be in the first 64 MB of memory, since this is 729 * the maximum mapped by the Linux kernel during initialization. 730 */ 731 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 732 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 733 734 #if defined(CONFIG_CMD_KGDB) 735 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 736 #endif 737 738 /* 739 * Environment Configuration 740 */ 741 742 #if defined(CONFIG_TSEC_ENET) 743 #define CONFIG_HAS_ETH0 744 #define CONFIG_HAS_ETH1 745 #define CONFIG_HAS_ETH2 746 #endif 747 748 #define CONFIG_ROOTPATH "/opt/nfsroot" 749 #define CONFIG_BOOTFILE "uImage" 750 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 751 752 /* default location for tftp and bootm */ 753 #define CONFIG_LOADADDR 1000000 754 755 #define CONFIG_EXTRA_ENV_SETTINGS \ 756 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 757 "netdev=eth0\0" \ 758 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 759 "loadaddr=1000000\0" \ 760 "consoledev=ttyS0\0" \ 761 "ramdiskaddr=2000000\0" \ 762 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 763 "fdtaddr=1e00000\0" \ 764 "fdtfile=p1010rdb.dtb\0" \ 765 "bdev=sda1\0" \ 766 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 767 "othbootargs=ramdisk_size=600000\0" \ 768 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 769 "console=$consoledev,$baudrate $othbootargs; " \ 770 "usb start;" \ 771 "fatload usb 0:2 $loadaddr $bootfile;" \ 772 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 773 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 774 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 775 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 776 "console=$consoledev,$baudrate $othbootargs; " \ 777 "usb start;" \ 778 "ext2load usb 0:4 $loadaddr $bootfile;" \ 779 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 780 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 781 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 782 CONFIG_BOOTMODE 783 784 #if defined(CONFIG_TARGET_P1010RDB_PA) 785 #define CONFIG_BOOTMODE \ 786 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 787 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 788 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 789 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 790 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 791 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 792 793 #elif defined(CONFIG_TARGET_P1010RDB_PB) 794 #define CONFIG_BOOTMODE \ 795 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 796 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 797 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 798 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 799 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 800 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 801 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 802 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 803 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 804 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 805 #endif 806 807 #define CONFIG_RAMBOOTCOMMAND \ 808 "setenv bootargs root=/dev/ram rw " \ 809 "console=$consoledev,$baudrate $othbootargs; " \ 810 "tftp $ramdiskaddr $ramdiskfile;" \ 811 "tftp $loadaddr $bootfile;" \ 812 "tftp $fdtaddr $fdtfile;" \ 813 "bootm $loadaddr $ramdiskaddr $fdtaddr" 814 815 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 816 817 #include <asm/fsl_secure_boot.h> 818 819 #endif /* __CONFIG_H */ 820