1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_36BIT 15 #define CONFIG_PHYS_64BIT 16 #endif 17 18 #define CONFIG_P1010 19 #define CONFIG_E500 /* BOOKE e500 family */ 20 #include <asm/config_mpc85xx.h> 21 #define CONFIG_NAND_FSL_IFC 22 23 #ifdef CONFIG_SDCARD 24 #define CONFIG_RAMBOOT_SDCARD 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 27 #endif 28 29 #ifdef CONFIG_SPIFLASH 30 #define CONFIG_RAMBOOT_SPIFLASH 31 #define CONFIG_SYS_TEXT_BASE 0x11000000 32 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 33 #endif 34 35 #ifdef CONFIG_NAND 36 #define CONFIG_SPL 37 #define CONFIG_SPL_INIT_MINIMAL 38 #define CONFIG_SPL_SERIAL_SUPPORT 39 #define CONFIG_SPL_NAND_SUPPORT 40 #define CONFIG_SPL_NAND_MINIMAL 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 46 #define CONFIG_SPL_MAX_SIZE 8192 47 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 48 #define CONFIG_SPL_RELOC_STACK 0x00100000 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 50 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #endif 55 56 57 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 58 #define CONFIG_RAMBOOT_NAND 59 #define CONFIG_SYS_TEXT_BASE 0x11000000 60 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 61 #endif 62 63 #ifndef CONFIG_SYS_TEXT_BASE 64 #define CONFIG_SYS_TEXT_BASE 0xeff80000 65 #endif 66 67 #ifndef CONFIG_RESET_VECTOR_ADDRESS 68 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 69 #endif 70 71 #ifdef CONFIG_SPL_BUILD 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 73 #else 74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 75 #endif 76 77 /* High Level Configuration Options */ 78 #define CONFIG_BOOKE /* BOOKE */ 79 #define CONFIG_E500 /* BOOKE e500 family */ 80 #define CONFIG_MPC85xx 81 #define CONFIG_FSL_IFC /* Enable IFC Support */ 82 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 83 84 #define CONFIG_PCI /* Enable PCI/PCIE */ 85 #if defined(CONFIG_PCI) 86 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 87 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ 88 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 89 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 90 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 91 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 92 93 #define CONFIG_CMD_NET 94 #define CONFIG_CMD_PCI 95 96 #define CONFIG_E1000 /* E1000 pci Ethernet card*/ 97 98 /* 99 * PCI Windows 100 * Memory space is mapped 1-1, but I/O space must start from 0. 101 */ 102 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 103 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 104 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 105 #ifdef CONFIG_PHYS_64BIT 106 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 107 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 108 #else 109 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 110 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 111 #endif 112 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 113 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 114 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 115 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 118 #else 119 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 120 #endif 121 122 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 123 #if defined(CONFIG_P1010RDB_PA) 124 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 125 #elif defined(CONFIG_P1010RDB_PB) 126 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 127 #endif 128 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 131 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 132 #else 133 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 134 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 135 #endif 136 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 137 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 138 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 139 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 142 #else 143 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 144 #endif 145 146 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 147 148 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 149 #define CONFIG_DOS_PARTITION 150 #endif 151 152 #define CONFIG_FSL_LAW /* Use common FSL init code */ 153 #define CONFIG_TSEC_ENET 154 #define CONFIG_ENV_OVERWRITE 155 156 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 157 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 158 159 #define CONFIG_MISC_INIT_R 160 #define CONFIG_HWCONFIG 161 /* 162 * These can be toggled for performance analysis, otherwise use default. 163 */ 164 #define CONFIG_L2_CACHE /* toggle L2 cache */ 165 #define CONFIG_BTB /* toggle branch predition */ 166 167 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 168 169 #define CONFIG_ENABLE_36BIT_PHYS 170 171 #ifdef CONFIG_PHYS_64BIT 172 #define CONFIG_ADDR_MAP 1 173 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 174 #endif 175 176 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 177 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 178 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 179 180 /* DDR Setup */ 181 #define CONFIG_FSL_DDR3 182 #define CONFIG_SYS_DDR_RAW_TIMING 183 #define CONFIG_DDR_SPD 184 #define CONFIG_SYS_SPD_BUS_NUM 1 185 #define SPD_EEPROM_ADDRESS 0x52 186 187 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 188 189 #ifndef __ASSEMBLY__ 190 extern unsigned long get_sdram_size(void); 191 #endif 192 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 193 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 194 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 195 196 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 197 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 198 199 /* DDR3 Controller Settings */ 200 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 201 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 202 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 203 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 204 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 205 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 206 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 207 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 208 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 209 #define CONFIG_SYS_DDR_RCW_1 0x00000000 210 #define CONFIG_SYS_DDR_RCW_2 0x00000000 211 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 212 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 213 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 214 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 215 216 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 217 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 218 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 219 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 220 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 221 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 222 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 223 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 224 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 225 226 /* settings for DDR3 at 667MT/s */ 227 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 228 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 229 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 230 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 231 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 232 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 233 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 234 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 235 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 236 237 #define CONFIG_SYS_CCSRBAR 0xffe00000 238 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 239 240 /* Don't relocate CCSRBAR while in NAND_SPL */ 241 #ifdef CONFIG_SPL_BUILD 242 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 243 #endif 244 245 /* 246 * Memory map 247 * 248 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 249 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 250 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 251 * 252 * Localbus non-cacheable 253 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 254 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 255 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 256 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 257 */ 258 259 /* 260 * IFC Definitions 261 */ 262 /* NOR Flash on IFC */ 263 #ifdef CONFIG_SPL_BUILD 264 #define CONFIG_SYS_NO_FLASH 265 #endif 266 267 #define CONFIG_SYS_FLASH_BASE 0xee000000 268 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 269 270 #ifdef CONFIG_PHYS_64BIT 271 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 272 #else 273 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 274 #endif 275 276 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 277 CSPR_PORT_SIZE_16 | \ 278 CSPR_MSEL_NOR | \ 279 CSPR_V) 280 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 281 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 282 /* NOR Flash Timing Params */ 283 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 284 FTIM0_NOR_TEADC(0x5) | \ 285 FTIM0_NOR_TEAHC(0x5) 286 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 287 FTIM1_NOR_TRAD_NOR(0x0f) 288 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 289 FTIM2_NOR_TCH(0x4) | \ 290 FTIM2_NOR_TWP(0x1c) 291 #define CONFIG_SYS_NOR_FTIM3 0x0 292 293 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 294 #define CONFIG_SYS_FLASH_QUIET_TEST 295 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 296 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 297 298 #undef CONFIG_SYS_FLASH_CHECKSUM 299 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 300 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 301 302 /* CFI for NOR Flash */ 303 #define CONFIG_FLASH_CFI_DRIVER 304 #define CONFIG_SYS_FLASH_CFI 305 #define CONFIG_SYS_FLASH_EMPTY_INFO 306 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 307 308 /* NAND Flash on IFC */ 309 #define CONFIG_SYS_NAND_BASE 0xff800000 310 #ifdef CONFIG_PHYS_64BIT 311 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 312 #else 313 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 314 #endif 315 316 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 317 | CSPR_PORT_SIZE_8 \ 318 | CSPR_MSEL_NAND \ 319 | CSPR_V) 320 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 321 322 #if defined(CONFIG_P1010RDB_PA) 323 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 324 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 325 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 326 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 327 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 328 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 329 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 330 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 331 332 #elif defined(CONFIG_P1010RDB_PB) 333 #define CONFIG_SYS_NAND_ONFI_DETECTION 334 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 335 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 336 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 337 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 338 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 339 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 340 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 341 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 342 #endif 343 344 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 345 #define CONFIG_SYS_MAX_NAND_DEVICE 1 346 #define CONFIG_MTD_NAND_VERIFY_WRITE 347 #define CONFIG_CMD_NAND 348 349 #if defined(CONFIG_P1010RDB_PA) 350 /* NAND Flash Timing Params */ 351 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 352 FTIM0_NAND_TWP(0x0C) | \ 353 FTIM0_NAND_TWCHT(0x04) | \ 354 FTIM0_NAND_TWH(0x05) 355 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 356 FTIM1_NAND_TWBE(0x1d) | \ 357 FTIM1_NAND_TRR(0x07) | \ 358 FTIM1_NAND_TRP(0x0c) 359 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 360 FTIM2_NAND_TREH(0x05) | \ 361 FTIM2_NAND_TWHRE(0x0f) 362 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 363 364 #elif defined(CONFIG_P1010RDB_PB) 365 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 366 /* ONFI NAND Flash mode0 Timing Params */ 367 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 368 FTIM0_NAND_TWP(0x18) | \ 369 FTIM0_NAND_TWCHT(0x07) | \ 370 FTIM0_NAND_TWH(0x0a)) 371 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 372 FTIM1_NAND_TWBE(0x39) | \ 373 FTIM1_NAND_TRR(0x0e) | \ 374 FTIM1_NAND_TRP(0x18)) 375 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 376 FTIM2_NAND_TREH(0x0a) | \ 377 FTIM2_NAND_TWHRE(0x1e)) 378 #define CONFIG_SYS_NAND_FTIM3 0x0 379 #endif 380 381 #define CONFIG_SYS_NAND_DDR_LAW 11 382 383 /* Set up IFC registers for boot location NOR/NAND */ 384 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 385 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 386 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 387 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 388 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 389 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 390 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 391 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 392 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 393 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 394 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 395 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 396 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 397 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 398 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 399 #else 400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 407 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 408 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 409 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 410 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 411 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 412 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 413 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 414 #endif 415 416 /* CPLD on IFC */ 417 #define CONFIG_SYS_CPLD_BASE 0xffb00000 418 419 #ifdef CONFIG_PHYS_64BIT 420 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 421 #else 422 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 423 #endif 424 425 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 426 | CSPR_PORT_SIZE_8 \ 427 | CSPR_MSEL_GPCM \ 428 | CSPR_V) 429 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 430 #define CONFIG_SYS_CSOR3 0x0 431 /* CPLD Timing parameters for IFC CS3 */ 432 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 433 FTIM0_GPCM_TEADC(0x0e) | \ 434 FTIM0_GPCM_TEAHC(0x0e)) 435 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 436 FTIM1_GPCM_TRAD(0x1f)) 437 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 438 FTIM2_GPCM_TCH(0x0) | \ 439 FTIM2_GPCM_TWP(0x1f)) 440 #define CONFIG_SYS_CS3_FTIM3 0x0 441 442 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 443 #define CONFIG_SYS_RAMBOOT 444 #define CONFIG_SYS_EXTRA_ENV_RELOC 445 #else 446 #undef CONFIG_SYS_RAMBOOT 447 #endif 448 449 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 450 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ 451 && !defined(CONFIG_SECURE_BOOT) 452 #define CONFIG_A003399_NOR_WORKAROUND 453 #endif 454 #endif 455 456 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 457 #define CONFIG_BOARD_EARLY_INIT_R 458 459 #define CONFIG_SYS_INIT_RAM_LOCK 460 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 461 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 462 463 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 464 - GENERATED_GBL_DATA_SIZE) 465 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 466 467 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ 468 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 469 470 /* Serial Port */ 471 #define CONFIG_CONS_INDEX 1 472 #undef CONFIG_SERIAL_SOFTWARE_FIFO 473 #define CONFIG_SYS_NS16550 474 #define CONFIG_SYS_NS16550_SERIAL 475 #define CONFIG_SYS_NS16550_REG_SIZE 1 476 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 477 #ifdef CONFIG_SPL_BUILD 478 #define CONFIG_NS16550_MIN_FUNCTIONS 479 #endif 480 481 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 482 483 #define CONFIG_SYS_BAUDRATE_TABLE \ 484 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 485 486 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 487 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 488 489 /* Use the HUSH parser */ 490 #define CONFIG_SYS_HUSH_PARSER 491 492 /* 493 * Pass open firmware flat tree 494 */ 495 #define CONFIG_OF_LIBFDT 496 #define CONFIG_OF_BOARD_SETUP 497 #define CONFIG_OF_STDOUT_VIA_ALIAS 498 499 /* new uImage format support */ 500 #define CONFIG_FIT 501 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 502 503 /* I2C */ 504 #define CONFIG_SYS_I2C 505 #define CONFIG_SYS_I2C_FSL 506 #define CONFIG_SYS_FSL_I2C_SPEED 400000 507 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 508 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 509 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 510 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 511 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 512 #define I2C_PCA9557_ADDR1 0x18 513 #define I2C_PCA9557_ADDR2 0x19 514 #define I2C_PCA9557_BUS_NUM 0 515 516 /* I2C EEPROM */ 517 #if defined(CONFIG_P1010RDB_PB) 518 #define CONFIG_ID_EEPROM 519 #ifdef CONFIG_ID_EEPROM 520 #define CONFIG_SYS_I2C_EEPROM_NXID 521 #endif 522 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 523 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 524 #define CONFIG_SYS_EEPROM_BUS_NUM 0 525 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 526 #endif 527 /* enable read and write access to EEPROM */ 528 #define CONFIG_CMD_EEPROM 529 #define CONFIG_SYS_I2C_MULTI_EEPROMS 530 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 531 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 532 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 533 534 /* RTC */ 535 #define CONFIG_RTC_PT7C4338 536 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 537 538 #define CONFIG_CMD_I2C 539 540 /* 541 * SPI interface will not be available in case of NAND boot SPI CS0 will be 542 * used for SLIC 543 */ 544 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 545 /* eSPI - Enhanced SPI */ 546 #define CONFIG_FSL_ESPI 547 #define CONFIG_SPI_FLASH 548 #define CONFIG_SPI_FLASH_SPANSION 549 #define CONFIG_CMD_SF 550 #define CONFIG_SF_DEFAULT_SPEED 10000000 551 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 552 #endif 553 554 #if defined(CONFIG_TSEC_ENET) 555 #define CONFIG_MII /* MII PHY management */ 556 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 557 #define CONFIG_TSEC1 1 558 #define CONFIG_TSEC1_NAME "eTSEC1" 559 #define CONFIG_TSEC2 1 560 #define CONFIG_TSEC2_NAME "eTSEC2" 561 #define CONFIG_TSEC3 1 562 #define CONFIG_TSEC3_NAME "eTSEC3" 563 564 #define TSEC1_PHY_ADDR 1 565 #define TSEC2_PHY_ADDR 0 566 #define TSEC3_PHY_ADDR 2 567 568 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 569 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 570 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 571 572 #define TSEC1_PHYIDX 0 573 #define TSEC2_PHYIDX 0 574 #define TSEC3_PHYIDX 0 575 576 #define CONFIG_ETHPRIME "eTSEC1" 577 578 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 579 580 /* TBI PHY configuration for SGMII mode */ 581 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 582 TBICR_PHY_RESET \ 583 | TBICR_ANEG_ENABLE \ 584 | TBICR_FULL_DUPLEX \ 585 | TBICR_SPEED1_SET \ 586 ) 587 588 #endif /* CONFIG_TSEC_ENET */ 589 590 591 /* SATA */ 592 #define CONFIG_FSL_SATA 593 #define CONFIG_FSL_SATA_V2 594 #define CONFIG_LIBATA 595 596 #ifdef CONFIG_FSL_SATA 597 #define CONFIG_SYS_SATA_MAX_DEVICE 2 598 #define CONFIG_SATA1 599 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 600 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 601 #define CONFIG_SATA2 602 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 603 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 604 605 #define CONFIG_CMD_SATA 606 #define CONFIG_LBA48 607 #endif /* #ifdef CONFIG_FSL_SATA */ 608 609 #define CONFIG_MMC 610 #ifdef CONFIG_MMC 611 #define CONFIG_CMD_MMC 612 #define CONFIG_DOS_PARTITION 613 #define CONFIG_FSL_ESDHC 614 #define CONFIG_GENERIC_MMC 615 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 616 #endif 617 618 #define CONFIG_HAS_FSL_DR_USB 619 620 #if defined(CONFIG_HAS_FSL_DR_USB) 621 #define CONFIG_USB_EHCI 622 623 #ifdef CONFIG_USB_EHCI 624 #define CONFIG_CMD_USB 625 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 626 #define CONFIG_USB_EHCI_FSL 627 #define CONFIG_USB_STORAGE 628 #endif 629 #endif 630 631 /* 632 * Environment 633 */ 634 #if defined(CONFIG_RAMBOOT_SDCARD) 635 #define CONFIG_ENV_IS_IN_MMC 636 #define CONFIG_FSL_FIXED_MMC_LOCATION 637 #define CONFIG_SYS_MMC_ENV_DEV 0 638 #define CONFIG_ENV_SIZE 0x2000 639 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 640 #define CONFIG_ENV_IS_IN_SPI_FLASH 641 #define CONFIG_ENV_SPI_BUS 0 642 #define CONFIG_ENV_SPI_CS 0 643 #define CONFIG_ENV_SPI_MAX_HZ 10000000 644 #define CONFIG_ENV_SPI_MODE 0 645 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 646 #define CONFIG_ENV_SECT_SIZE 0x10000 647 #define CONFIG_ENV_SIZE 0x2000 648 #elif defined(CONFIG_NAND) 649 #define CONFIG_ENV_IS_IN_NAND 650 #if defined(CONFIG_P1010RDB_PA) 651 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 652 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 653 #elif defined(CONFIG_P1010RDB_PB) 654 #define CONFIG_ENV_SIZE (16 * 1024) 655 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 656 #endif 657 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 658 #elif defined(CONFIG_SYS_RAMBOOT) 659 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 660 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 661 #define CONFIG_ENV_SIZE 0x2000 662 #else 663 #define CONFIG_ENV_IS_IN_FLASH 664 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 665 #define CONFIG_ENV_ADDR 0xfff80000 666 #else 667 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 668 #endif 669 #define CONFIG_ENV_SIZE 0x2000 670 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 671 #endif 672 673 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 674 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 675 676 /* 677 * Command line configuration. 678 */ 679 #include <config_cmd_default.h> 680 681 #define CONFIG_CMD_DATE 682 #define CONFIG_CMD_ERRATA 683 #define CONFIG_CMD_ELF 684 #define CONFIG_CMD_IRQ 685 #define CONFIG_CMD_MII 686 #define CONFIG_CMD_PING 687 #define CONFIG_CMD_SETEXPR 688 #define CONFIG_CMD_REGINFO 689 690 #undef CONFIG_WATCHDOG /* watchdog disabled */ 691 692 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 693 || defined(CONFIG_FSL_SATA) 694 #define CONFIG_CMD_EXT2 695 #define CONFIG_CMD_FAT 696 #define CONFIG_DOS_PARTITION 697 #endif 698 699 /* 700 * Miscellaneous configurable options 701 */ 702 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 703 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 704 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 705 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 706 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 707 708 #if defined(CONFIG_CMD_KGDB) 709 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 710 #else 711 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 712 #endif 713 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 714 /* Print Buffer Size */ 715 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 716 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 717 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ 718 719 /* 720 * Internal Definitions 721 * 722 * Boot Flags 723 */ 724 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 725 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 726 727 /* 728 * For booting Linux, the board info and command line data 729 * have to be in the first 64 MB of memory, since this is 730 * the maximum mapped by the Linux kernel during initialization. 731 */ 732 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 733 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 734 735 #if defined(CONFIG_CMD_KGDB) 736 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 737 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 738 #endif 739 740 /* 741 * Environment Configuration 742 */ 743 744 #if defined(CONFIG_TSEC_ENET) 745 #define CONFIG_HAS_ETH0 746 #define CONFIG_HAS_ETH1 747 #define CONFIG_HAS_ETH2 748 #endif 749 750 #define CONFIG_ROOTPATH "/opt/nfsroot" 751 #define CONFIG_BOOTFILE "uImage" 752 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 753 754 /* default location for tftp and bootm */ 755 #define CONFIG_LOADADDR 1000000 756 757 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 758 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 759 760 #define CONFIG_BAUDRATE 115200 761 762 #define CONFIG_EXTRA_ENV_SETTINGS \ 763 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 764 "netdev=eth0\0" \ 765 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 766 "loadaddr=1000000\0" \ 767 "consoledev=ttyS0\0" \ 768 "ramdiskaddr=2000000\0" \ 769 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 770 "fdtaddr=c00000\0" \ 771 "fdtfile=p1010rdb.dtb\0" \ 772 "bdev=sda1\0" \ 773 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 774 "othbootargs=ramdisk_size=600000\0" \ 775 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 776 "console=$consoledev,$baudrate $othbootargs; " \ 777 "usb start;" \ 778 "fatload usb 0:2 $loadaddr $bootfile;" \ 779 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 780 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 781 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 782 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 783 "console=$consoledev,$baudrate $othbootargs; " \ 784 "usb start;" \ 785 "ext2load usb 0:4 $loadaddr $bootfile;" \ 786 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 787 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 788 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 789 CONFIG_BOOTMODE 790 791 #if defined(CONFIG_P1010RDB_PA) 792 #define CONFIG_BOOTMODE \ 793 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 794 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 795 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 796 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 797 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 798 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 799 800 #elif defined(CONFIG_P1010RDB_PB) 801 #define CONFIG_BOOTMODE \ 802 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 803 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 804 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 805 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 806 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 807 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 808 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 809 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 810 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 811 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 812 #endif 813 814 #define CONFIG_RAMBOOTCOMMAND \ 815 "setenv bootargs root=/dev/ram rw " \ 816 "console=$consoledev,$baudrate $othbootargs; " \ 817 "tftp $ramdiskaddr $ramdiskfile;" \ 818 "tftp $loadaddr $bootfile;" \ 819 "tftp $fdtaddr $fdtfile;" \ 820 "bootm $loadaddr $ramdiskaddr $fdtaddr" 821 822 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 823 824 #include <asm/fsl_secure_boot.h> 825 826 #endif /* __CONFIG_H */ 827