1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_MMC_MINIMAL 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_FSL_LAW /* Use common FSL init code */ 26 #define CONFIG_SYS_TEXT_BASE 0x11001000 27 #define CONFIG_SPL_TEXT_BASE 0xD0001000 28 #define CONFIG_SPL_PAD_TO 0x18000 29 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 30 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 31 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 32 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 33 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 34 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 35 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 36 #define CONFIG_SPL_MMC_BOOT 37 #ifdef CONFIG_SPL_BUILD 38 #define CONFIG_SPL_COMMON_INIT_DDR 39 #endif 40 #endif 41 42 #ifdef CONFIG_SPIFLASH 43 #ifdef CONFIG_SECURE_BOOT 44 #define CONFIG_RAMBOOT_SPIFLASH 45 #define CONFIG_SYS_TEXT_BASE 0x11000000 46 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 47 #else 48 #define CONFIG_SPL_SPI_FLASH_MINIMAL 49 #define CONFIG_SPL_FLUSH_IMAGE 50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 51 #define CONFIG_FSL_LAW /* Use common FSL init code */ 52 #define CONFIG_SYS_TEXT_BASE 0x11001000 53 #define CONFIG_SPL_TEXT_BASE 0xD0001000 54 #define CONFIG_SPL_PAD_TO 0x18000 55 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 62 #define CONFIG_SPL_SPI_BOOT 63 #ifdef CONFIG_SPL_BUILD 64 #define CONFIG_SPL_COMMON_INIT_DDR 65 #endif 66 #endif 67 #endif 68 69 #ifdef CONFIG_NAND 70 #ifdef CONFIG_SECURE_BOOT 71 #define CONFIG_SPL_INIT_MINIMAL 72 #define CONFIG_SPL_NAND_BOOT 73 #define CONFIG_SPL_FLUSH_IMAGE 74 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 75 76 #define CONFIG_SYS_TEXT_BASE 0x00201000 77 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 78 #define CONFIG_SPL_MAX_SIZE 8192 79 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 80 #define CONFIG_SPL_RELOC_STACK 0x00100000 81 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 82 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 83 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 84 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 86 #else 87 #ifdef CONFIG_TPL_BUILD 88 #define CONFIG_SPL_NAND_BOOT 89 #define CONFIG_SPL_FLUSH_IMAGE 90 #define CONFIG_SPL_NAND_INIT 91 #define CONFIG_SPL_COMMON_INIT_DDR 92 #define CONFIG_SPL_MAX_SIZE (128 << 10) 93 #define CONFIG_SPL_TEXT_BASE 0xD0001000 94 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 95 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 96 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 97 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 98 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 99 #elif defined(CONFIG_SPL_BUILD) 100 #define CONFIG_SPL_INIT_MINIMAL 101 #define CONFIG_SPL_NAND_MINIMAL 102 #define CONFIG_SPL_FLUSH_IMAGE 103 #define CONFIG_SPL_TEXT_BASE 0xff800000 104 #define CONFIG_SPL_MAX_SIZE 8192 105 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 106 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 107 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 108 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 109 #endif 110 #define CONFIG_SPL_PAD_TO 0x20000 111 #define CONFIG_TPL_PAD_TO 0x20000 112 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 113 #define CONFIG_SYS_TEXT_BASE 0x11001000 114 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 115 #endif 116 #endif 117 118 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 119 #define CONFIG_RAMBOOT_NAND 120 #define CONFIG_SYS_TEXT_BASE 0x11000000 121 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 122 #endif 123 124 #ifndef CONFIG_SYS_TEXT_BASE 125 #define CONFIG_SYS_TEXT_BASE 0xeff40000 126 #endif 127 128 #ifndef CONFIG_RESET_VECTOR_ADDRESS 129 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 130 #endif 131 132 #ifdef CONFIG_SPL_BUILD 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 134 #else 135 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 136 #endif 137 138 /* High Level Configuration Options */ 139 #define CONFIG_BOOKE /* BOOKE */ 140 #define CONFIG_E500 /* BOOKE e500 family */ 141 #define CONFIG_FSL_IFC /* Enable IFC Support */ 142 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 143 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 144 145 #define CONFIG_PCI /* Enable PCI/PCIE */ 146 #if defined(CONFIG_PCI) 147 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 148 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 149 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 150 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 151 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 152 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 153 154 #define CONFIG_CMD_PCI 155 156 /* 157 * PCI Windows 158 * Memory space is mapped 1-1, but I/O space must start from 0. 159 */ 160 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 161 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 162 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 163 #ifdef CONFIG_PHYS_64BIT 164 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 165 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 166 #else 167 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 168 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 169 #endif 170 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 171 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 172 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 173 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 174 #ifdef CONFIG_PHYS_64BIT 175 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 176 #else 177 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 178 #endif 179 180 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 181 #if defined(CONFIG_P1010RDB_PA) 182 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 183 #elif defined(CONFIG_P1010RDB_PB) 184 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 185 #endif 186 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 187 #ifdef CONFIG_PHYS_64BIT 188 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 189 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 190 #else 191 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 192 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 193 #endif 194 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 195 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 196 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 197 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 198 #ifdef CONFIG_PHYS_64BIT 199 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 200 #else 201 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 202 #endif 203 204 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 205 206 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 207 #define CONFIG_DOS_PARTITION 208 #endif 209 210 #define CONFIG_FSL_LAW /* Use common FSL init code */ 211 #define CONFIG_TSEC_ENET 212 #define CONFIG_ENV_OVERWRITE 213 214 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 215 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 216 217 #define CONFIG_MISC_INIT_R 218 #define CONFIG_HWCONFIG 219 /* 220 * These can be toggled for performance analysis, otherwise use default. 221 */ 222 #define CONFIG_L2_CACHE /* toggle L2 cache */ 223 #define CONFIG_BTB /* toggle branch predition */ 224 225 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 226 227 #define CONFIG_ENABLE_36BIT_PHYS 228 229 #ifdef CONFIG_PHYS_64BIT 230 #define CONFIG_ADDR_MAP 1 231 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 232 #endif 233 234 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 235 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 236 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 237 238 /* DDR Setup */ 239 #define CONFIG_SYS_FSL_DDR3 240 #define CONFIG_SYS_DDR_RAW_TIMING 241 #define CONFIG_DDR_SPD 242 #define CONFIG_SYS_SPD_BUS_NUM 1 243 #define SPD_EEPROM_ADDRESS 0x52 244 245 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 246 247 #ifndef __ASSEMBLY__ 248 extern unsigned long get_sdram_size(void); 249 #endif 250 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 251 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 252 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 253 254 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 255 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 256 257 /* DDR3 Controller Settings */ 258 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 259 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 260 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 261 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 262 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 263 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 264 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 265 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 266 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 267 #define CONFIG_SYS_DDR_RCW_1 0x00000000 268 #define CONFIG_SYS_DDR_RCW_2 0x00000000 269 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 270 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 271 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 272 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 273 274 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 275 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 276 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 277 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 278 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 279 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 280 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 281 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 282 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 283 284 /* settings for DDR3 at 667MT/s */ 285 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 286 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 287 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 288 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 289 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 290 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 291 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 292 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 293 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 294 295 #define CONFIG_SYS_CCSRBAR 0xffe00000 296 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 297 298 /* Don't relocate CCSRBAR while in NAND_SPL */ 299 #ifdef CONFIG_SPL_BUILD 300 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 301 #endif 302 303 /* 304 * Memory map 305 * 306 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 307 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 308 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 309 * 310 * Localbus non-cacheable 311 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 312 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 313 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 314 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 315 */ 316 317 /* 318 * IFC Definitions 319 */ 320 /* NOR Flash on IFC */ 321 #ifdef CONFIG_SPL_BUILD 322 #define CONFIG_SYS_NO_FLASH 323 #endif 324 325 #define CONFIG_SYS_FLASH_BASE 0xee000000 326 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 327 328 #ifdef CONFIG_PHYS_64BIT 329 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 330 #else 331 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 332 #endif 333 334 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 335 CSPR_PORT_SIZE_16 | \ 336 CSPR_MSEL_NOR | \ 337 CSPR_V) 338 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 339 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 340 /* NOR Flash Timing Params */ 341 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 342 FTIM0_NOR_TEADC(0x5) | \ 343 FTIM0_NOR_TEAHC(0x5) 344 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 345 FTIM1_NOR_TRAD_NOR(0x0f) 346 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 347 FTIM2_NOR_TCH(0x4) | \ 348 FTIM2_NOR_TWP(0x1c) 349 #define CONFIG_SYS_NOR_FTIM3 0x0 350 351 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 352 #define CONFIG_SYS_FLASH_QUIET_TEST 353 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 354 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 355 356 #undef CONFIG_SYS_FLASH_CHECKSUM 357 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 358 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 359 360 /* CFI for NOR Flash */ 361 #define CONFIG_FLASH_CFI_DRIVER 362 #define CONFIG_SYS_FLASH_CFI 363 #define CONFIG_SYS_FLASH_EMPTY_INFO 364 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 365 366 /* NAND Flash on IFC */ 367 #define CONFIG_SYS_NAND_BASE 0xff800000 368 #ifdef CONFIG_PHYS_64BIT 369 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 370 #else 371 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 372 #endif 373 374 #define CONFIG_MTD_DEVICE 375 #define CONFIG_MTD_PARTITION 376 #define CONFIG_CMD_MTDPARTS 377 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 378 #define MTDPARTS_DEFAULT \ 379 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 380 381 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 382 | CSPR_PORT_SIZE_8 \ 383 | CSPR_MSEL_NAND \ 384 | CSPR_V) 385 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 386 387 #if defined(CONFIG_P1010RDB_PA) 388 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 389 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 390 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 391 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 392 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 393 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 394 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 395 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 396 397 #elif defined(CONFIG_P1010RDB_PB) 398 #define CONFIG_SYS_NAND_ONFI_DETECTION 399 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 400 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 401 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 402 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 403 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 404 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 405 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 406 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 407 #endif 408 409 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 410 #define CONFIG_SYS_MAX_NAND_DEVICE 1 411 #define CONFIG_CMD_NAND 412 413 #if defined(CONFIG_P1010RDB_PA) 414 /* NAND Flash Timing Params */ 415 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 416 FTIM0_NAND_TWP(0x0C) | \ 417 FTIM0_NAND_TWCHT(0x04) | \ 418 FTIM0_NAND_TWH(0x05) 419 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 420 FTIM1_NAND_TWBE(0x1d) | \ 421 FTIM1_NAND_TRR(0x07) | \ 422 FTIM1_NAND_TRP(0x0c) 423 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 424 FTIM2_NAND_TREH(0x05) | \ 425 FTIM2_NAND_TWHRE(0x0f) 426 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 427 428 #elif defined(CONFIG_P1010RDB_PB) 429 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 430 /* ONFI NAND Flash mode0 Timing Params */ 431 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 432 FTIM0_NAND_TWP(0x18) | \ 433 FTIM0_NAND_TWCHT(0x07) | \ 434 FTIM0_NAND_TWH(0x0a)) 435 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 436 FTIM1_NAND_TWBE(0x39) | \ 437 FTIM1_NAND_TRR(0x0e) | \ 438 FTIM1_NAND_TRP(0x18)) 439 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 440 FTIM2_NAND_TREH(0x0a) | \ 441 FTIM2_NAND_TWHRE(0x1e)) 442 #define CONFIG_SYS_NAND_FTIM3 0x0 443 #endif 444 445 #define CONFIG_SYS_NAND_DDR_LAW 11 446 447 /* Set up IFC registers for boot location NOR/NAND */ 448 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 449 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 450 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 451 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 452 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 453 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 454 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 455 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 456 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 457 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 458 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 459 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 460 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 461 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 462 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 463 #else 464 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 465 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 466 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 467 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 468 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 469 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 470 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 471 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 472 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 473 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 474 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 475 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 476 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 477 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 478 #endif 479 480 /* CPLD on IFC */ 481 #define CONFIG_SYS_CPLD_BASE 0xffb00000 482 483 #ifdef CONFIG_PHYS_64BIT 484 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 485 #else 486 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 487 #endif 488 489 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 490 | CSPR_PORT_SIZE_8 \ 491 | CSPR_MSEL_GPCM \ 492 | CSPR_V) 493 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 494 #define CONFIG_SYS_CSOR3 0x0 495 /* CPLD Timing parameters for IFC CS3 */ 496 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 497 FTIM0_GPCM_TEADC(0x0e) | \ 498 FTIM0_GPCM_TEAHC(0x0e)) 499 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 500 FTIM1_GPCM_TRAD(0x1f)) 501 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 502 FTIM2_GPCM_TCH(0x8) | \ 503 FTIM2_GPCM_TWP(0x1f)) 504 #define CONFIG_SYS_CS3_FTIM3 0x0 505 506 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 507 defined(CONFIG_RAMBOOT_NAND) 508 #define CONFIG_SYS_RAMBOOT 509 #define CONFIG_SYS_EXTRA_ENV_RELOC 510 #else 511 #undef CONFIG_SYS_RAMBOOT 512 #endif 513 514 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 515 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 516 #define CONFIG_A003399_NOR_WORKAROUND 517 #endif 518 #endif 519 520 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 521 #define CONFIG_BOARD_EARLY_INIT_R 522 523 #define CONFIG_SYS_INIT_RAM_LOCK 524 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 525 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 526 527 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 528 - GENERATED_GBL_DATA_SIZE) 529 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 530 531 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 532 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 533 534 /* 535 * Config the L2 Cache as L2 SRAM 536 */ 537 #if defined(CONFIG_SPL_BUILD) 538 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 539 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 540 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 541 #define CONFIG_SYS_L2_SIZE (256 << 10) 542 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 543 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 544 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 545 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 546 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 547 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 548 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 549 #elif defined(CONFIG_NAND) 550 #ifdef CONFIG_TPL_BUILD 551 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 552 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 553 #define CONFIG_SYS_L2_SIZE (256 << 10) 554 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 555 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 556 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 557 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 558 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 559 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 560 #else 561 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 562 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 563 #define CONFIG_SYS_L2_SIZE (256 << 10) 564 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 565 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 566 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 567 #endif 568 #endif 569 #endif 570 571 /* Serial Port */ 572 #define CONFIG_CONS_INDEX 1 573 #undef CONFIG_SERIAL_SOFTWARE_FIFO 574 #define CONFIG_SYS_NS16550_SERIAL 575 #define CONFIG_SYS_NS16550_REG_SIZE 1 576 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 577 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 578 #define CONFIG_NS16550_MIN_FUNCTIONS 579 #endif 580 581 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 582 583 #define CONFIG_SYS_BAUDRATE_TABLE \ 584 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 585 586 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 587 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 588 589 /* I2C */ 590 #define CONFIG_SYS_I2C 591 #define CONFIG_SYS_I2C_FSL 592 #define CONFIG_SYS_FSL_I2C_SPEED 400000 593 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 594 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 595 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 596 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 597 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 598 #define I2C_PCA9557_ADDR1 0x18 599 #define I2C_PCA9557_ADDR2 0x19 600 #define I2C_PCA9557_BUS_NUM 0 601 602 /* I2C EEPROM */ 603 #if defined(CONFIG_P1010RDB_PB) 604 #define CONFIG_ID_EEPROM 605 #ifdef CONFIG_ID_EEPROM 606 #define CONFIG_SYS_I2C_EEPROM_NXID 607 #endif 608 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 609 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 610 #define CONFIG_SYS_EEPROM_BUS_NUM 0 611 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 612 #endif 613 /* enable read and write access to EEPROM */ 614 #define CONFIG_CMD_EEPROM 615 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 616 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 617 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 618 619 /* RTC */ 620 #define CONFIG_RTC_PT7C4338 621 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 622 623 /* 624 * SPI interface will not be available in case of NAND boot SPI CS0 will be 625 * used for SLIC 626 */ 627 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 628 /* eSPI - Enhanced SPI */ 629 #define CONFIG_SF_DEFAULT_SPEED 10000000 630 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 631 #endif 632 633 #if defined(CONFIG_TSEC_ENET) 634 #define CONFIG_MII /* MII PHY management */ 635 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 636 #define CONFIG_TSEC1 1 637 #define CONFIG_TSEC1_NAME "eTSEC1" 638 #define CONFIG_TSEC2 1 639 #define CONFIG_TSEC2_NAME "eTSEC2" 640 #define CONFIG_TSEC3 1 641 #define CONFIG_TSEC3_NAME "eTSEC3" 642 643 #define TSEC1_PHY_ADDR 1 644 #define TSEC2_PHY_ADDR 0 645 #define TSEC3_PHY_ADDR 2 646 647 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 648 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 649 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 650 651 #define TSEC1_PHYIDX 0 652 #define TSEC2_PHYIDX 0 653 #define TSEC3_PHYIDX 0 654 655 #define CONFIG_ETHPRIME "eTSEC1" 656 657 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 658 659 /* TBI PHY configuration for SGMII mode */ 660 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 661 TBICR_PHY_RESET \ 662 | TBICR_ANEG_ENABLE \ 663 | TBICR_FULL_DUPLEX \ 664 | TBICR_SPEED1_SET \ 665 ) 666 667 #endif /* CONFIG_TSEC_ENET */ 668 669 /* SATA */ 670 #define CONFIG_FSL_SATA 671 #define CONFIG_FSL_SATA_V2 672 #define CONFIG_LIBATA 673 674 #ifdef CONFIG_FSL_SATA 675 #define CONFIG_SYS_SATA_MAX_DEVICE 2 676 #define CONFIG_SATA1 677 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 678 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 679 #define CONFIG_SATA2 680 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 681 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 682 683 #define CONFIG_CMD_SATA 684 #define CONFIG_LBA48 685 #endif /* #ifdef CONFIG_FSL_SATA */ 686 687 #define CONFIG_MMC 688 #ifdef CONFIG_MMC 689 #define CONFIG_DOS_PARTITION 690 #define CONFIG_FSL_ESDHC 691 #define CONFIG_GENERIC_MMC 692 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 693 #endif 694 695 #define CONFIG_HAS_FSL_DR_USB 696 697 #if defined(CONFIG_HAS_FSL_DR_USB) 698 #define CONFIG_USB_EHCI 699 700 #ifdef CONFIG_USB_EHCI 701 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 702 #define CONFIG_USB_EHCI_FSL 703 #endif 704 #endif 705 706 /* 707 * Environment 708 */ 709 #if defined(CONFIG_SDCARD) 710 #define CONFIG_ENV_IS_IN_MMC 711 #define CONFIG_FSL_FIXED_MMC_LOCATION 712 #define CONFIG_SYS_MMC_ENV_DEV 0 713 #define CONFIG_ENV_SIZE 0x2000 714 #elif defined(CONFIG_SPIFLASH) 715 #define CONFIG_ENV_IS_IN_SPI_FLASH 716 #define CONFIG_ENV_SPI_BUS 0 717 #define CONFIG_ENV_SPI_CS 0 718 #define CONFIG_ENV_SPI_MAX_HZ 10000000 719 #define CONFIG_ENV_SPI_MODE 0 720 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 721 #define CONFIG_ENV_SECT_SIZE 0x10000 722 #define CONFIG_ENV_SIZE 0x2000 723 #elif defined(CONFIG_NAND) 724 #define CONFIG_ENV_IS_IN_NAND 725 #ifdef CONFIG_TPL_BUILD 726 #define CONFIG_ENV_SIZE 0x2000 727 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 728 #else 729 #if defined(CONFIG_P1010RDB_PA) 730 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 731 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 732 #elif defined(CONFIG_P1010RDB_PB) 733 #define CONFIG_ENV_SIZE (16 * 1024) 734 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 735 #endif 736 #endif 737 #define CONFIG_ENV_OFFSET (1024 * 1024) 738 #elif defined(CONFIG_SYS_RAMBOOT) 739 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 740 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 741 #define CONFIG_ENV_SIZE 0x2000 742 #else 743 #define CONFIG_ENV_IS_IN_FLASH 744 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 745 #define CONFIG_ENV_SIZE 0x2000 746 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 747 #endif 748 749 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 750 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 751 752 /* 753 * Command line configuration. 754 */ 755 #define CONFIG_CMD_DATE 756 #define CONFIG_CMD_ERRATA 757 #define CONFIG_CMD_IRQ 758 #define CONFIG_CMD_REGINFO 759 760 #undef CONFIG_WATCHDOG /* watchdog disabled */ 761 762 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 763 || defined(CONFIG_FSL_SATA) 764 #define CONFIG_DOS_PARTITION 765 #endif 766 767 /* Hash command with SHA acceleration supported in hardware */ 768 #ifdef CONFIG_FSL_CAAM 769 #define CONFIG_CMD_HASH 770 #define CONFIG_SHA_HW_ACCEL 771 #endif 772 773 /* 774 * Miscellaneous configurable options 775 */ 776 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 777 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 778 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 779 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 780 781 #if defined(CONFIG_CMD_KGDB) 782 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 783 #else 784 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 785 #endif 786 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 787 /* Print Buffer Size */ 788 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 789 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 790 791 /* 792 * For booting Linux, the board info and command line data 793 * have to be in the first 64 MB of memory, since this is 794 * the maximum mapped by the Linux kernel during initialization. 795 */ 796 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 797 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 798 799 #if defined(CONFIG_CMD_KGDB) 800 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 801 #endif 802 803 /* 804 * Environment Configuration 805 */ 806 807 #if defined(CONFIG_TSEC_ENET) 808 #define CONFIG_HAS_ETH0 809 #define CONFIG_HAS_ETH1 810 #define CONFIG_HAS_ETH2 811 #endif 812 813 #define CONFIG_ROOTPATH "/opt/nfsroot" 814 #define CONFIG_BOOTFILE "uImage" 815 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 816 817 /* default location for tftp and bootm */ 818 #define CONFIG_LOADADDR 1000000 819 820 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 821 822 #define CONFIG_BAUDRATE 115200 823 824 #define CONFIG_EXTRA_ENV_SETTINGS \ 825 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 826 "netdev=eth0\0" \ 827 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 828 "loadaddr=1000000\0" \ 829 "consoledev=ttyS0\0" \ 830 "ramdiskaddr=2000000\0" \ 831 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 832 "fdtaddr=1e00000\0" \ 833 "fdtfile=p1010rdb.dtb\0" \ 834 "bdev=sda1\0" \ 835 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 836 "othbootargs=ramdisk_size=600000\0" \ 837 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 838 "console=$consoledev,$baudrate $othbootargs; " \ 839 "usb start;" \ 840 "fatload usb 0:2 $loadaddr $bootfile;" \ 841 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 842 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 843 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 844 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 845 "console=$consoledev,$baudrate $othbootargs; " \ 846 "usb start;" \ 847 "ext2load usb 0:4 $loadaddr $bootfile;" \ 848 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 849 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 850 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 851 CONFIG_BOOTMODE 852 853 #if defined(CONFIG_P1010RDB_PA) 854 #define CONFIG_BOOTMODE \ 855 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 856 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 857 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 858 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 859 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 860 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 861 862 #elif defined(CONFIG_P1010RDB_PB) 863 #define CONFIG_BOOTMODE \ 864 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 865 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 866 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 867 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 868 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 869 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 870 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 871 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 872 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 873 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 874 #endif 875 876 #define CONFIG_RAMBOOTCOMMAND \ 877 "setenv bootargs root=/dev/ram rw " \ 878 "console=$consoledev,$baudrate $othbootargs; " \ 879 "tftp $ramdiskaddr $ramdiskfile;" \ 880 "tftp $loadaddr $bootfile;" \ 881 "tftp $fdtaddr $fdtfile;" \ 882 "bootm $loadaddr $ramdiskaddr $fdtaddr" 883 884 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 885 886 #include <asm/fsl_secure_boot.h> 887 888 #endif /* __CONFIG_H */ 889