1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_P1010 17 #define CONFIG_E500 /* BOOKE e500 family */ 18 #include <asm/config_mpc85xx.h> 19 #define CONFIG_NAND_FSL_IFC 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 23 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 24 #define CONFIG_SPL_ENV_SUPPORT 25 #define CONFIG_SPL_SERIAL_SUPPORT 26 #define CONFIG_SPL_MMC_SUPPORT 27 #define CONFIG_SPL_MMC_MINIMAL 28 #define CONFIG_SPL_FLUSH_IMAGE 29 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 30 #define CONFIG_SPL_LIBGENERIC_SUPPORT 31 #define CONFIG_SPL_LIBCOMMON_SUPPORT 32 #define CONFIG_SPL_I2C_SUPPORT 33 #define CONFIG_FSL_LAW /* Use common FSL init code */ 34 #define CONFIG_SYS_TEXT_BASE 0x11001000 35 #define CONFIG_SPL_TEXT_BASE 0xD0001000 36 #define CONFIG_SPL_PAD_TO 0x18000 37 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 38 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 39 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 40 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 41 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 42 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SPL_MMC_BOOT 45 #ifdef CONFIG_SPL_BUILD 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #endif 48 #endif 49 50 #ifdef CONFIG_SPIFLASH 51 #ifdef CONFIG_SECURE_BOOT 52 #define CONFIG_RAMBOOT_SPIFLASH 53 #define CONFIG_SYS_TEXT_BASE 0x11000000 54 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 55 #else 56 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 57 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 58 #define CONFIG_SPL_ENV_SUPPORT 59 #define CONFIG_SPL_SERIAL_SUPPORT 60 #define CONFIG_SPL_SPI_SUPPORT 61 #define CONFIG_SPL_SPI_FLASH_SUPPORT 62 #define CONFIG_SPL_SPI_FLASH_MINIMAL 63 #define CONFIG_SPL_FLUSH_IMAGE 64 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 65 #define CONFIG_SPL_LIBGENERIC_SUPPORT 66 #define CONFIG_SPL_LIBCOMMON_SUPPORT 67 #define CONFIG_SPL_I2C_SUPPORT 68 #define CONFIG_FSL_LAW /* Use common FSL init code */ 69 #define CONFIG_SYS_TEXT_BASE 0x11001000 70 #define CONFIG_SPL_TEXT_BASE 0xD0001000 71 #define CONFIG_SPL_PAD_TO 0x18000 72 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 79 #define CONFIG_SPL_SPI_BOOT 80 #ifdef CONFIG_SPL_BUILD 81 #define CONFIG_SPL_COMMON_INIT_DDR 82 #endif 83 #endif 84 #endif 85 86 #ifdef CONFIG_NAND 87 #ifdef CONFIG_SECURE_BOOT 88 #define CONFIG_SPL_INIT_MINIMAL 89 #define CONFIG_SPL_SERIAL_SUPPORT 90 #define CONFIG_SPL_NAND_SUPPORT 91 #define CONFIG_SPL_NAND_BOOT 92 #define CONFIG_SPL_FLUSH_IMAGE 93 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 94 95 #define CONFIG_SYS_TEXT_BASE 0x00201000 96 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 97 #define CONFIG_SPL_MAX_SIZE 8192 98 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 99 #define CONFIG_SPL_RELOC_STACK 0x00100000 100 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 101 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 102 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 103 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 105 #else 106 #ifdef CONFIG_TPL_BUILD 107 #define CONFIG_SPL_NAND_BOOT 108 #define CONFIG_SPL_FLUSH_IMAGE 109 #define CONFIG_SPL_ENV_SUPPORT 110 #define CONFIG_SPL_NAND_INIT 111 #define CONFIG_SPL_SERIAL_SUPPORT 112 #define CONFIG_SPL_LIBGENERIC_SUPPORT 113 #define CONFIG_SPL_LIBCOMMON_SUPPORT 114 #define CONFIG_SPL_I2C_SUPPORT 115 #define CONFIG_SPL_NAND_SUPPORT 116 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 117 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 118 #define CONFIG_SPL_COMMON_INIT_DDR 119 #define CONFIG_SPL_MAX_SIZE (128 << 10) 120 #define CONFIG_SPL_TEXT_BASE 0xD0001000 121 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 122 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 123 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 124 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 125 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 126 #elif defined(CONFIG_SPL_BUILD) 127 #define CONFIG_SPL_INIT_MINIMAL 128 #define CONFIG_SPL_SERIAL_SUPPORT 129 #define CONFIG_SPL_NAND_SUPPORT 130 #define CONFIG_SPL_NAND_MINIMAL 131 #define CONFIG_SPL_FLUSH_IMAGE 132 #define CONFIG_SPL_TEXT_BASE 0xff800000 133 #define CONFIG_SPL_MAX_SIZE 8192 134 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 135 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 136 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 137 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 138 #endif 139 #define CONFIG_SPL_PAD_TO 0x20000 140 #define CONFIG_TPL_PAD_TO 0x20000 141 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 142 #define CONFIG_SYS_TEXT_BASE 0x11001000 143 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 144 #endif 145 #endif 146 147 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 148 #define CONFIG_RAMBOOT_NAND 149 #define CONFIG_SYS_TEXT_BASE 0x11000000 150 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 151 #endif 152 153 #ifndef CONFIG_SYS_TEXT_BASE 154 #define CONFIG_SYS_TEXT_BASE 0xeff40000 155 #endif 156 157 #ifndef CONFIG_RESET_VECTOR_ADDRESS 158 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 159 #endif 160 161 #ifdef CONFIG_SPL_BUILD 162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 163 #else 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 165 #endif 166 167 /* High Level Configuration Options */ 168 #define CONFIG_BOOKE /* BOOKE */ 169 #define CONFIG_E500 /* BOOKE e500 family */ 170 #define CONFIG_FSL_IFC /* Enable IFC Support */ 171 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 172 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 173 174 #define CONFIG_PCI /* Enable PCI/PCIE */ 175 #if defined(CONFIG_PCI) 176 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 177 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 178 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 179 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 180 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 181 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 182 183 #define CONFIG_CMD_PCI 184 185 /* 186 * PCI Windows 187 * Memory space is mapped 1-1, but I/O space must start from 0. 188 */ 189 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 190 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 191 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 192 #ifdef CONFIG_PHYS_64BIT 193 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 194 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 195 #else 196 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 197 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 198 #endif 199 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 200 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 201 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 202 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 203 #ifdef CONFIG_PHYS_64BIT 204 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 205 #else 206 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 207 #endif 208 209 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 210 #if defined(CONFIG_P1010RDB_PA) 211 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 212 #elif defined(CONFIG_P1010RDB_PB) 213 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 214 #endif 215 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 216 #ifdef CONFIG_PHYS_64BIT 217 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 218 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 219 #else 220 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 221 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 222 #endif 223 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 224 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 225 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 226 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 227 #ifdef CONFIG_PHYS_64BIT 228 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 229 #else 230 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 231 #endif 232 233 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 234 235 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 236 #define CONFIG_DOS_PARTITION 237 #endif 238 239 #define CONFIG_FSL_LAW /* Use common FSL init code */ 240 #define CONFIG_TSEC_ENET 241 #define CONFIG_ENV_OVERWRITE 242 243 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 244 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 245 246 #define CONFIG_MISC_INIT_R 247 #define CONFIG_HWCONFIG 248 /* 249 * These can be toggled for performance analysis, otherwise use default. 250 */ 251 #define CONFIG_L2_CACHE /* toggle L2 cache */ 252 #define CONFIG_BTB /* toggle branch predition */ 253 254 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 255 256 #define CONFIG_ENABLE_36BIT_PHYS 257 258 #ifdef CONFIG_PHYS_64BIT 259 #define CONFIG_ADDR_MAP 1 260 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 261 #endif 262 263 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 264 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 265 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 266 267 /* DDR Setup */ 268 #define CONFIG_SYS_FSL_DDR3 269 #define CONFIG_SYS_DDR_RAW_TIMING 270 #define CONFIG_DDR_SPD 271 #define CONFIG_SYS_SPD_BUS_NUM 1 272 #define SPD_EEPROM_ADDRESS 0x52 273 274 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 275 276 #ifndef __ASSEMBLY__ 277 extern unsigned long get_sdram_size(void); 278 #endif 279 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 280 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 281 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 282 283 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 284 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 285 286 /* DDR3 Controller Settings */ 287 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 288 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 289 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 290 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 291 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 292 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 293 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 294 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 295 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 296 #define CONFIG_SYS_DDR_RCW_1 0x00000000 297 #define CONFIG_SYS_DDR_RCW_2 0x00000000 298 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 299 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 300 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 301 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 302 303 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 304 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 305 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 306 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 307 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 308 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 309 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 310 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 311 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 312 313 /* settings for DDR3 at 667MT/s */ 314 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 315 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 316 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 317 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 318 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 319 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 320 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 321 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 322 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 323 324 #define CONFIG_SYS_CCSRBAR 0xffe00000 325 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 326 327 /* Don't relocate CCSRBAR while in NAND_SPL */ 328 #ifdef CONFIG_SPL_BUILD 329 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 330 #endif 331 332 /* 333 * Memory map 334 * 335 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 336 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 337 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 338 * 339 * Localbus non-cacheable 340 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 341 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 342 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 343 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 344 */ 345 346 /* 347 * IFC Definitions 348 */ 349 /* NOR Flash on IFC */ 350 #ifdef CONFIG_SPL_BUILD 351 #define CONFIG_SYS_NO_FLASH 352 #endif 353 354 #define CONFIG_SYS_FLASH_BASE 0xee000000 355 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 356 357 #ifdef CONFIG_PHYS_64BIT 358 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 359 #else 360 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 361 #endif 362 363 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 364 CSPR_PORT_SIZE_16 | \ 365 CSPR_MSEL_NOR | \ 366 CSPR_V) 367 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 368 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 369 /* NOR Flash Timing Params */ 370 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 371 FTIM0_NOR_TEADC(0x5) | \ 372 FTIM0_NOR_TEAHC(0x5) 373 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 374 FTIM1_NOR_TRAD_NOR(0x0f) 375 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 376 FTIM2_NOR_TCH(0x4) | \ 377 FTIM2_NOR_TWP(0x1c) 378 #define CONFIG_SYS_NOR_FTIM3 0x0 379 380 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 381 #define CONFIG_SYS_FLASH_QUIET_TEST 382 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 383 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 384 385 #undef CONFIG_SYS_FLASH_CHECKSUM 386 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 387 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 388 389 /* CFI for NOR Flash */ 390 #define CONFIG_FLASH_CFI_DRIVER 391 #define CONFIG_SYS_FLASH_CFI 392 #define CONFIG_SYS_FLASH_EMPTY_INFO 393 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 394 395 /* NAND Flash on IFC */ 396 #define CONFIG_SYS_NAND_BASE 0xff800000 397 #ifdef CONFIG_PHYS_64BIT 398 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 399 #else 400 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 401 #endif 402 403 #define CONFIG_MTD_DEVICE 404 #define CONFIG_MTD_PARTITION 405 #define CONFIG_CMD_MTDPARTS 406 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 407 #define MTDPARTS_DEFAULT \ 408 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 409 410 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 411 | CSPR_PORT_SIZE_8 \ 412 | CSPR_MSEL_NAND \ 413 | CSPR_V) 414 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 415 416 #if defined(CONFIG_P1010RDB_PA) 417 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 418 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 419 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 420 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 421 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 422 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 423 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 424 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 425 426 #elif defined(CONFIG_P1010RDB_PB) 427 #define CONFIG_SYS_NAND_ONFI_DETECTION 428 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 429 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 430 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 431 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 432 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 433 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 434 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 435 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 436 #endif 437 438 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 439 #define CONFIG_SYS_MAX_NAND_DEVICE 1 440 #define CONFIG_CMD_NAND 441 442 #if defined(CONFIG_P1010RDB_PA) 443 /* NAND Flash Timing Params */ 444 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 445 FTIM0_NAND_TWP(0x0C) | \ 446 FTIM0_NAND_TWCHT(0x04) | \ 447 FTIM0_NAND_TWH(0x05) 448 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 449 FTIM1_NAND_TWBE(0x1d) | \ 450 FTIM1_NAND_TRR(0x07) | \ 451 FTIM1_NAND_TRP(0x0c) 452 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 453 FTIM2_NAND_TREH(0x05) | \ 454 FTIM2_NAND_TWHRE(0x0f) 455 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 456 457 #elif defined(CONFIG_P1010RDB_PB) 458 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 459 /* ONFI NAND Flash mode0 Timing Params */ 460 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 461 FTIM0_NAND_TWP(0x18) | \ 462 FTIM0_NAND_TWCHT(0x07) | \ 463 FTIM0_NAND_TWH(0x0a)) 464 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 465 FTIM1_NAND_TWBE(0x39) | \ 466 FTIM1_NAND_TRR(0x0e) | \ 467 FTIM1_NAND_TRP(0x18)) 468 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 469 FTIM2_NAND_TREH(0x0a) | \ 470 FTIM2_NAND_TWHRE(0x1e)) 471 #define CONFIG_SYS_NAND_FTIM3 0x0 472 #endif 473 474 #define CONFIG_SYS_NAND_DDR_LAW 11 475 476 /* Set up IFC registers for boot location NOR/NAND */ 477 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 478 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 479 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 480 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 481 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 482 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 483 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 484 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 485 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 486 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 487 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 488 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 489 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 490 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 491 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 492 #else 493 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 494 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 495 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 496 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 497 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 498 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 499 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 500 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 501 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 502 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 503 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 504 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 505 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 506 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 507 #endif 508 509 /* CPLD on IFC */ 510 #define CONFIG_SYS_CPLD_BASE 0xffb00000 511 512 #ifdef CONFIG_PHYS_64BIT 513 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 514 #else 515 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 516 #endif 517 518 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 519 | CSPR_PORT_SIZE_8 \ 520 | CSPR_MSEL_GPCM \ 521 | CSPR_V) 522 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 523 #define CONFIG_SYS_CSOR3 0x0 524 /* CPLD Timing parameters for IFC CS3 */ 525 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 526 FTIM0_GPCM_TEADC(0x0e) | \ 527 FTIM0_GPCM_TEAHC(0x0e)) 528 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 529 FTIM1_GPCM_TRAD(0x1f)) 530 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 531 FTIM2_GPCM_TCH(0x8) | \ 532 FTIM2_GPCM_TWP(0x1f)) 533 #define CONFIG_SYS_CS3_FTIM3 0x0 534 535 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 536 defined(CONFIG_RAMBOOT_NAND) 537 #define CONFIG_SYS_RAMBOOT 538 #define CONFIG_SYS_EXTRA_ENV_RELOC 539 #else 540 #undef CONFIG_SYS_RAMBOOT 541 #endif 542 543 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 544 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 545 #define CONFIG_A003399_NOR_WORKAROUND 546 #endif 547 #endif 548 549 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 550 #define CONFIG_BOARD_EARLY_INIT_R 551 552 #define CONFIG_SYS_INIT_RAM_LOCK 553 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 554 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 555 556 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 557 - GENERATED_GBL_DATA_SIZE) 558 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 559 560 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 561 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 562 563 /* 564 * Config the L2 Cache as L2 SRAM 565 */ 566 #if defined(CONFIG_SPL_BUILD) 567 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 568 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 569 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 570 #define CONFIG_SYS_L2_SIZE (256 << 10) 571 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 572 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 573 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 574 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 575 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 576 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 577 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 578 #elif defined(CONFIG_NAND) 579 #ifdef CONFIG_TPL_BUILD 580 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 581 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 582 #define CONFIG_SYS_L2_SIZE (256 << 10) 583 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 584 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 585 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 586 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 587 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 588 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 589 #else 590 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 591 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 592 #define CONFIG_SYS_L2_SIZE (256 << 10) 593 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 594 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 595 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 596 #endif 597 #endif 598 #endif 599 600 /* Serial Port */ 601 #define CONFIG_CONS_INDEX 1 602 #undef CONFIG_SERIAL_SOFTWARE_FIFO 603 #define CONFIG_SYS_NS16550_SERIAL 604 #define CONFIG_SYS_NS16550_REG_SIZE 1 605 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 606 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 607 #define CONFIG_NS16550_MIN_FUNCTIONS 608 #endif 609 610 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 611 612 #define CONFIG_SYS_BAUDRATE_TABLE \ 613 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 614 615 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 616 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 617 618 /* I2C */ 619 #define CONFIG_SYS_I2C 620 #define CONFIG_SYS_I2C_FSL 621 #define CONFIG_SYS_FSL_I2C_SPEED 400000 622 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 623 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 624 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 625 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 626 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 627 #define I2C_PCA9557_ADDR1 0x18 628 #define I2C_PCA9557_ADDR2 0x19 629 #define I2C_PCA9557_BUS_NUM 0 630 631 /* I2C EEPROM */ 632 #if defined(CONFIG_P1010RDB_PB) 633 #define CONFIG_ID_EEPROM 634 #ifdef CONFIG_ID_EEPROM 635 #define CONFIG_SYS_I2C_EEPROM_NXID 636 #endif 637 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 638 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 639 #define CONFIG_SYS_EEPROM_BUS_NUM 0 640 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 641 #endif 642 /* enable read and write access to EEPROM */ 643 #define CONFIG_CMD_EEPROM 644 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 645 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 646 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 647 648 /* RTC */ 649 #define CONFIG_RTC_PT7C4338 650 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 651 652 /* 653 * SPI interface will not be available in case of NAND boot SPI CS0 will be 654 * used for SLIC 655 */ 656 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 657 /* eSPI - Enhanced SPI */ 658 #define CONFIG_SF_DEFAULT_SPEED 10000000 659 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 660 #endif 661 662 #if defined(CONFIG_TSEC_ENET) 663 #define CONFIG_MII /* MII PHY management */ 664 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 665 #define CONFIG_TSEC1 1 666 #define CONFIG_TSEC1_NAME "eTSEC1" 667 #define CONFIG_TSEC2 1 668 #define CONFIG_TSEC2_NAME "eTSEC2" 669 #define CONFIG_TSEC3 1 670 #define CONFIG_TSEC3_NAME "eTSEC3" 671 672 #define TSEC1_PHY_ADDR 1 673 #define TSEC2_PHY_ADDR 0 674 #define TSEC3_PHY_ADDR 2 675 676 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 677 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 678 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 679 680 #define TSEC1_PHYIDX 0 681 #define TSEC2_PHYIDX 0 682 #define TSEC3_PHYIDX 0 683 684 #define CONFIG_ETHPRIME "eTSEC1" 685 686 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 687 688 /* TBI PHY configuration for SGMII mode */ 689 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 690 TBICR_PHY_RESET \ 691 | TBICR_ANEG_ENABLE \ 692 | TBICR_FULL_DUPLEX \ 693 | TBICR_SPEED1_SET \ 694 ) 695 696 #endif /* CONFIG_TSEC_ENET */ 697 698 /* SATA */ 699 #define CONFIG_FSL_SATA 700 #define CONFIG_FSL_SATA_V2 701 #define CONFIG_LIBATA 702 703 #ifdef CONFIG_FSL_SATA 704 #define CONFIG_SYS_SATA_MAX_DEVICE 2 705 #define CONFIG_SATA1 706 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 707 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 708 #define CONFIG_SATA2 709 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 710 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 711 712 #define CONFIG_CMD_SATA 713 #define CONFIG_LBA48 714 #endif /* #ifdef CONFIG_FSL_SATA */ 715 716 #define CONFIG_MMC 717 #ifdef CONFIG_MMC 718 #define CONFIG_DOS_PARTITION 719 #define CONFIG_FSL_ESDHC 720 #define CONFIG_GENERIC_MMC 721 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 722 #endif 723 724 #define CONFIG_HAS_FSL_DR_USB 725 726 #if defined(CONFIG_HAS_FSL_DR_USB) 727 #define CONFIG_USB_EHCI 728 729 #ifdef CONFIG_USB_EHCI 730 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 731 #define CONFIG_USB_EHCI_FSL 732 #define CONFIG_USB_STORAGE 733 #endif 734 #endif 735 736 /* 737 * Environment 738 */ 739 #if defined(CONFIG_SDCARD) 740 #define CONFIG_ENV_IS_IN_MMC 741 #define CONFIG_FSL_FIXED_MMC_LOCATION 742 #define CONFIG_SYS_MMC_ENV_DEV 0 743 #define CONFIG_ENV_SIZE 0x2000 744 #elif defined(CONFIG_SPIFLASH) 745 #define CONFIG_ENV_IS_IN_SPI_FLASH 746 #define CONFIG_ENV_SPI_BUS 0 747 #define CONFIG_ENV_SPI_CS 0 748 #define CONFIG_ENV_SPI_MAX_HZ 10000000 749 #define CONFIG_ENV_SPI_MODE 0 750 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 751 #define CONFIG_ENV_SECT_SIZE 0x10000 752 #define CONFIG_ENV_SIZE 0x2000 753 #elif defined(CONFIG_NAND) 754 #define CONFIG_ENV_IS_IN_NAND 755 #ifdef CONFIG_TPL_BUILD 756 #define CONFIG_ENV_SIZE 0x2000 757 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 758 #else 759 #if defined(CONFIG_P1010RDB_PA) 760 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 761 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 762 #elif defined(CONFIG_P1010RDB_PB) 763 #define CONFIG_ENV_SIZE (16 * 1024) 764 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 765 #endif 766 #endif 767 #define CONFIG_ENV_OFFSET (1024 * 1024) 768 #elif defined(CONFIG_SYS_RAMBOOT) 769 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 770 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 771 #define CONFIG_ENV_SIZE 0x2000 772 #else 773 #define CONFIG_ENV_IS_IN_FLASH 774 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 775 #define CONFIG_ENV_SIZE 0x2000 776 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 777 #endif 778 779 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 780 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 781 782 /* 783 * Command line configuration. 784 */ 785 #define CONFIG_CMD_DATE 786 #define CONFIG_CMD_ERRATA 787 #define CONFIG_CMD_IRQ 788 #define CONFIG_CMD_REGINFO 789 790 #undef CONFIG_WATCHDOG /* watchdog disabled */ 791 792 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 793 || defined(CONFIG_FSL_SATA) 794 #define CONFIG_DOS_PARTITION 795 #endif 796 797 /* Hash command with SHA acceleration supported in hardware */ 798 #ifdef CONFIG_FSL_CAAM 799 #define CONFIG_CMD_HASH 800 #define CONFIG_SHA_HW_ACCEL 801 #endif 802 803 /* 804 * Miscellaneous configurable options 805 */ 806 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 807 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 808 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 809 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 810 811 #if defined(CONFIG_CMD_KGDB) 812 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 813 #else 814 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 815 #endif 816 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 817 /* Print Buffer Size */ 818 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 819 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 820 821 /* 822 * For booting Linux, the board info and command line data 823 * have to be in the first 64 MB of memory, since this is 824 * the maximum mapped by the Linux kernel during initialization. 825 */ 826 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 827 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 828 829 #if defined(CONFIG_CMD_KGDB) 830 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 831 #endif 832 833 /* 834 * Environment Configuration 835 */ 836 837 #if defined(CONFIG_TSEC_ENET) 838 #define CONFIG_HAS_ETH0 839 #define CONFIG_HAS_ETH1 840 #define CONFIG_HAS_ETH2 841 #endif 842 843 #define CONFIG_ROOTPATH "/opt/nfsroot" 844 #define CONFIG_BOOTFILE "uImage" 845 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 846 847 /* default location for tftp and bootm */ 848 #define CONFIG_LOADADDR 1000000 849 850 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 851 852 #define CONFIG_BAUDRATE 115200 853 854 #define CONFIG_EXTRA_ENV_SETTINGS \ 855 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 856 "netdev=eth0\0" \ 857 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 858 "loadaddr=1000000\0" \ 859 "consoledev=ttyS0\0" \ 860 "ramdiskaddr=2000000\0" \ 861 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 862 "fdtaddr=1e00000\0" \ 863 "fdtfile=p1010rdb.dtb\0" \ 864 "bdev=sda1\0" \ 865 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 866 "othbootargs=ramdisk_size=600000\0" \ 867 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 868 "console=$consoledev,$baudrate $othbootargs; " \ 869 "usb start;" \ 870 "fatload usb 0:2 $loadaddr $bootfile;" \ 871 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 872 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 873 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 874 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 875 "console=$consoledev,$baudrate $othbootargs; " \ 876 "usb start;" \ 877 "ext2load usb 0:4 $loadaddr $bootfile;" \ 878 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 879 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 880 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 881 CONFIG_BOOTMODE 882 883 #if defined(CONFIG_P1010RDB_PA) 884 #define CONFIG_BOOTMODE \ 885 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 886 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 887 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 888 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 889 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 890 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 891 892 #elif defined(CONFIG_P1010RDB_PB) 893 #define CONFIG_BOOTMODE \ 894 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 895 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 896 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 897 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 898 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 899 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 900 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 901 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 902 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 903 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 904 #endif 905 906 #define CONFIG_RAMBOOTCOMMAND \ 907 "setenv bootargs root=/dev/ram rw " \ 908 "console=$consoledev,$baudrate $othbootargs; " \ 909 "tftp $ramdiskaddr $ramdiskfile;" \ 910 "tftp $loadaddr $bootfile;" \ 911 "tftp $fdtaddr $fdtfile;" \ 912 "bootm $loadaddr $ramdiskaddr $fdtaddr" 913 914 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 915 916 #include <asm/fsl_secure_boot.h> 917 918 #endif /* __CONFIG_H */ 919