1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_E500 /* BOOKE e500 family */ 15 #include <asm/config_mpc85xx.h> 16 #define CONFIG_NAND_FSL_IFC 17 18 #ifdef CONFIG_SDCARD 19 #define CONFIG_SPL_MMC_MINIMAL 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_SYS_TEXT_BASE 0x11001000 23 #define CONFIG_SPL_TEXT_BASE 0xD0001000 24 #define CONFIG_SPL_PAD_TO 0x18000 25 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 26 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 27 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 28 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 29 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 30 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 31 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 32 #define CONFIG_SPL_MMC_BOOT 33 #ifdef CONFIG_SPL_BUILD 34 #define CONFIG_SPL_COMMON_INIT_DDR 35 #endif 36 #endif 37 38 #ifdef CONFIG_SPIFLASH 39 #ifdef CONFIG_SECURE_BOOT 40 #define CONFIG_RAMBOOT_SPIFLASH 41 #define CONFIG_SYS_TEXT_BASE 0x11000000 42 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 43 #else 44 #define CONFIG_SPL_SPI_FLASH_MINIMAL 45 #define CONFIG_SPL_FLUSH_IMAGE 46 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 47 #define CONFIG_SYS_TEXT_BASE 0x11001000 48 #define CONFIG_SPL_TEXT_BASE 0xD0001000 49 #define CONFIG_SPL_PAD_TO 0x18000 50 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 54 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 56 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 57 #define CONFIG_SPL_SPI_BOOT 58 #ifdef CONFIG_SPL_BUILD 59 #define CONFIG_SPL_COMMON_INIT_DDR 60 #endif 61 #endif 62 #endif 63 64 #ifdef CONFIG_NAND 65 #ifdef CONFIG_SECURE_BOOT 66 #define CONFIG_SPL_INIT_MINIMAL 67 #define CONFIG_SPL_NAND_BOOT 68 #define CONFIG_SPL_FLUSH_IMAGE 69 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 70 71 #define CONFIG_SYS_TEXT_BASE 0x00201000 72 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 73 #define CONFIG_SPL_MAX_SIZE 8192 74 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 75 #define CONFIG_SPL_RELOC_STACK 0x00100000 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 77 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 78 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 81 #else 82 #ifdef CONFIG_TPL_BUILD 83 #define CONFIG_SPL_NAND_BOOT 84 #define CONFIG_SPL_FLUSH_IMAGE 85 #define CONFIG_SPL_NAND_INIT 86 #define CONFIG_SPL_COMMON_INIT_DDR 87 #define CONFIG_SPL_MAX_SIZE (128 << 10) 88 #define CONFIG_SPL_TEXT_BASE 0xD0001000 89 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 90 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 91 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 92 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 93 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 94 #elif defined(CONFIG_SPL_BUILD) 95 #define CONFIG_SPL_INIT_MINIMAL 96 #define CONFIG_SPL_NAND_MINIMAL 97 #define CONFIG_SPL_FLUSH_IMAGE 98 #define CONFIG_SPL_TEXT_BASE 0xff800000 99 #define CONFIG_SPL_MAX_SIZE 8192 100 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 101 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 102 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 103 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 104 #endif 105 #define CONFIG_SPL_PAD_TO 0x20000 106 #define CONFIG_TPL_PAD_TO 0x20000 107 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 108 #define CONFIG_SYS_TEXT_BASE 0x11001000 109 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 110 #endif 111 #endif 112 113 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 114 #define CONFIG_RAMBOOT_NAND 115 #define CONFIG_SYS_TEXT_BASE 0x11000000 116 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 117 #endif 118 119 #ifndef CONFIG_SYS_TEXT_BASE 120 #define CONFIG_SYS_TEXT_BASE 0xeff40000 121 #endif 122 123 #ifndef CONFIG_RESET_VECTOR_ADDRESS 124 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 125 #endif 126 127 #ifdef CONFIG_SPL_BUILD 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 129 #else 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 131 #endif 132 133 /* High Level Configuration Options */ 134 #define CONFIG_BOOKE /* BOOKE */ 135 #define CONFIG_E500 /* BOOKE e500 family */ 136 #define CONFIG_FSL_IFC /* Enable IFC Support */ 137 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 138 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 139 140 #if defined(CONFIG_PCI) 141 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 142 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 143 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 144 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 145 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 146 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 147 148 #define CONFIG_CMD_PCI 149 150 /* 151 * PCI Windows 152 * Memory space is mapped 1-1, but I/O space must start from 0. 153 */ 154 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 155 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 156 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 157 #ifdef CONFIG_PHYS_64BIT 158 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 159 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 160 #else 161 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 162 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 163 #endif 164 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 165 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 166 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 167 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 168 #ifdef CONFIG_PHYS_64BIT 169 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 170 #else 171 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 172 #endif 173 174 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 175 #if defined(CONFIG_TARGET_P1010RDB_PA) 176 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 177 #elif defined(CONFIG_TARGET_P1010RDB_PB) 178 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 179 #endif 180 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 181 #ifdef CONFIG_PHYS_64BIT 182 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 183 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 184 #else 185 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 186 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 187 #endif 188 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 189 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 190 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 191 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 192 #ifdef CONFIG_PHYS_64BIT 193 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 194 #else 195 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 196 #endif 197 198 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 199 #define CONFIG_DOS_PARTITION 200 #endif 201 202 #define CONFIG_TSEC_ENET 203 #define CONFIG_ENV_OVERWRITE 204 205 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 206 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 207 208 #define CONFIG_MISC_INIT_R 209 #define CONFIG_HWCONFIG 210 /* 211 * These can be toggled for performance analysis, otherwise use default. 212 */ 213 #define CONFIG_L2_CACHE /* toggle L2 cache */ 214 #define CONFIG_BTB /* toggle branch predition */ 215 216 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 217 218 #define CONFIG_ENABLE_36BIT_PHYS 219 220 #ifdef CONFIG_PHYS_64BIT 221 #define CONFIG_ADDR_MAP 1 222 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 223 #endif 224 225 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 226 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 227 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 228 229 /* DDR Setup */ 230 #define CONFIG_SYS_FSL_DDR3 231 #define CONFIG_SYS_DDR_RAW_TIMING 232 #define CONFIG_DDR_SPD 233 #define CONFIG_SYS_SPD_BUS_NUM 1 234 #define SPD_EEPROM_ADDRESS 0x52 235 236 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 237 238 #ifndef __ASSEMBLY__ 239 extern unsigned long get_sdram_size(void); 240 #endif 241 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 242 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 243 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 244 245 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 246 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 247 248 /* DDR3 Controller Settings */ 249 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 250 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 251 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 252 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 253 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 254 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 255 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 256 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 257 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 258 #define CONFIG_SYS_DDR_RCW_1 0x00000000 259 #define CONFIG_SYS_DDR_RCW_2 0x00000000 260 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 261 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 262 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 263 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 264 265 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 266 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 267 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 268 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 269 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 270 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 271 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 272 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 273 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 274 275 /* settings for DDR3 at 667MT/s */ 276 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 277 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 278 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 279 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 280 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 281 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 282 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 283 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 284 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 285 286 #define CONFIG_SYS_CCSRBAR 0xffe00000 287 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 288 289 /* Don't relocate CCSRBAR while in NAND_SPL */ 290 #ifdef CONFIG_SPL_BUILD 291 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 292 #endif 293 294 /* 295 * Memory map 296 * 297 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 298 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 299 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 300 * 301 * Localbus non-cacheable 302 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 303 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 304 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 305 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 306 */ 307 308 /* 309 * IFC Definitions 310 */ 311 /* NOR Flash on IFC */ 312 #ifdef CONFIG_SPL_BUILD 313 #define CONFIG_SYS_NO_FLASH 314 #endif 315 316 #define CONFIG_SYS_FLASH_BASE 0xee000000 317 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 318 319 #ifdef CONFIG_PHYS_64BIT 320 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 321 #else 322 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 323 #endif 324 325 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 326 CSPR_PORT_SIZE_16 | \ 327 CSPR_MSEL_NOR | \ 328 CSPR_V) 329 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 330 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 331 /* NOR Flash Timing Params */ 332 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 333 FTIM0_NOR_TEADC(0x5) | \ 334 FTIM0_NOR_TEAHC(0x5) 335 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 336 FTIM1_NOR_TRAD_NOR(0x0f) 337 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 338 FTIM2_NOR_TCH(0x4) | \ 339 FTIM2_NOR_TWP(0x1c) 340 #define CONFIG_SYS_NOR_FTIM3 0x0 341 342 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 343 #define CONFIG_SYS_FLASH_QUIET_TEST 344 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 345 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 346 347 #undef CONFIG_SYS_FLASH_CHECKSUM 348 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 349 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 350 351 /* CFI for NOR Flash */ 352 #define CONFIG_FLASH_CFI_DRIVER 353 #define CONFIG_SYS_FLASH_CFI 354 #define CONFIG_SYS_FLASH_EMPTY_INFO 355 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 356 357 /* NAND Flash on IFC */ 358 #define CONFIG_SYS_NAND_BASE 0xff800000 359 #ifdef CONFIG_PHYS_64BIT 360 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 361 #else 362 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 363 #endif 364 365 #define CONFIG_MTD_DEVICE 366 #define CONFIG_MTD_PARTITION 367 #define CONFIG_CMD_MTDPARTS 368 #define MTDIDS_DEFAULT "nand0=ff800000.flash" 369 #define MTDPARTS_DEFAULT \ 370 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" 371 372 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 373 | CSPR_PORT_SIZE_8 \ 374 | CSPR_MSEL_NAND \ 375 | CSPR_V) 376 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 377 378 #if defined(CONFIG_TARGET_P1010RDB_PA) 379 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 380 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 381 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 382 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 383 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 384 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 385 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 386 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 387 388 #elif defined(CONFIG_TARGET_P1010RDB_PB) 389 #define CONFIG_SYS_NAND_ONFI_DETECTION 390 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 391 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 392 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 393 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 394 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 395 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 396 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 397 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 398 #endif 399 400 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 401 #define CONFIG_SYS_MAX_NAND_DEVICE 1 402 #define CONFIG_CMD_NAND 403 404 #if defined(CONFIG_TARGET_P1010RDB_PA) 405 /* NAND Flash Timing Params */ 406 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 407 FTIM0_NAND_TWP(0x0C) | \ 408 FTIM0_NAND_TWCHT(0x04) | \ 409 FTIM0_NAND_TWH(0x05) 410 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 411 FTIM1_NAND_TWBE(0x1d) | \ 412 FTIM1_NAND_TRR(0x07) | \ 413 FTIM1_NAND_TRP(0x0c) 414 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 415 FTIM2_NAND_TREH(0x05) | \ 416 FTIM2_NAND_TWHRE(0x0f) 417 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 418 419 #elif defined(CONFIG_TARGET_P1010RDB_PB) 420 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 421 /* ONFI NAND Flash mode0 Timing Params */ 422 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 423 FTIM0_NAND_TWP(0x18) | \ 424 FTIM0_NAND_TWCHT(0x07) | \ 425 FTIM0_NAND_TWH(0x0a)) 426 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 427 FTIM1_NAND_TWBE(0x39) | \ 428 FTIM1_NAND_TRR(0x0e) | \ 429 FTIM1_NAND_TRP(0x18)) 430 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 431 FTIM2_NAND_TREH(0x0a) | \ 432 FTIM2_NAND_TWHRE(0x1e)) 433 #define CONFIG_SYS_NAND_FTIM3 0x0 434 #endif 435 436 #define CONFIG_SYS_NAND_DDR_LAW 11 437 438 /* Set up IFC registers for boot location NOR/NAND */ 439 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 440 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 441 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 442 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 443 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 444 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 445 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 446 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 447 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 448 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 449 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 450 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 451 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 452 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 453 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 454 #else 455 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 456 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 457 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 458 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 459 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 460 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 461 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 462 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 463 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 464 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 465 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 466 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 467 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 468 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 469 #endif 470 471 /* CPLD on IFC */ 472 #define CONFIG_SYS_CPLD_BASE 0xffb00000 473 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 476 #else 477 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 478 #endif 479 480 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 481 | CSPR_PORT_SIZE_8 \ 482 | CSPR_MSEL_GPCM \ 483 | CSPR_V) 484 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 485 #define CONFIG_SYS_CSOR3 0x0 486 /* CPLD Timing parameters for IFC CS3 */ 487 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 488 FTIM0_GPCM_TEADC(0x0e) | \ 489 FTIM0_GPCM_TEAHC(0x0e)) 490 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 491 FTIM1_GPCM_TRAD(0x1f)) 492 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 493 FTIM2_GPCM_TCH(0x8) | \ 494 FTIM2_GPCM_TWP(0x1f)) 495 #define CONFIG_SYS_CS3_FTIM3 0x0 496 497 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 498 defined(CONFIG_RAMBOOT_NAND) 499 #define CONFIG_SYS_RAMBOOT 500 #define CONFIG_SYS_EXTRA_ENV_RELOC 501 #else 502 #undef CONFIG_SYS_RAMBOOT 503 #endif 504 505 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 506 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 507 #define CONFIG_A003399_NOR_WORKAROUND 508 #endif 509 #endif 510 511 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 512 #define CONFIG_BOARD_EARLY_INIT_R 513 514 #define CONFIG_SYS_INIT_RAM_LOCK 515 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 516 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 517 518 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 519 - GENERATED_GBL_DATA_SIZE) 520 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 521 522 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 523 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 524 525 /* 526 * Config the L2 Cache as L2 SRAM 527 */ 528 #if defined(CONFIG_SPL_BUILD) 529 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 530 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 531 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 532 #define CONFIG_SYS_L2_SIZE (256 << 10) 533 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 534 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 535 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 536 #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) 537 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 538 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 539 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 540 #elif defined(CONFIG_NAND) 541 #ifdef CONFIG_TPL_BUILD 542 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 543 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 544 #define CONFIG_SYS_L2_SIZE (256 << 10) 545 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 546 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 547 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 548 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 549 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 550 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 551 #else 552 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 553 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 554 #define CONFIG_SYS_L2_SIZE (256 << 10) 555 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 556 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 557 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 558 #endif 559 #endif 560 #endif 561 562 /* Serial Port */ 563 #define CONFIG_CONS_INDEX 1 564 #undef CONFIG_SERIAL_SOFTWARE_FIFO 565 #define CONFIG_SYS_NS16550_SERIAL 566 #define CONFIG_SYS_NS16550_REG_SIZE 1 567 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 568 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 569 #define CONFIG_NS16550_MIN_FUNCTIONS 570 #endif 571 572 #define CONFIG_SYS_BAUDRATE_TABLE \ 573 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 574 575 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 576 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 577 578 /* I2C */ 579 #define CONFIG_SYS_I2C 580 #define CONFIG_SYS_I2C_FSL 581 #define CONFIG_SYS_FSL_I2C_SPEED 400000 582 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 583 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 584 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 585 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 586 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 587 #define I2C_PCA9557_ADDR1 0x18 588 #define I2C_PCA9557_ADDR2 0x19 589 #define I2C_PCA9557_BUS_NUM 0 590 591 /* I2C EEPROM */ 592 #if defined(CONFIG_TARGET_P1010RDB_PB) 593 #define CONFIG_ID_EEPROM 594 #ifdef CONFIG_ID_EEPROM 595 #define CONFIG_SYS_I2C_EEPROM_NXID 596 #endif 597 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 598 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 599 #define CONFIG_SYS_EEPROM_BUS_NUM 0 600 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 601 #endif 602 /* enable read and write access to EEPROM */ 603 #define CONFIG_CMD_EEPROM 604 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 605 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 606 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 607 608 /* RTC */ 609 #define CONFIG_RTC_PT7C4338 610 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 611 612 /* 613 * SPI interface will not be available in case of NAND boot SPI CS0 will be 614 * used for SLIC 615 */ 616 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 617 /* eSPI - Enhanced SPI */ 618 #define CONFIG_SF_DEFAULT_SPEED 10000000 619 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 620 #endif 621 622 #if defined(CONFIG_TSEC_ENET) 623 #define CONFIG_MII /* MII PHY management */ 624 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 625 #define CONFIG_TSEC1 1 626 #define CONFIG_TSEC1_NAME "eTSEC1" 627 #define CONFIG_TSEC2 1 628 #define CONFIG_TSEC2_NAME "eTSEC2" 629 #define CONFIG_TSEC3 1 630 #define CONFIG_TSEC3_NAME "eTSEC3" 631 632 #define TSEC1_PHY_ADDR 1 633 #define TSEC2_PHY_ADDR 0 634 #define TSEC3_PHY_ADDR 2 635 636 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 637 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 638 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 639 640 #define TSEC1_PHYIDX 0 641 #define TSEC2_PHYIDX 0 642 #define TSEC3_PHYIDX 0 643 644 #define CONFIG_ETHPRIME "eTSEC1" 645 646 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 647 648 /* TBI PHY configuration for SGMII mode */ 649 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 650 TBICR_PHY_RESET \ 651 | TBICR_ANEG_ENABLE \ 652 | TBICR_FULL_DUPLEX \ 653 | TBICR_SPEED1_SET \ 654 ) 655 656 #endif /* CONFIG_TSEC_ENET */ 657 658 /* SATA */ 659 #define CONFIG_FSL_SATA 660 #define CONFIG_FSL_SATA_V2 661 #define CONFIG_LIBATA 662 663 #ifdef CONFIG_FSL_SATA 664 #define CONFIG_SYS_SATA_MAX_DEVICE 2 665 #define CONFIG_SATA1 666 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 667 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 668 #define CONFIG_SATA2 669 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 670 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 671 672 #define CONFIG_CMD_SATA 673 #define CONFIG_LBA48 674 #endif /* #ifdef CONFIG_FSL_SATA */ 675 676 #define CONFIG_MMC 677 #ifdef CONFIG_MMC 678 #define CONFIG_DOS_PARTITION 679 #define CONFIG_FSL_ESDHC 680 #define CONFIG_GENERIC_MMC 681 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 682 #endif 683 684 #define CONFIG_HAS_FSL_DR_USB 685 686 #if defined(CONFIG_HAS_FSL_DR_USB) 687 #define CONFIG_USB_EHCI 688 689 #ifdef CONFIG_USB_EHCI 690 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 691 #define CONFIG_USB_EHCI_FSL 692 #endif 693 #endif 694 695 /* 696 * Environment 697 */ 698 #if defined(CONFIG_SDCARD) 699 #define CONFIG_ENV_IS_IN_MMC 700 #define CONFIG_FSL_FIXED_MMC_LOCATION 701 #define CONFIG_SYS_MMC_ENV_DEV 0 702 #define CONFIG_ENV_SIZE 0x2000 703 #elif defined(CONFIG_SPIFLASH) 704 #define CONFIG_ENV_IS_IN_SPI_FLASH 705 #define CONFIG_ENV_SPI_BUS 0 706 #define CONFIG_ENV_SPI_CS 0 707 #define CONFIG_ENV_SPI_MAX_HZ 10000000 708 #define CONFIG_ENV_SPI_MODE 0 709 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 710 #define CONFIG_ENV_SECT_SIZE 0x10000 711 #define CONFIG_ENV_SIZE 0x2000 712 #elif defined(CONFIG_NAND) 713 #define CONFIG_ENV_IS_IN_NAND 714 #ifdef CONFIG_TPL_BUILD 715 #define CONFIG_ENV_SIZE 0x2000 716 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 717 #else 718 #if defined(CONFIG_TARGET_P1010RDB_PA) 719 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 720 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 721 #elif defined(CONFIG_TARGET_P1010RDB_PB) 722 #define CONFIG_ENV_SIZE (16 * 1024) 723 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 724 #endif 725 #endif 726 #define CONFIG_ENV_OFFSET (1024 * 1024) 727 #elif defined(CONFIG_SYS_RAMBOOT) 728 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 729 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 730 #define CONFIG_ENV_SIZE 0x2000 731 #else 732 #define CONFIG_ENV_IS_IN_FLASH 733 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 734 #define CONFIG_ENV_SIZE 0x2000 735 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 736 #endif 737 738 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 739 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 740 741 /* 742 * Command line configuration. 743 */ 744 #define CONFIG_CMD_DATE 745 #define CONFIG_CMD_ERRATA 746 #define CONFIG_CMD_IRQ 747 #define CONFIG_CMD_REGINFO 748 749 #undef CONFIG_WATCHDOG /* watchdog disabled */ 750 751 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ 752 || defined(CONFIG_FSL_SATA) 753 #define CONFIG_DOS_PARTITION 754 #endif 755 756 /* Hash command with SHA acceleration supported in hardware */ 757 #ifdef CONFIG_FSL_CAAM 758 #define CONFIG_CMD_HASH 759 #define CONFIG_SHA_HW_ACCEL 760 #endif 761 762 /* 763 * Miscellaneous configurable options 764 */ 765 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 766 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 767 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 768 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 769 770 #if defined(CONFIG_CMD_KGDB) 771 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 772 #else 773 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 774 #endif 775 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 776 /* Print Buffer Size */ 777 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 778 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 779 780 /* 781 * For booting Linux, the board info and command line data 782 * have to be in the first 64 MB of memory, since this is 783 * the maximum mapped by the Linux kernel during initialization. 784 */ 785 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 786 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 787 788 #if defined(CONFIG_CMD_KGDB) 789 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 790 #endif 791 792 /* 793 * Environment Configuration 794 */ 795 796 #if defined(CONFIG_TSEC_ENET) 797 #define CONFIG_HAS_ETH0 798 #define CONFIG_HAS_ETH1 799 #define CONFIG_HAS_ETH2 800 #endif 801 802 #define CONFIG_ROOTPATH "/opt/nfsroot" 803 #define CONFIG_BOOTFILE "uImage" 804 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 805 806 /* default location for tftp and bootm */ 807 #define CONFIG_LOADADDR 1000000 808 809 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 810 811 #define CONFIG_BAUDRATE 115200 812 813 #define CONFIG_EXTRA_ENV_SETTINGS \ 814 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 815 "netdev=eth0\0" \ 816 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 817 "loadaddr=1000000\0" \ 818 "consoledev=ttyS0\0" \ 819 "ramdiskaddr=2000000\0" \ 820 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 821 "fdtaddr=1e00000\0" \ 822 "fdtfile=p1010rdb.dtb\0" \ 823 "bdev=sda1\0" \ 824 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 825 "othbootargs=ramdisk_size=600000\0" \ 826 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 827 "console=$consoledev,$baudrate $othbootargs; " \ 828 "usb start;" \ 829 "fatload usb 0:2 $loadaddr $bootfile;" \ 830 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 831 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 832 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 833 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 834 "console=$consoledev,$baudrate $othbootargs; " \ 835 "usb start;" \ 836 "ext2load usb 0:4 $loadaddr $bootfile;" \ 837 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 838 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 839 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 840 CONFIG_BOOTMODE 841 842 #if defined(CONFIG_TARGET_P1010RDB_PA) 843 #define CONFIG_BOOTMODE \ 844 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 845 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 846 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 847 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 848 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 849 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 850 851 #elif defined(CONFIG_TARGET_P1010RDB_PB) 852 #define CONFIG_BOOTMODE \ 853 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 854 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 855 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 856 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 857 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 858 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 859 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 860 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 861 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 862 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 863 #endif 864 865 #define CONFIG_RAMBOOTCOMMAND \ 866 "setenv bootargs root=/dev/ram rw " \ 867 "console=$consoledev,$baudrate $othbootargs; " \ 868 "tftp $ramdiskaddr $ramdiskfile;" \ 869 "tftp $loadaddr $bootfile;" \ 870 "tftp $fdtaddr $fdtfile;" \ 871 "bootm $loadaddr $ramdiskaddr $fdtaddr" 872 873 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 874 875 #include <asm/fsl_secure_boot.h> 876 877 #endif /* __CONFIG_H */ 878