1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * P010 RDB board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/config_mpc85xx.h> 14 #define CONFIG_NAND_FSL_IFC 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_SPL_FLUSH_IMAGE 18 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 19 #define CONFIG_SPL_TEXT_BASE 0xD0001000 20 #define CONFIG_SPL_PAD_TO 0x18000 21 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 22 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 23 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 24 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 25 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 26 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 27 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 28 #define CONFIG_SPL_MMC_BOOT 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #endif 32 #endif 33 34 #ifdef CONFIG_SPIFLASH 35 #ifdef CONFIG_SECURE_BOOT 36 #define CONFIG_RAMBOOT_SPIFLASH 37 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 38 #else 39 #define CONFIG_SPL_SPI_FLASH_MINIMAL 40 #define CONFIG_SPL_FLUSH_IMAGE 41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 42 #define CONFIG_SPL_TEXT_BASE 0xD0001000 43 #define CONFIG_SPL_PAD_TO 0x18000 44 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 48 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 49 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 51 #define CONFIG_SPL_SPI_BOOT 52 #ifdef CONFIG_SPL_BUILD 53 #define CONFIG_SPL_COMMON_INIT_DDR 54 #endif 55 #endif 56 #endif 57 58 #ifdef CONFIG_NAND 59 #ifdef CONFIG_SECURE_BOOT 60 #define CONFIG_SPL_INIT_MINIMAL 61 #define CONFIG_SPL_NAND_BOOT 62 #define CONFIG_SPL_FLUSH_IMAGE 63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 64 65 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 66 #define CONFIG_SPL_MAX_SIZE 8192 67 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 68 #define CONFIG_SPL_RELOC_STACK 0x00100000 69 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 70 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 71 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 72 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 74 #else 75 #ifdef CONFIG_TPL_BUILD 76 #define CONFIG_SPL_NAND_BOOT 77 #define CONFIG_SPL_FLUSH_IMAGE 78 #define CONFIG_SPL_NAND_INIT 79 #define CONFIG_SPL_COMMON_INIT_DDR 80 #define CONFIG_SPL_MAX_SIZE (128 << 10) 81 #define CONFIG_TPL_TEXT_BASE 0xD0001000 82 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 83 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 84 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 85 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 86 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 87 #elif defined(CONFIG_SPL_BUILD) 88 #define CONFIG_SPL_INIT_MINIMAL 89 #define CONFIG_SPL_NAND_MINIMAL 90 #define CONFIG_SPL_FLUSH_IMAGE 91 #define CONFIG_SPL_TEXT_BASE 0xff800000 92 #define CONFIG_SPL_MAX_SIZE 8192 93 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 94 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 95 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 96 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 97 #endif 98 #define CONFIG_SPL_PAD_TO 0x20000 99 #define CONFIG_TPL_PAD_TO 0x20000 100 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 101 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 102 #endif 103 #endif 104 105 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 106 #define CONFIG_RAMBOOT_NAND 107 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 108 #endif 109 110 #ifndef CONFIG_RESET_VECTOR_ADDRESS 111 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 112 #endif 113 114 #ifdef CONFIG_TPL_BUILD 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE 116 #elif defined(CONFIG_SPL_BUILD) 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 118 #else 119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 120 #endif 121 122 /* High Level Configuration Options */ 123 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 124 125 #if defined(CONFIG_PCI) 126 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 127 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 128 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 129 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 130 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 131 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 132 133 /* 134 * PCI Windows 135 * Memory space is mapped 1-1, but I/O space must start from 0. 136 */ 137 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 138 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 139 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 142 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 143 #else 144 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 145 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 146 #endif 147 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 148 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 149 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 150 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 151 #ifdef CONFIG_PHYS_64BIT 152 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 153 #else 154 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 155 #endif 156 157 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 158 #if defined(CONFIG_TARGET_P1010RDB_PA) 159 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 160 #elif defined(CONFIG_TARGET_P1010RDB_PB) 161 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 162 #endif 163 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 164 #ifdef CONFIG_PHYS_64BIT 165 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 166 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 167 #else 168 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 169 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 170 #endif 171 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 172 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 173 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 174 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 175 #ifdef CONFIG_PHYS_64BIT 176 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 177 #else 178 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 179 #endif 180 181 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 182 #endif 183 184 #define CONFIG_ENV_OVERWRITE 185 186 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 187 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 188 189 #define CONFIG_HWCONFIG 190 /* 191 * These can be toggled for performance analysis, otherwise use default. 192 */ 193 #define CONFIG_L2_CACHE /* toggle L2 cache */ 194 #define CONFIG_BTB /* toggle branch predition */ 195 196 197 #define CONFIG_ENABLE_36BIT_PHYS 198 199 #ifdef CONFIG_PHYS_64BIT 200 #define CONFIG_ADDR_MAP 1 201 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 202 #endif 203 204 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 205 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 206 207 /* DDR Setup */ 208 #define CONFIG_SYS_DDR_RAW_TIMING 209 #define CONFIG_DDR_SPD 210 #define CONFIG_SYS_SPD_BUS_NUM 1 211 #define SPD_EEPROM_ADDRESS 0x52 212 213 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 214 215 #ifndef __ASSEMBLY__ 216 extern unsigned long get_sdram_size(void); 217 #endif 218 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 219 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 220 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 221 222 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 223 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 224 225 /* DDR3 Controller Settings */ 226 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 227 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 228 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 229 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 230 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 231 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 232 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 233 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 234 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 235 #define CONFIG_SYS_DDR_RCW_1 0x00000000 236 #define CONFIG_SYS_DDR_RCW_2 0x00000000 237 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 238 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 239 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 240 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 241 242 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 243 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 244 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 245 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 246 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 247 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 248 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 249 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 250 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 251 252 /* settings for DDR3 at 667MT/s */ 253 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 254 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 255 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 256 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 257 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 258 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 259 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 260 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 261 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 262 263 #define CONFIG_SYS_CCSRBAR 0xffe00000 264 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 265 266 /* Don't relocate CCSRBAR while in NAND_SPL */ 267 #ifdef CONFIG_SPL_BUILD 268 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 269 #endif 270 271 /* 272 * Memory map 273 * 274 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 275 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 276 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 277 * 278 * Localbus non-cacheable 279 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 280 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 281 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 282 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 283 */ 284 285 /* 286 * IFC Definitions 287 */ 288 /* NOR Flash on IFC */ 289 290 #define CONFIG_SYS_FLASH_BASE 0xee000000 291 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 292 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 295 #else 296 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 297 #endif 298 299 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 300 CSPR_PORT_SIZE_16 | \ 301 CSPR_MSEL_NOR | \ 302 CSPR_V) 303 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 304 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 305 /* NOR Flash Timing Params */ 306 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 307 FTIM0_NOR_TEADC(0x5) | \ 308 FTIM0_NOR_TEAHC(0x5) 309 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 310 FTIM1_NOR_TRAD_NOR(0x0f) 311 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 312 FTIM2_NOR_TCH(0x4) | \ 313 FTIM2_NOR_TWP(0x1c) 314 #define CONFIG_SYS_NOR_FTIM3 0x0 315 316 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 317 #define CONFIG_SYS_FLASH_QUIET_TEST 318 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 319 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 320 321 #undef CONFIG_SYS_FLASH_CHECKSUM 322 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 323 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 324 325 /* CFI for NOR Flash */ 326 #define CONFIG_SYS_FLASH_EMPTY_INFO 327 328 /* NAND Flash on IFC */ 329 #define CONFIG_SYS_NAND_BASE 0xff800000 330 #ifdef CONFIG_PHYS_64BIT 331 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 332 #else 333 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 334 #endif 335 336 #define CONFIG_MTD_PARTITION 337 338 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 339 | CSPR_PORT_SIZE_8 \ 340 | CSPR_MSEL_NAND \ 341 | CSPR_V) 342 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 343 344 #if defined(CONFIG_TARGET_P1010RDB_PA) 345 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 346 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 347 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 348 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 349 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 350 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 351 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 352 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 353 354 #elif defined(CONFIG_TARGET_P1010RDB_PB) 355 #define CONFIG_SYS_NAND_ONFI_DETECTION 356 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 357 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 358 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 359 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 360 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 361 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 362 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 363 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 364 #endif 365 366 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 367 #define CONFIG_SYS_MAX_NAND_DEVICE 1 368 369 #if defined(CONFIG_TARGET_P1010RDB_PA) 370 /* NAND Flash Timing Params */ 371 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 372 FTIM0_NAND_TWP(0x0C) | \ 373 FTIM0_NAND_TWCHT(0x04) | \ 374 FTIM0_NAND_TWH(0x05) 375 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 376 FTIM1_NAND_TWBE(0x1d) | \ 377 FTIM1_NAND_TRR(0x07) | \ 378 FTIM1_NAND_TRP(0x0c) 379 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 380 FTIM2_NAND_TREH(0x05) | \ 381 FTIM2_NAND_TWHRE(0x0f) 382 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 383 384 #elif defined(CONFIG_TARGET_P1010RDB_PB) 385 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 386 /* ONFI NAND Flash mode0 Timing Params */ 387 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 388 FTIM0_NAND_TWP(0x18) | \ 389 FTIM0_NAND_TWCHT(0x07) | \ 390 FTIM0_NAND_TWH(0x0a)) 391 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 392 FTIM1_NAND_TWBE(0x39) | \ 393 FTIM1_NAND_TRR(0x0e) | \ 394 FTIM1_NAND_TRP(0x18)) 395 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 396 FTIM2_NAND_TREH(0x0a) | \ 397 FTIM2_NAND_TWHRE(0x1e)) 398 #define CONFIG_SYS_NAND_FTIM3 0x0 399 #endif 400 401 #define CONFIG_SYS_NAND_DDR_LAW 11 402 403 /* Set up IFC registers for boot location NOR/NAND */ 404 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 405 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 406 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 407 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 408 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 409 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 410 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 411 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 412 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 413 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 414 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 415 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 416 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 417 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 418 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 419 #else 420 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 421 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 422 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 423 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 424 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 425 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 426 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 427 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 428 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 429 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 430 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 431 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 432 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 433 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 434 #endif 435 436 /* CPLD on IFC */ 437 #define CONFIG_SYS_CPLD_BASE 0xffb00000 438 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 441 #else 442 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 443 #endif 444 445 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 446 | CSPR_PORT_SIZE_8 \ 447 | CSPR_MSEL_GPCM \ 448 | CSPR_V) 449 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 450 #define CONFIG_SYS_CSOR3 0x0 451 /* CPLD Timing parameters for IFC CS3 */ 452 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 453 FTIM0_GPCM_TEADC(0x0e) | \ 454 FTIM0_GPCM_TEAHC(0x0e)) 455 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 456 FTIM1_GPCM_TRAD(0x1f)) 457 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 458 FTIM2_GPCM_TCH(0x8) | \ 459 FTIM2_GPCM_TWP(0x1f)) 460 #define CONFIG_SYS_CS3_FTIM3 0x0 461 462 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 463 defined(CONFIG_RAMBOOT_NAND) 464 #define CONFIG_SYS_RAMBOOT 465 #else 466 #undef CONFIG_SYS_RAMBOOT 467 #endif 468 469 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 470 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 471 #define CONFIG_A003399_NOR_WORKAROUND 472 #endif 473 #endif 474 475 #define CONFIG_SYS_INIT_RAM_LOCK 476 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 477 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 478 479 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 480 - GENERATED_GBL_DATA_SIZE) 481 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 482 483 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 484 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 485 486 /* 487 * Config the L2 Cache as L2 SRAM 488 */ 489 #if defined(CONFIG_SPL_BUILD) 490 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 491 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 492 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 493 #define CONFIG_SYS_L2_SIZE (256 << 10) 494 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 495 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 496 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 497 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 498 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 499 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 500 #elif defined(CONFIG_NAND) 501 #ifdef CONFIG_TPL_BUILD 502 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 503 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 504 #define CONFIG_SYS_L2_SIZE (256 << 10) 505 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 506 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 507 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 508 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 509 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 510 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 511 #else 512 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 513 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 514 #define CONFIG_SYS_L2_SIZE (256 << 10) 515 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 516 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 517 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 518 #endif 519 #endif 520 #endif 521 522 /* Serial Port */ 523 #undef CONFIG_SERIAL_SOFTWARE_FIFO 524 #define CONFIG_SYS_NS16550_SERIAL 525 #define CONFIG_SYS_NS16550_REG_SIZE 1 526 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 527 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 528 #define CONFIG_NS16550_MIN_FUNCTIONS 529 #endif 530 531 #define CONFIG_SYS_BAUDRATE_TABLE \ 532 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 533 534 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 535 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 536 537 /* I2C */ 538 #define CONFIG_SYS_I2C 539 #define CONFIG_SYS_I2C_FSL 540 #define CONFIG_SYS_FSL_I2C_SPEED 400000 541 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 542 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 543 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 544 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 545 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 546 #define I2C_PCA9557_ADDR1 0x18 547 #define I2C_PCA9557_ADDR2 0x19 548 #define I2C_PCA9557_BUS_NUM 0 549 550 /* I2C EEPROM */ 551 #if defined(CONFIG_TARGET_P1010RDB_PB) 552 #define CONFIG_ID_EEPROM 553 #ifdef CONFIG_ID_EEPROM 554 #define CONFIG_SYS_I2C_EEPROM_NXID 555 #endif 556 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 557 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 558 #define CONFIG_SYS_EEPROM_BUS_NUM 0 559 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 560 #endif 561 /* enable read and write access to EEPROM */ 562 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 563 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 564 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 565 566 /* RTC */ 567 #define CONFIG_RTC_PT7C4338 568 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 569 570 /* 571 * SPI interface will not be available in case of NAND boot SPI CS0 will be 572 * used for SLIC 573 */ 574 #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) 575 /* eSPI - Enhanced SPI */ 576 #endif 577 578 #if defined(CONFIG_TSEC_ENET) 579 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 580 #define CONFIG_TSEC1 1 581 #define CONFIG_TSEC1_NAME "eTSEC1" 582 #define CONFIG_TSEC2 1 583 #define CONFIG_TSEC2_NAME "eTSEC2" 584 #define CONFIG_TSEC3 1 585 #define CONFIG_TSEC3_NAME "eTSEC3" 586 587 #define TSEC1_PHY_ADDR 1 588 #define TSEC2_PHY_ADDR 0 589 #define TSEC3_PHY_ADDR 2 590 591 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 592 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 593 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 594 595 #define TSEC1_PHYIDX 0 596 #define TSEC2_PHYIDX 0 597 #define TSEC3_PHYIDX 0 598 599 #define CONFIG_ETHPRIME "eTSEC1" 600 601 /* TBI PHY configuration for SGMII mode */ 602 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 603 TBICR_PHY_RESET \ 604 | TBICR_ANEG_ENABLE \ 605 | TBICR_FULL_DUPLEX \ 606 | TBICR_SPEED1_SET \ 607 ) 608 609 #endif /* CONFIG_TSEC_ENET */ 610 611 /* SATA */ 612 #define CONFIG_FSL_SATA_V2 613 614 #ifdef CONFIG_FSL_SATA 615 #define CONFIG_SYS_SATA_MAX_DEVICE 2 616 #define CONFIG_SATA1 617 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 618 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 619 #define CONFIG_SATA2 620 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 621 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 622 623 #define CONFIG_LBA48 624 #endif /* #ifdef CONFIG_FSL_SATA */ 625 626 #ifdef CONFIG_MMC 627 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 628 #endif 629 630 #define CONFIG_HAS_FSL_DR_USB 631 632 #if defined(CONFIG_HAS_FSL_DR_USB) 633 #ifdef CONFIG_USB_EHCI_HCD 634 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 635 #define CONFIG_USB_EHCI_FSL 636 #endif 637 #endif 638 639 /* 640 * Environment 641 */ 642 #if defined(CONFIG_SDCARD) 643 #define CONFIG_FSL_FIXED_MMC_LOCATION 644 #define CONFIG_SYS_MMC_ENV_DEV 0 645 #define CONFIG_ENV_SIZE 0x2000 646 #elif defined(CONFIG_SPIFLASH) 647 #define CONFIG_ENV_SPI_BUS 0 648 #define CONFIG_ENV_SPI_CS 0 649 #define CONFIG_ENV_SPI_MAX_HZ 10000000 650 #define CONFIG_ENV_SPI_MODE 0 651 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 652 #define CONFIG_ENV_SECT_SIZE 0x10000 653 #define CONFIG_ENV_SIZE 0x2000 654 #elif defined(CONFIG_NAND) 655 #ifdef CONFIG_TPL_BUILD 656 #define CONFIG_ENV_SIZE 0x2000 657 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 658 #else 659 #if defined(CONFIG_TARGET_P1010RDB_PA) 660 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 661 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 662 #elif defined(CONFIG_TARGET_P1010RDB_PB) 663 #define CONFIG_ENV_SIZE (16 * 1024) 664 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 665 #endif 666 #endif 667 #define CONFIG_ENV_OFFSET (1024 * 1024) 668 #elif defined(CONFIG_SYS_RAMBOOT) 669 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 670 #define CONFIG_ENV_SIZE 0x2000 671 #else 672 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 673 #define CONFIG_ENV_SIZE 0x2000 674 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 675 #endif 676 677 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 678 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 679 680 #undef CONFIG_WATCHDOG /* watchdog disabled */ 681 682 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ 683 || defined(CONFIG_FSL_SATA) 684 #endif 685 686 /* 687 * Miscellaneous configurable options 688 */ 689 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 690 691 /* 692 * For booting Linux, the board info and command line data 693 * have to be in the first 64 MB of memory, since this is 694 * the maximum mapped by the Linux kernel during initialization. 695 */ 696 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 697 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 698 699 #if defined(CONFIG_CMD_KGDB) 700 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 701 #endif 702 703 /* 704 * Environment Configuration 705 */ 706 707 #if defined(CONFIG_TSEC_ENET) 708 #define CONFIG_HAS_ETH0 709 #define CONFIG_HAS_ETH1 710 #define CONFIG_HAS_ETH2 711 #endif 712 713 #define CONFIG_ROOTPATH "/opt/nfsroot" 714 #define CONFIG_BOOTFILE "uImage" 715 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 716 717 /* default location for tftp and bootm */ 718 #define CONFIG_LOADADDR 1000000 719 720 #define CONFIG_EXTRA_ENV_SETTINGS \ 721 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 722 "netdev=eth0\0" \ 723 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 724 "loadaddr=1000000\0" \ 725 "consoledev=ttyS0\0" \ 726 "ramdiskaddr=2000000\0" \ 727 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 728 "fdtaddr=1e00000\0" \ 729 "fdtfile=p1010rdb.dtb\0" \ 730 "bdev=sda1\0" \ 731 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 732 "othbootargs=ramdisk_size=600000\0" \ 733 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 734 "console=$consoledev,$baudrate $othbootargs; " \ 735 "usb start;" \ 736 "fatload usb 0:2 $loadaddr $bootfile;" \ 737 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 738 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 739 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 740 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 741 "console=$consoledev,$baudrate $othbootargs; " \ 742 "usb start;" \ 743 "ext2load usb 0:4 $loadaddr $bootfile;" \ 744 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 745 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 746 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 747 CONFIG_BOOTMODE 748 749 #if defined(CONFIG_TARGET_P1010RDB_PA) 750 #define CONFIG_BOOTMODE \ 751 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 752 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 753 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 754 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 755 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 756 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 757 758 #elif defined(CONFIG_TARGET_P1010RDB_PB) 759 #define CONFIG_BOOTMODE \ 760 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 761 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 762 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 763 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 764 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 765 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 766 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 767 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 768 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 769 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 770 #endif 771 772 #define CONFIG_RAMBOOTCOMMAND \ 773 "setenv bootargs root=/dev/ram rw " \ 774 "console=$consoledev,$baudrate $othbootargs; " \ 775 "tftp $ramdiskaddr $ramdiskfile;" \ 776 "tftp $loadaddr $bootfile;" \ 777 "tftp $fdtaddr $fdtfile;" \ 778 "bootm $loadaddr $ramdiskaddr $fdtaddr" 779 780 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 781 782 #include <asm/fsl_secure_boot.h> 783 784 #endif /* __CONFIG_H */ 785