1 /* 2 * Configuation settings for the Renesas Solutions Migo-R board 3 * 4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __MIGO_R_H 10 #define __MIGO_R_H 11 12 #define CONFIG_CPU_SH7722 1 13 #define CONFIG_MIGO_R 1 14 15 #define CONFIG_CMD_SDRAM 16 17 #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" 18 19 #define CONFIG_DISPLAY_BOARDINFO 20 #undef CONFIG_SHOW_BOOT_PROGRESS 21 22 /* SMC9111 */ 23 #define CONFIG_SMC91111 24 #define CONFIG_SMC91111_BASE (0xB0000000) 25 26 /* MEMORY */ 27 #define MIGO_R_SDRAM_BASE (0x8C000000) 28 #define MIGO_R_FLASH_BASE_1 (0xA0000000) 29 #define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) 30 31 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 32 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 33 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ 34 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 35 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ 36 #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ 37 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ 38 39 /* SCIF */ 40 #define CONFIG_CONS_SCIF0 1 41 42 #define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) 43 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 44 45 /* Enable alternate, more extensive, memory test */ 46 #undef CONFIG_SYS_ALT_MEMTEST 47 /* Scratch address used by the alternate memory test */ 48 #undef CONFIG_SYS_MEMTEST_SCRATCH 49 50 /* Enable temporary baudrate change while serial download */ 51 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 52 53 #define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) 54 /* maybe more, but if so u-boot doesn't know about it... */ 55 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 56 /* default load address for scripts ?!? */ 57 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 58 59 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 60 #define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) 61 /* Monitor size */ 62 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 63 /* Size of DRAM reserved for malloc() use */ 64 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 65 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 66 67 /* FLASH */ 68 #define CONFIG_SYS_FLASH_CFI 69 #define CONFIG_FLASH_CFI_DRIVER 70 #undef CONFIG_SYS_FLASH_QUIET_TEST 71 /* print 'E' for empty sector on flinfo */ 72 #define CONFIG_SYS_FLASH_EMPTY_INFO 73 /* Physical start address of Flash memory */ 74 #define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) 75 /* Max number of sectors on each Flash chip */ 76 #define CONFIG_SYS_MAX_FLASH_SECT 512 77 78 /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ 79 #define CONFIG_SYS_MAX_FLASH_BANKS 1 80 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } 81 82 /* Timeout for Flash erase operations (in ms) */ 83 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 84 /* Timeout for Flash write operations (in ms) */ 85 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 86 /* Timeout for Flash set sector lock bit operations (in ms) */ 87 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 88 /* Timeout for Flash clear lock bit operations (in ms) */ 89 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 90 91 /* Use hardware flash sectors protection instead of U-Boot software protection */ 92 #undef CONFIG_SYS_FLASH_PROTECTION 93 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 94 95 /* ENV setting */ 96 #define CONFIG_ENV_OVERWRITE 1 97 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 98 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 99 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 100 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 101 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 102 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 103 104 /* Board Clock */ 105 #define CONFIG_SYS_CLK_FREQ 33333333 106 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 107 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 108 #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ 109 110 #endif /* __MIGO_R_H */ 111