1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ 42 43 #ifdef RUN_DIAG 44 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 45 #endif 46 47 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 48 49 /* 50 * virtual address to be used for temporary mappings. There 51 * should be 128k free at this VA. 52 */ 53 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 54 55 /* 56 * set this to enable Rapid IO. PCI and RIO are mutually exclusive 57 */ 58 /*#define CONFIG_RIO 1*/ 59 60 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ 61 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 62 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ 63 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ 64 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 65 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 66 #endif 67 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 68 69 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 70 #define CONFIG_ENV_OVERWRITE 71 72 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 73 74 #define CONFIG_ALTIVEC 1 75 76 /* 77 * L2CR setup -- make sure this is right for your board! 78 */ 79 #define CONFIG_SYS_L2 80 #define L2_INIT 0 81 #define L2_ENABLE (L2CR_L2E) 82 83 #ifndef CONFIG_SYS_CLK_FREQ 84 #ifndef __ASSEMBLY__ 85 extern unsigned long get_board_sys_clk(unsigned long dummy); 86 #endif 87 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 88 #endif 89 90 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 91 92 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 93 #define CONFIG_SYS_MEMTEST_END 0x00400000 94 95 /* 96 * With the exception of PCI Memory and Rapid IO, most devices will simply 97 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 98 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 99 */ 100 #ifdef CONFIG_PHYS_64BIT 101 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL 102 #else 103 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 104 #endif 105 106 /* 107 * Base addresses -- Note these are effective addresses where the 108 * actual resources get mapped (not physical addresses) 109 */ 110 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 111 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 112 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 113 114 /* Physical addresses */ 115 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 118 #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 119 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) 120 #else 121 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 122 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 123 #endif 124 125 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 126 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 127 128 /* 129 * DDR Setup 130 */ 131 #define CONFIG_FSL_DDR2 132 #undef CONFIG_FSL_DDR_INTERACTIVE 133 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 134 #define CONFIG_DDR_SPD 135 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 137 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 138 139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 140 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 141 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 142 #define CONFIG_VERY_BIG_RAM 143 144 #define MPC86xx_DDR_SDRAM_CLK_CNTL 145 146 #define CONFIG_NUM_DDR_CONTROLLERS 2 147 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 148 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 149 150 /* 151 * I2C addresses of SPD EEPROMs 152 */ 153 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 154 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 155 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 156 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 157 158 159 /* 160 * These are used when DDR doesn't use SPD. 161 */ 162 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 163 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 164 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 165 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 166 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 167 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 168 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 169 #define CONFIG_SYS_DDR_MODE_1 0x00480432 170 #define CONFIG_SYS_DDR_MODE_2 0x00000000 171 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 172 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 173 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 174 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 175 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 176 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 177 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 178 179 #define CONFIG_ID_EEPROM 180 #define CONFIG_SYS_I2C_EEPROM_NXID 181 #define CONFIG_ID_EEPROM 182 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 184 185 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 186 #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ 187 | CONFIG_SYS_PHYS_ADDR_HIGH) 188 189 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} 190 191 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 192 | 0x00001001) /* port size 16bit */ 193 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 194 195 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 196 | 0x00001001) /* port size 16bit */ 197 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 198 199 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 200 | 0x00000801) /* port size 8bit */ 201 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 202 203 /* 204 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 205 * The PIXIS and CF by themselves aren't large enough to take up the 128k 206 * required for the smallest BAT mapping, so there's a 64k hole. 207 */ 208 #define CONFIG_SYS_LBC_BASE 0xffde0000 209 #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ 210 | CONFIG_SYS_PHYS_ADDR_HIGH) 211 212 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 213 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 214 #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) 215 #define PIXIS_SIZE 0x00008000 /* 32k */ 216 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 217 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 218 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 219 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 220 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 221 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 222 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 223 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 224 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 225 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 226 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 227 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 228 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 229 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 230 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 231 232 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 233 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 234 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 235 236 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 237 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 238 239 #undef CONFIG_SYS_FLASH_CHECKSUM 240 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 241 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 242 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 243 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 244 245 #define CONFIG_FLASH_CFI_DRIVER 246 #define CONFIG_SYS_FLASH_CFI 247 #define CONFIG_SYS_FLASH_EMPTY_INFO 248 249 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 250 #define CONFIG_SYS_RAMBOOT 251 #else 252 #undef CONFIG_SYS_RAMBOOT 253 #endif 254 255 #if defined(CONFIG_SYS_RAMBOOT) 256 #undef CONFIG_SPD_EEPROM 257 #define CONFIG_SYS_SDRAM_SIZE 256 258 #endif 259 260 #undef CONFIG_CLOCKS_IN_MHZ 261 262 #define CONFIG_SYS_INIT_RAM_LOCK 1 263 #ifndef CONFIG_SYS_INIT_RAM_LOCK 264 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 265 #else 266 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 267 #endif 268 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 269 270 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 271 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 272 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 273 274 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 275 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 276 277 /* Serial Port */ 278 #define CONFIG_CONS_INDEX 1 279 #undef CONFIG_SERIAL_SOFTWARE_FIFO 280 #define CONFIG_SYS_NS16550 281 #define CONFIG_SYS_NS16550_SERIAL 282 #define CONFIG_SYS_NS16550_REG_SIZE 1 283 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 284 285 #define CONFIG_SYS_BAUDRATE_TABLE \ 286 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 287 288 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 289 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 290 291 /* Use the HUSH parser */ 292 #define CONFIG_SYS_HUSH_PARSER 293 #ifdef CONFIG_SYS_HUSH_PARSER 294 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 295 #endif 296 297 /* 298 * Pass open firmware flat tree to kernel 299 */ 300 #define CONFIG_OF_LIBFDT 1 301 #define CONFIG_OF_BOARD_SETUP 1 302 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 303 304 305 #define CONFIG_SYS_64BIT_VSPRINTF 1 306 #define CONFIG_SYS_64BIT_STRTOUL 1 307 308 /* 309 * I2C 310 */ 311 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 312 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 313 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 314 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 315 #define CONFIG_SYS_I2C_SLAVE 0x7F 316 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 317 #define CONFIG_SYS_I2C_OFFSET 0x3100 318 319 /* 320 * RapidIO MMU 321 */ 322 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ 323 #ifdef CONFIG_PHYS_64BIT 324 #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL 325 #else 326 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 327 #endif 328 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 329 330 /* 331 * General PCI 332 * Addresses are mapped 1-1. 333 */ 334 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 335 #ifdef CONFIG_PHYS_64BIT 336 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL 337 #else 338 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 339 #endif 340 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 341 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 342 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 343 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ 344 | CONFIG_SYS_PHYS_ADDR_HIGH) 345 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ 346 347 /* For RTL8139 */ 348 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 349 #define _IO_BASE 0x00000000 350 351 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \ 352 + CONFIG_SYS_PCI1_MEM_SIZE) 353 #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ 354 + CONFIG_SYS_PCI1_MEM_SIZE) 355 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 356 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 357 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ 358 + CONFIG_SYS_PCI1_IO_SIZE) 359 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ 360 + CONFIG_SYS_PCI1_IO_SIZE) 361 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE 362 363 #if defined(CONFIG_PCI) 364 365 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 366 367 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 368 369 #define CONFIG_NET_MULTI 370 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 371 372 #define CONFIG_RTL8139 373 374 #undef CONFIG_EEPRO100 375 #undef CONFIG_TULIP 376 377 /************************************************************ 378 * USB support 379 ************************************************************/ 380 #define CONFIG_PCI_OHCI 1 381 #define CONFIG_USB_OHCI_NEW 1 382 #define CONFIG_USB_KEYBOARD 1 383 #define CONFIG_SYS_DEVICE_DEREGISTER 384 #define CONFIG_SYS_USB_EVENT_POLL 1 385 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 386 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 387 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 388 389 /*PCIE video card used*/ 390 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT 391 392 /*PCI video card used*/ 393 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 394 395 /* video */ 396 #define CONFIG_VIDEO 397 398 #if defined(CONFIG_VIDEO) 399 #define CONFIG_BIOSEMU 400 #define CONFIG_CFB_CONSOLE 401 #define CONFIG_VIDEO_SW_CURSOR 402 #define CONFIG_VGA_AS_SINGLE_DEVICE 403 #define CONFIG_ATI_RADEON_FB 404 #define CONFIG_VIDEO_LOGO 405 /*#define CONFIG_CONSOLE_CURSOR*/ 406 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT 407 #endif 408 409 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 410 411 #define CONFIG_DOS_PARTITION 412 #define CONFIG_SCSI_AHCI 413 414 #ifdef CONFIG_SCSI_AHCI 415 #define CONFIG_SATA_ULI5288 416 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 417 #define CONFIG_SYS_SCSI_MAX_LUN 1 418 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 419 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 420 #endif 421 422 #define CONFIG_MPC86XX_PCI2 423 424 #endif /* CONFIG_PCI */ 425 426 #if defined(CONFIG_TSEC_ENET) 427 428 #ifndef CONFIG_NET_MULTI 429 #define CONFIG_NET_MULTI 1 430 #endif 431 432 #define CONFIG_MII 1 /* MII PHY management */ 433 434 #define CONFIG_TSEC1 1 435 #define CONFIG_TSEC1_NAME "eTSEC1" 436 #define CONFIG_TSEC2 1 437 #define CONFIG_TSEC2_NAME "eTSEC2" 438 #define CONFIG_TSEC3 1 439 #define CONFIG_TSEC3_NAME "eTSEC3" 440 #define CONFIG_TSEC4 1 441 #define CONFIG_TSEC4_NAME "eTSEC4" 442 443 #define TSEC1_PHY_ADDR 0 444 #define TSEC2_PHY_ADDR 1 445 #define TSEC3_PHY_ADDR 2 446 #define TSEC4_PHY_ADDR 3 447 #define TSEC1_PHYIDX 0 448 #define TSEC2_PHYIDX 0 449 #define TSEC3_PHYIDX 0 450 #define TSEC4_PHYIDX 0 451 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 452 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 453 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 454 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 455 456 #define CONFIG_ETHPRIME "eTSEC1" 457 458 #endif /* CONFIG_TSEC_ENET */ 459 460 /* Contort an addr into the format needed for BATs */ 461 #ifdef CONFIG_PHYS_64BIT 462 #define BAT_PHYS_ADDR(x) ((unsigned long) \ 463 ((x & 0x00000000ffffffffULL) | \ 464 ((x & 0x0000000e00000000ULL) >> 24) | \ 465 ((x & 0x0000000100000000ULL) >> 30))) 466 #else 467 #define BAT_PHYS_ADDR(x) (x) 468 #endif 469 470 471 /* Put high physical address bits into the BAT format */ 472 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 473 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 474 475 /* 476 * BAT0 DDR 477 */ 478 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 479 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 480 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 481 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 482 483 /* 484 * BAT1 LBC (PIXIS/CF) 485 */ 486 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 487 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 488 BATL_GUARDEDSTORAGE) 489 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 490 | BATU_VS | BATU_VP) 491 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 492 | BATL_PP_RW | BATL_MEMCOHERENCE) 493 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 494 495 /* if CONFIG_PCI: 496 * BAT2 PCI1 and PCI1 MEM 497 * if CONFIG_RIO 498 * BAT2 Rapidio Memory 499 */ 500 #ifdef CONFIG_PCI 501 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ 502 | BATL_PP_RW | BATL_CACHEINHIBIT \ 503 | BATL_GUARDEDSTORAGE) 504 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \ 505 | BATU_VS | BATU_VP) 506 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ 507 | BATL_PP_RW | BATL_CACHEINHIBIT) 508 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 509 #else /* CONFIG_RIO */ 510 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 511 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 512 BATL_GUARDEDSTORAGE) 513 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ 514 | BATU_VS | BATU_VP) 515 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 516 | BATL_PP_RW | BATL_CACHEINHIBIT) 517 518 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ 519 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 520 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 521 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 522 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 523 #endif 524 525 /* 526 * BAT3 CCSR Space 527 * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs 528 * instead. The assembler chokes on ULL. 529 */ 530 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 531 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 532 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 533 | BATL_PP_RW | BATL_CACHEINHIBIT \ 534 | BATL_GUARDEDSTORAGE) 535 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 536 | BATU_VP) 537 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 538 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 539 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 540 | BATL_PP_RW | BATL_CACHEINHIBIT) 541 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 542 543 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 544 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 545 | BATL_PP_RW | BATL_CACHEINHIBIT \ 546 | BATL_GUARDEDSTORAGE) 547 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 548 | BATU_BL_1M | BATU_VS | BATU_VP) 549 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 550 | BATL_PP_RW | BATL_CACHEINHIBIT) 551 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 552 #endif 553 554 /* 555 * BAT4 PCI1_IO and PCI2_IO 556 */ 557 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ 558 | BATL_PP_RW | BATL_CACHEINHIBIT \ 559 | BATL_GUARDEDSTORAGE) 560 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \ 561 | BATU_VS | BATU_VP) 562 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ 563 | BATL_PP_RW | BATL_CACHEINHIBIT) 564 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 565 566 /* 567 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 568 */ 569 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 570 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 571 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 572 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 573 574 /* 575 * BAT6 FLASH 576 */ 577 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 578 | BATL_PP_RW | BATL_CACHEINHIBIT \ 579 | BATL_GUARDEDSTORAGE) 580 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 581 | BATU_VP) 582 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 583 | BATL_PP_RW | BATL_MEMCOHERENCE) 584 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 585 586 /* Map the last 1M of flash where we're running from reset */ 587 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 588 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 589 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 590 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 591 | BATL_MEMCOHERENCE) 592 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 593 594 /* 595 * BAT7 FREE - used later for tmp mappings 596 */ 597 #define CONFIG_SYS_DBAT7L 0x00000000 598 #define CONFIG_SYS_DBAT7U 0x00000000 599 #define CONFIG_SYS_IBAT7L 0x00000000 600 #define CONFIG_SYS_IBAT7U 0x00000000 601 602 /* 603 * Environment 604 */ 605 #ifndef CONFIG_SYS_RAMBOOT 606 #define CONFIG_ENV_IS_IN_FLASH 1 607 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 608 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 609 #else 610 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 611 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 612 #endif 613 #define CONFIG_ENV_SIZE 0x2000 614 615 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 616 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 617 618 619 /* 620 * BOOTP options 621 */ 622 #define CONFIG_BOOTP_BOOTFILESIZE 623 #define CONFIG_BOOTP_BOOTPATH 624 #define CONFIG_BOOTP_GATEWAY 625 #define CONFIG_BOOTP_HOSTNAME 626 627 628 /* 629 * Command line configuration. 630 */ 631 #include <config_cmd_default.h> 632 633 #define CONFIG_CMD_PING 634 #define CONFIG_CMD_I2C 635 #define CONFIG_CMD_REGINFO 636 637 #if defined(CONFIG_SYS_RAMBOOT) 638 #undef CONFIG_CMD_ENV 639 #endif 640 641 #if defined(CONFIG_PCI) 642 #define CONFIG_CMD_PCI 643 #define CONFIG_CMD_SCSI 644 #define CONFIG_CMD_EXT2 645 #define CONFIG_CMD_USB 646 #endif 647 648 649 #undef CONFIG_WATCHDOG /* watchdog disabled */ 650 651 /* 652 * Miscellaneous configurable options 653 */ 654 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 655 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 656 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 657 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 658 659 #if defined(CONFIG_CMD_KGDB) 660 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 661 #else 662 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 663 #endif 664 665 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 666 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 667 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 668 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 669 670 /* 671 * For booting Linux, the board info and command line data 672 * have to be in the first 8 MB of memory, since this is 673 * the maximum mapped by the Linux kernel during initialization. 674 */ 675 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 676 677 /* 678 * Internal Definitions 679 * 680 * Boot Flags 681 */ 682 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 683 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 684 685 #if defined(CONFIG_CMD_KGDB) 686 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 687 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 688 #endif 689 690 /* 691 * Environment Configuration 692 */ 693 694 /* The mac addresses for all ethernet interface */ 695 #if defined(CONFIG_TSEC_ENET) 696 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 697 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 698 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 699 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 700 #endif 701 702 #define CONFIG_HAS_ETH0 1 703 #define CONFIG_HAS_ETH1 1 704 #define CONFIG_HAS_ETH2 1 705 #define CONFIG_HAS_ETH3 1 706 707 #define CONFIG_IPADDR 192.168.1.100 708 709 #define CONFIG_HOSTNAME unknown 710 #define CONFIG_ROOTPATH /opt/nfsroot 711 #define CONFIG_BOOTFILE uImage 712 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 713 714 #define CONFIG_SERVERIP 192.168.1.1 715 #define CONFIG_GATEWAYIP 192.168.1.1 716 #define CONFIG_NETMASK 255.255.255.0 717 718 /* default location for tftp and bootm */ 719 #define CONFIG_LOADADDR 1000000 720 721 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 722 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 723 724 #define CONFIG_BAUDRATE 115200 725 726 #define CONFIG_EXTRA_ENV_SETTINGS \ 727 "netdev=eth0\0" \ 728 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 729 "tftpflash=tftpboot $loadaddr $uboot; " \ 730 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 731 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 732 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 733 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 734 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 735 "consoledev=ttyS0\0" \ 736 "ramdiskaddr=2000000\0" \ 737 "ramdiskfile=your.ramdisk.u-boot\0" \ 738 "fdtaddr=c00000\0" \ 739 "fdtfile=mpc8641_hpcn.dtb\0" \ 740 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 741 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 742 "maxcpus=2" 743 744 745 #define CONFIG_NFSBOOTCOMMAND \ 746 "setenv bootargs root=/dev/nfs rw " \ 747 "nfsroot=$serverip:$rootpath " \ 748 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 749 "console=$consoledev,$baudrate $othbootargs;" \ 750 "tftp $loadaddr $bootfile;" \ 751 "tftp $fdtaddr $fdtfile;" \ 752 "bootm $loadaddr - $fdtaddr" 753 754 #define CONFIG_RAMBOOTCOMMAND \ 755 "setenv bootargs root=/dev/ram rw " \ 756 "console=$consoledev,$baudrate $othbootargs;" \ 757 "tftp $ramdiskaddr $ramdiskfile;" \ 758 "tftp $loadaddr $bootfile;" \ 759 "tftp $fdtaddr $fdtfile;" \ 760 "bootm $loadaddr $ramdiskaddr $fdtaddr" 761 762 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 763 764 #endif /* __CONFIG_H */ 765