1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * MPC8641HPCN board configuration file 11 * 12 * Make sure you change the MAC address and other network params first, 13 * search for CONFIG_SERVERIP, etc. in this file. 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MP 1 /* support multiple processors */ 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 23 24 /* 25 * default CCSRBAR is at 0xff700000 26 * assume U-Boot is less than 0.5MB 27 */ 28 29 #ifdef RUN_DIAG 30 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 31 #endif 32 33 /* 34 * virtual address to be used for temporary mappings. There 35 * should be 128k free at this VA. 36 */ 37 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 38 39 #define CONFIG_SYS_SRIO 40 #define CONFIG_SRIO1 /* SRIO port 1 */ 41 42 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ 43 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 47 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48 #define CONFIG_ENV_OVERWRITE 49 50 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 51 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 52 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 53 54 #define CONFIG_ALTIVEC 1 55 56 /* 57 * L2CR setup -- make sure this is right for your board! 58 */ 59 #define CONFIG_SYS_L2 60 #define L2_INIT 0 61 #define L2_ENABLE (L2CR_L2E) 62 63 #ifndef CONFIG_SYS_CLK_FREQ 64 #ifndef __ASSEMBLY__ 65 extern unsigned long get_board_sys_clk(unsigned long dummy); 66 #endif 67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 68 #endif 69 70 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 71 #define CONFIG_SYS_MEMTEST_END 0x00400000 72 73 /* 74 * With the exception of PCI Memory and Rapid IO, most devices will simply 75 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 76 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 77 */ 78 #ifdef CONFIG_PHYS_64BIT 79 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f 80 #else 81 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 82 #endif 83 84 /* 85 * Base addresses -- Note these are effective addresses where the 86 * actual resources get mapped (not physical addresses) 87 */ 88 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 89 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 90 91 /* Physical addresses */ 92 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 93 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH 94 #define CONFIG_SYS_CCSRBAR_PHYS \ 95 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 96 CONFIG_SYS_CCSRBAR_PHYS_HIGH) 97 98 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 99 100 /* 101 * DDR Setup 102 */ 103 #define CONFIG_FSL_DDR_INTERACTIVE 104 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 105 #define CONFIG_DDR_SPD 106 107 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 108 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 109 110 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 112 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 113 #define CONFIG_VERY_BIG_RAM 114 115 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 116 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 117 118 /* 119 * I2C addresses of SPD EEPROMs 120 */ 121 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 122 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 123 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 124 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 125 126 /* 127 * These are used when DDR doesn't use SPD. 128 */ 129 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 130 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 131 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 132 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 133 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 134 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 135 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 136 #define CONFIG_SYS_DDR_MODE_1 0x00480432 137 #define CONFIG_SYS_DDR_MODE_2 0x00000000 138 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 139 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 140 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 141 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 142 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 143 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 144 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 145 146 #define CONFIG_ID_EEPROM 147 #define CONFIG_SYS_I2C_EEPROM_NXID 148 #define CONFIG_ID_EEPROM 149 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 151 152 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 153 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE 154 #define CONFIG_SYS_FLASH_BASE_PHYS \ 155 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 156 CONFIG_SYS_PHYS_ADDR_HIGH) 157 158 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 159 160 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 161 | 0x00001001) /* port size 16bit */ 162 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 163 164 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 165 | 0x00001001) /* port size 16bit */ 166 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 167 168 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 169 | 0x00000801) /* port size 8bit */ 170 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 171 172 /* 173 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 174 * The PIXIS and CF by themselves aren't large enough to take up the 128k 175 * required for the smallest BAT mapping, so there's a 64k hole. 176 */ 177 #define CONFIG_SYS_LBC_BASE 0xffde0000 178 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE 179 180 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 181 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 182 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) 183 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ 184 CONFIG_SYS_PHYS_ADDR_HIGH) 185 #define PIXIS_SIZE 0x00008000 /* 32k */ 186 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 187 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 188 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 189 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 190 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 191 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 192 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 193 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 194 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 195 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 196 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 197 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 198 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 199 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 200 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 201 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 202 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 203 204 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 205 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 206 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 210 211 #undef CONFIG_SYS_FLASH_CHECKSUM 212 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 213 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 215 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 216 217 #define CONFIG_FLASH_CFI_DRIVER 218 #define CONFIG_SYS_FLASH_CFI 219 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 221 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 222 #define CONFIG_SYS_RAMBOOT 223 #else 224 #undef CONFIG_SYS_RAMBOOT 225 #endif 226 227 #if defined(CONFIG_SYS_RAMBOOT) 228 #undef CONFIG_SPD_EEPROM 229 #define CONFIG_SYS_SDRAM_SIZE 256 230 #endif 231 232 #undef CONFIG_CLOCKS_IN_MHZ 233 234 #define CONFIG_SYS_INIT_RAM_LOCK 1 235 #ifndef CONFIG_SYS_INIT_RAM_LOCK 236 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 237 #else 238 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 239 #endif 240 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 241 242 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 243 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 244 245 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 246 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 247 248 /* Serial Port */ 249 #define CONFIG_SYS_NS16550_SERIAL 250 #define CONFIG_SYS_NS16550_REG_SIZE 1 251 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 252 253 #define CONFIG_SYS_BAUDRATE_TABLE \ 254 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 255 256 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 257 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 258 259 /* 260 * I2C 261 */ 262 #define CONFIG_SYS_I2C 263 #define CONFIG_SYS_I2C_FSL 264 #define CONFIG_SYS_FSL_I2C_SPEED 400000 265 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 266 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 267 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 268 269 /* 270 * RapidIO MMU 271 */ 272 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 273 #ifdef CONFIG_PHYS_64BIT 274 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 275 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c 276 #else 277 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE 278 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 279 #endif 280 #define CONFIG_SYS_SRIO1_MEM_PHYS \ 281 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 282 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) 283 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 284 285 /* 286 * General PCI 287 * Addresses are mapped 1-1. 288 */ 289 290 #define CONFIG_SYS_PCIE1_NAME "ULI" 291 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 292 #ifdef CONFIG_PHYS_64BIT 293 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 294 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 295 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c 296 #else 297 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 298 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT 299 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 300 #endif 301 #define CONFIG_SYS_PCIE1_MEM_PHYS \ 302 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 303 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) 304 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 305 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 306 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 307 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT 308 #define CONFIG_SYS_PCIE1_IO_PHYS \ 309 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 310 CONFIG_SYS_PHYS_ADDR_HIGH) 311 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 312 313 #ifdef CONFIG_PHYS_64BIT 314 /* 315 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 316 * This will increase the amount of PCI address space available for 317 * for mapping RAM. 318 */ 319 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 320 #else 321 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 322 + CONFIG_SYS_PCIE1_MEM_SIZE) 323 #endif 324 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 325 + CONFIG_SYS_PCIE1_MEM_SIZE) 326 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ 327 + CONFIG_SYS_PCIE1_MEM_SIZE) 328 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 329 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 330 + CONFIG_SYS_PCIE1_MEM_SIZE) 331 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 332 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 333 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 334 + CONFIG_SYS_PCIE1_IO_SIZE) 335 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ 336 + CONFIG_SYS_PCIE1_IO_SIZE) 337 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 338 + CONFIG_SYS_PCIE1_IO_SIZE) 339 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 340 341 #if defined(CONFIG_PCI) 342 343 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 344 345 #undef CONFIG_EEPRO100 346 #undef CONFIG_TULIP 347 348 /************************************************************ 349 * USB support 350 ************************************************************/ 351 #define CONFIG_PCI_OHCI 1 352 #define CONFIG_USB_OHCI_NEW 1 353 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 354 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 355 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 356 357 /*PCIE video card used*/ 358 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 359 360 /*PCI video card used*/ 361 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 362 363 /* video */ 364 365 #if defined(CONFIG_VIDEO) 366 #define CONFIG_BIOSEMU 367 #define CONFIG_ATI_RADEON_FB 368 #define CONFIG_VIDEO_LOGO 369 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 370 #endif 371 372 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 373 374 #ifdef CONFIG_SCSI_AHCI 375 #define CONFIG_SATA_ULI5288 376 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 377 #define CONFIG_SYS_SCSI_MAX_LUN 1 378 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 379 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 380 #endif 381 382 #endif /* CONFIG_PCI */ 383 384 #if defined(CONFIG_TSEC_ENET) 385 386 #define CONFIG_MII 1 /* MII PHY management */ 387 388 #define CONFIG_TSEC1 1 389 #define CONFIG_TSEC1_NAME "eTSEC1" 390 #define CONFIG_TSEC2 1 391 #define CONFIG_TSEC2_NAME "eTSEC2" 392 #define CONFIG_TSEC3 1 393 #define CONFIG_TSEC3_NAME "eTSEC3" 394 #define CONFIG_TSEC4 1 395 #define CONFIG_TSEC4_NAME "eTSEC4" 396 397 #define TSEC1_PHY_ADDR 0 398 #define TSEC2_PHY_ADDR 1 399 #define TSEC3_PHY_ADDR 2 400 #define TSEC4_PHY_ADDR 3 401 #define TSEC1_PHYIDX 0 402 #define TSEC2_PHYIDX 0 403 #define TSEC3_PHYIDX 0 404 #define TSEC4_PHYIDX 0 405 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 406 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 407 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 408 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 409 410 #define CONFIG_ETHPRIME "eTSEC1" 411 412 #endif /* CONFIG_TSEC_ENET */ 413 414 #ifdef CONFIG_PHYS_64BIT 415 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 416 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 417 418 /* Put physical address into the BAT format */ 419 #define BAT_PHYS_ADDR(low, high) \ 420 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) 421 /* Convert high/low pairs to actual 64-bit value */ 422 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) 423 #else 424 /* 32-bit systems just ignore the "high" bits */ 425 #define BAT_PHYS_ADDR(low, high) (low) 426 #define PAIRED_PHYS_TO_PHYS(low, high) (low) 427 #endif 428 429 /* 430 * BAT0 DDR 431 */ 432 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 433 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 434 435 /* 436 * BAT1 LBC (PIXIS/CF) 437 */ 438 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 439 CONFIG_SYS_PHYS_ADDR_HIGH) \ 440 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 441 BATL_GUARDEDSTORAGE) 442 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 443 | BATU_VS | BATU_VP) 444 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 445 CONFIG_SYS_PHYS_ADDR_HIGH) \ 446 | BATL_PP_RW | BATL_MEMCOHERENCE) 447 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 448 449 /* if CONFIG_PCI: 450 * BAT2 PCIE1 and PCIE1 MEM 451 * if CONFIG_RIO 452 * BAT2 Rapidio Memory 453 */ 454 #ifdef CONFIG_PCI 455 #define CONFIG_PCI_INDIRECT_BRIDGE 456 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 457 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 458 | BATL_PP_RW | BATL_CACHEINHIBIT \ 459 | BATL_GUARDEDSTORAGE) 460 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 461 | BATU_VS | BATU_VP) 462 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 463 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 464 | BATL_PP_RW | BATL_CACHEINHIBIT) 465 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 466 #else /* CONFIG_RIO */ 467 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 468 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 469 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 470 BATL_GUARDEDSTORAGE) 471 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 472 | BATU_VS | BATU_VP) 473 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 474 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 475 | BATL_PP_RW | BATL_CACHEINHIBIT) 476 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 477 #endif 478 479 /* 480 * BAT3 CCSR Space 481 */ 482 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 483 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 484 | BATL_PP_RW | BATL_CACHEINHIBIT \ 485 | BATL_GUARDEDSTORAGE) 486 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 487 | BATU_VP) 488 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 489 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 490 | BATL_PP_RW | BATL_CACHEINHIBIT) 491 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 492 493 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 494 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 495 | BATL_PP_RW | BATL_CACHEINHIBIT \ 496 | BATL_GUARDEDSTORAGE) 497 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 498 | BATU_BL_1M | BATU_VS | BATU_VP) 499 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 500 | BATL_PP_RW | BATL_CACHEINHIBIT) 501 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 502 #endif 503 504 /* 505 * BAT4 PCIE1_IO and PCIE2_IO 506 */ 507 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 508 CONFIG_SYS_PHYS_ADDR_HIGH) \ 509 | BATL_PP_RW | BATL_CACHEINHIBIT \ 510 | BATL_GUARDEDSTORAGE) 511 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 512 | BATU_VS | BATU_VP) 513 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 514 CONFIG_SYS_PHYS_ADDR_HIGH) \ 515 | BATL_PP_RW | BATL_CACHEINHIBIT) 516 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 517 518 /* 519 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 520 */ 521 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 522 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 523 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 524 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 525 526 /* 527 * BAT6 FLASH 528 */ 529 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 530 CONFIG_SYS_PHYS_ADDR_HIGH) \ 531 | BATL_PP_RW | BATL_CACHEINHIBIT \ 532 | BATL_GUARDEDSTORAGE) 533 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 534 | BATU_VP) 535 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 536 CONFIG_SYS_PHYS_ADDR_HIGH) \ 537 | BATL_PP_RW | BATL_MEMCOHERENCE) 538 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 539 540 /* Map the last 1M of flash where we're running from reset */ 541 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 542 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 543 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 544 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 545 | BATL_MEMCOHERENCE) 546 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 547 548 /* 549 * BAT7 FREE - used later for tmp mappings 550 */ 551 #define CONFIG_SYS_DBAT7L 0x00000000 552 #define CONFIG_SYS_DBAT7U 0x00000000 553 #define CONFIG_SYS_IBAT7L 0x00000000 554 #define CONFIG_SYS_IBAT7U 0x00000000 555 556 /* 557 * Environment 558 */ 559 #ifndef CONFIG_SYS_RAMBOOT 560 #define CONFIG_ENV_ADDR \ 561 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 562 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 563 #else 564 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 565 #endif 566 #define CONFIG_ENV_SIZE 0x2000 567 568 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 569 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 570 571 /* 572 * BOOTP options 573 */ 574 #define CONFIG_BOOTP_BOOTFILESIZE 575 576 #undef CONFIG_WATCHDOG /* watchdog disabled */ 577 578 /* 579 * Miscellaneous configurable options 580 */ 581 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 582 583 /* 584 * For booting Linux, the board info and command line data 585 * have to be in the first 8 MB of memory, since this is 586 * the maximum mapped by the Linux kernel during initialization. 587 */ 588 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 589 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 590 591 #if defined(CONFIG_CMD_KGDB) 592 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 593 #endif 594 595 /* 596 * Environment Configuration 597 */ 598 599 #define CONFIG_HAS_ETH0 1 600 #define CONFIG_HAS_ETH1 1 601 #define CONFIG_HAS_ETH2 1 602 #define CONFIG_HAS_ETH3 1 603 604 #define CONFIG_IPADDR 192.168.1.100 605 606 #define CONFIG_HOSTNAME unknown 607 #define CONFIG_ROOTPATH "/opt/nfsroot" 608 #define CONFIG_BOOTFILE "uImage" 609 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 610 611 #define CONFIG_SERVERIP 192.168.1.1 612 #define CONFIG_GATEWAYIP 192.168.1.1 613 #define CONFIG_NETMASK 255.255.255.0 614 615 /* default location for tftp and bootm */ 616 #define CONFIG_LOADADDR 0x10000000 617 618 #define CONFIG_EXTRA_ENV_SETTINGS \ 619 "netdev=eth0\0" \ 620 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 621 "tftpflash=tftpboot $loadaddr $uboot; " \ 622 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 623 " +$filesize; " \ 624 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 625 " +$filesize; " \ 626 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 627 " $filesize; " \ 628 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 629 " +$filesize; " \ 630 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 631 " $filesize\0" \ 632 "consoledev=ttyS0\0" \ 633 "ramdiskaddr=0x18000000\0" \ 634 "ramdiskfile=your.ramdisk.u-boot\0" \ 635 "fdtaddr=0x17c00000\0" \ 636 "fdtfile=mpc8641_hpcn.dtb\0" \ 637 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 638 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 639 "maxcpus=2" 640 641 #define CONFIG_NFSBOOTCOMMAND \ 642 "setenv bootargs root=/dev/nfs rw " \ 643 "nfsroot=$serverip:$rootpath " \ 644 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 645 "console=$consoledev,$baudrate $othbootargs;" \ 646 "tftp $loadaddr $bootfile;" \ 647 "tftp $fdtaddr $fdtfile;" \ 648 "bootm $loadaddr - $fdtaddr" 649 650 #define CONFIG_RAMBOOTCOMMAND \ 651 "setenv bootargs root=/dev/ram rw " \ 652 "console=$consoledev,$baudrate $othbootargs;" \ 653 "tftp $ramdiskaddr $ramdiskfile;" \ 654 "tftp $loadaddr $bootfile;" \ 655 "tftp $fdtaddr $fdtfile;" \ 656 "bootm $loadaddr $ramdiskaddr $fdtaddr" 657 658 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 659 660 #endif /* __CONFIG_H */ 661