1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * MPC8641HPCN board configuration file 11 * 12 * Make sure you change the MAC address and other network params first, 13 * search for CONFIG_SERVERIP, etc. in this file. 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MP 1 /* support multiple processors */ 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 23 24 /* 25 * default CCSRBAR is at 0xff700000 26 * assume U-Boot is less than 0.5MB 27 */ 28 #define CONFIG_SYS_TEXT_BASE 0xeff00000 29 30 #ifdef RUN_DIAG 31 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 32 #endif 33 34 /* 35 * virtual address to be used for temporary mappings. There 36 * should be 128k free at this VA. 37 */ 38 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 39 40 #define CONFIG_SYS_SRIO 41 #define CONFIG_SRIO1 /* SRIO port 1 */ 42 43 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ 44 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ 45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47 48 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 49 #define CONFIG_ENV_OVERWRITE 50 51 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 52 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 53 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 54 55 #define CONFIG_ALTIVEC 1 56 57 /* 58 * L2CR setup -- make sure this is right for your board! 59 */ 60 #define CONFIG_SYS_L2 61 #define L2_INIT 0 62 #define L2_ENABLE (L2CR_L2E) 63 64 #ifndef CONFIG_SYS_CLK_FREQ 65 #ifndef __ASSEMBLY__ 66 extern unsigned long get_board_sys_clk(unsigned long dummy); 67 #endif 68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 69 #endif 70 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 /* 75 * With the exception of PCI Memory and Rapid IO, most devices will simply 76 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 77 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 78 */ 79 #ifdef CONFIG_PHYS_64BIT 80 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f 81 #else 82 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 83 #endif 84 85 /* 86 * Base addresses -- Note these are effective addresses where the 87 * actual resources get mapped (not physical addresses) 88 */ 89 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 90 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 91 92 /* Physical addresses */ 93 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 94 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH 95 #define CONFIG_SYS_CCSRBAR_PHYS \ 96 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 97 CONFIG_SYS_CCSRBAR_PHYS_HIGH) 98 99 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 100 101 /* 102 * DDR Setup 103 */ 104 #define CONFIG_FSL_DDR_INTERACTIVE 105 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 106 #define CONFIG_DDR_SPD 107 108 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 109 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 110 111 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 112 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 113 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 114 #define CONFIG_VERY_BIG_RAM 115 116 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 117 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 118 119 /* 120 * I2C addresses of SPD EEPROMs 121 */ 122 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 123 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 124 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 125 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 126 127 /* 128 * These are used when DDR doesn't use SPD. 129 */ 130 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 131 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 132 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 133 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 134 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 135 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 136 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 137 #define CONFIG_SYS_DDR_MODE_1 0x00480432 138 #define CONFIG_SYS_DDR_MODE_2 0x00000000 139 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 140 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 141 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 142 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 143 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 144 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 145 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 146 147 #define CONFIG_ID_EEPROM 148 #define CONFIG_SYS_I2C_EEPROM_NXID 149 #define CONFIG_ID_EEPROM 150 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 151 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 152 153 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 154 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE 155 #define CONFIG_SYS_FLASH_BASE_PHYS \ 156 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 157 CONFIG_SYS_PHYS_ADDR_HIGH) 158 159 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 160 161 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 162 | 0x00001001) /* port size 16bit */ 163 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 164 165 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 166 | 0x00001001) /* port size 16bit */ 167 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 168 169 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 170 | 0x00000801) /* port size 8bit */ 171 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 172 173 /* 174 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 175 * The PIXIS and CF by themselves aren't large enough to take up the 128k 176 * required for the smallest BAT mapping, so there's a 64k hole. 177 */ 178 #define CONFIG_SYS_LBC_BASE 0xffde0000 179 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE 180 181 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 182 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 183 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) 184 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ 185 CONFIG_SYS_PHYS_ADDR_HIGH) 186 #define PIXIS_SIZE 0x00008000 /* 32k */ 187 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 188 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 189 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 190 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 191 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 192 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 193 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 194 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 195 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 196 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 197 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 198 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 199 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 200 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 201 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 202 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 203 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 204 205 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 206 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 207 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 208 209 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 210 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 211 212 #undef CONFIG_SYS_FLASH_CHECKSUM 213 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 214 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 215 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 216 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 217 218 #define CONFIG_FLASH_CFI_DRIVER 219 #define CONFIG_SYS_FLASH_CFI 220 #define CONFIG_SYS_FLASH_EMPTY_INFO 221 222 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 223 #define CONFIG_SYS_RAMBOOT 224 #else 225 #undef CONFIG_SYS_RAMBOOT 226 #endif 227 228 #if defined(CONFIG_SYS_RAMBOOT) 229 #undef CONFIG_SPD_EEPROM 230 #define CONFIG_SYS_SDRAM_SIZE 256 231 #endif 232 233 #undef CONFIG_CLOCKS_IN_MHZ 234 235 #define CONFIG_SYS_INIT_RAM_LOCK 1 236 #ifndef CONFIG_SYS_INIT_RAM_LOCK 237 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 238 #else 239 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 240 #endif 241 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 242 243 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 244 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 245 246 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 247 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 248 249 /* Serial Port */ 250 #define CONFIG_CONS_INDEX 1 251 #define CONFIG_SYS_NS16550_SERIAL 252 #define CONFIG_SYS_NS16550_REG_SIZE 1 253 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 254 255 #define CONFIG_SYS_BAUDRATE_TABLE \ 256 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 257 258 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 259 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 260 261 /* 262 * I2C 263 */ 264 #define CONFIG_SYS_I2C 265 #define CONFIG_SYS_I2C_FSL 266 #define CONFIG_SYS_FSL_I2C_SPEED 400000 267 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 268 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 269 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 270 271 /* 272 * RapidIO MMU 273 */ 274 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 275 #ifdef CONFIG_PHYS_64BIT 276 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 277 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c 278 #else 279 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE 280 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 281 #endif 282 #define CONFIG_SYS_SRIO1_MEM_PHYS \ 283 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 284 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) 285 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 286 287 /* 288 * General PCI 289 * Addresses are mapped 1-1. 290 */ 291 292 #define CONFIG_SYS_PCIE1_NAME "ULI" 293 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 294 #ifdef CONFIG_PHYS_64BIT 295 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 296 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 297 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c 298 #else 299 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 300 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT 301 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 302 #endif 303 #define CONFIG_SYS_PCIE1_MEM_PHYS \ 304 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 305 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) 306 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 307 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 308 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 309 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT 310 #define CONFIG_SYS_PCIE1_IO_PHYS \ 311 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 312 CONFIG_SYS_PHYS_ADDR_HIGH) 313 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 314 315 #ifdef CONFIG_PHYS_64BIT 316 /* 317 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 318 * This will increase the amount of PCI address space available for 319 * for mapping RAM. 320 */ 321 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 322 #else 323 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 324 + CONFIG_SYS_PCIE1_MEM_SIZE) 325 #endif 326 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 327 + CONFIG_SYS_PCIE1_MEM_SIZE) 328 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ 329 + CONFIG_SYS_PCIE1_MEM_SIZE) 330 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 331 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 332 + CONFIG_SYS_PCIE1_MEM_SIZE) 333 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 334 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 335 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 336 + CONFIG_SYS_PCIE1_IO_SIZE) 337 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ 338 + CONFIG_SYS_PCIE1_IO_SIZE) 339 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 340 + CONFIG_SYS_PCIE1_IO_SIZE) 341 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 342 343 #if defined(CONFIG_PCI) 344 345 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 346 347 #undef CONFIG_EEPRO100 348 #undef CONFIG_TULIP 349 350 /************************************************************ 351 * USB support 352 ************************************************************/ 353 #define CONFIG_PCI_OHCI 1 354 #define CONFIG_USB_OHCI_NEW 1 355 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 356 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 357 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 358 359 /*PCIE video card used*/ 360 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 361 362 /*PCI video card used*/ 363 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 364 365 /* video */ 366 367 #if defined(CONFIG_VIDEO) 368 #define CONFIG_BIOSEMU 369 #define CONFIG_ATI_RADEON_FB 370 #define CONFIG_VIDEO_LOGO 371 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 372 #endif 373 374 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 375 376 #define CONFIG_SCSI_AHCI 377 378 #ifdef CONFIG_SCSI_AHCI 379 #define CONFIG_LIBATA 380 #define CONFIG_SATA_ULI5288 381 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 382 #define CONFIG_SYS_SCSI_MAX_LUN 1 383 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 384 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 385 #endif 386 387 #endif /* CONFIG_PCI */ 388 389 #if defined(CONFIG_TSEC_ENET) 390 391 #define CONFIG_MII 1 /* MII PHY management */ 392 393 #define CONFIG_TSEC1 1 394 #define CONFIG_TSEC1_NAME "eTSEC1" 395 #define CONFIG_TSEC2 1 396 #define CONFIG_TSEC2_NAME "eTSEC2" 397 #define CONFIG_TSEC3 1 398 #define CONFIG_TSEC3_NAME "eTSEC3" 399 #define CONFIG_TSEC4 1 400 #define CONFIG_TSEC4_NAME "eTSEC4" 401 402 #define TSEC1_PHY_ADDR 0 403 #define TSEC2_PHY_ADDR 1 404 #define TSEC3_PHY_ADDR 2 405 #define TSEC4_PHY_ADDR 3 406 #define TSEC1_PHYIDX 0 407 #define TSEC2_PHYIDX 0 408 #define TSEC3_PHYIDX 0 409 #define TSEC4_PHYIDX 0 410 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 411 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 412 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 413 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 414 415 #define CONFIG_ETHPRIME "eTSEC1" 416 417 #endif /* CONFIG_TSEC_ENET */ 418 419 #ifdef CONFIG_PHYS_64BIT 420 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 421 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 422 423 /* Put physical address into the BAT format */ 424 #define BAT_PHYS_ADDR(low, high) \ 425 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) 426 /* Convert high/low pairs to actual 64-bit value */ 427 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) 428 #else 429 /* 32-bit systems just ignore the "high" bits */ 430 #define BAT_PHYS_ADDR(low, high) (low) 431 #define PAIRED_PHYS_TO_PHYS(low, high) (low) 432 #endif 433 434 /* 435 * BAT0 DDR 436 */ 437 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 438 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 439 440 /* 441 * BAT1 LBC (PIXIS/CF) 442 */ 443 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 444 CONFIG_SYS_PHYS_ADDR_HIGH) \ 445 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 446 BATL_GUARDEDSTORAGE) 447 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 448 | BATU_VS | BATU_VP) 449 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 450 CONFIG_SYS_PHYS_ADDR_HIGH) \ 451 | BATL_PP_RW | BATL_MEMCOHERENCE) 452 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 453 454 /* if CONFIG_PCI: 455 * BAT2 PCIE1 and PCIE1 MEM 456 * if CONFIG_RIO 457 * BAT2 Rapidio Memory 458 */ 459 #ifdef CONFIG_PCI 460 #define CONFIG_PCI_INDIRECT_BRIDGE 461 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 462 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 463 | BATL_PP_RW | BATL_CACHEINHIBIT \ 464 | BATL_GUARDEDSTORAGE) 465 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 466 | BATU_VS | BATU_VP) 467 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 468 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 469 | BATL_PP_RW | BATL_CACHEINHIBIT) 470 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 471 #else /* CONFIG_RIO */ 472 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 473 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 474 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 475 BATL_GUARDEDSTORAGE) 476 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 477 | BATU_VS | BATU_VP) 478 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 479 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 480 | BATL_PP_RW | BATL_CACHEINHIBIT) 481 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 482 #endif 483 484 /* 485 * BAT3 CCSR Space 486 */ 487 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 488 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 489 | BATL_PP_RW | BATL_CACHEINHIBIT \ 490 | BATL_GUARDEDSTORAGE) 491 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 492 | BATU_VP) 493 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 494 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 495 | BATL_PP_RW | BATL_CACHEINHIBIT) 496 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 497 498 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 499 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 500 | BATL_PP_RW | BATL_CACHEINHIBIT \ 501 | BATL_GUARDEDSTORAGE) 502 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 503 | BATU_BL_1M | BATU_VS | BATU_VP) 504 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 505 | BATL_PP_RW | BATL_CACHEINHIBIT) 506 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 507 #endif 508 509 /* 510 * BAT4 PCIE1_IO and PCIE2_IO 511 */ 512 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 513 CONFIG_SYS_PHYS_ADDR_HIGH) \ 514 | BATL_PP_RW | BATL_CACHEINHIBIT \ 515 | BATL_GUARDEDSTORAGE) 516 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 517 | BATU_VS | BATU_VP) 518 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 519 CONFIG_SYS_PHYS_ADDR_HIGH) \ 520 | BATL_PP_RW | BATL_CACHEINHIBIT) 521 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 522 523 /* 524 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 525 */ 526 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 527 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 528 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 529 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 530 531 /* 532 * BAT6 FLASH 533 */ 534 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 535 CONFIG_SYS_PHYS_ADDR_HIGH) \ 536 | BATL_PP_RW | BATL_CACHEINHIBIT \ 537 | BATL_GUARDEDSTORAGE) 538 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 539 | BATU_VP) 540 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 541 CONFIG_SYS_PHYS_ADDR_HIGH) \ 542 | BATL_PP_RW | BATL_MEMCOHERENCE) 543 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 544 545 /* Map the last 1M of flash where we're running from reset */ 546 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 547 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 548 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 549 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 550 | BATL_MEMCOHERENCE) 551 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 552 553 /* 554 * BAT7 FREE - used later for tmp mappings 555 */ 556 #define CONFIG_SYS_DBAT7L 0x00000000 557 #define CONFIG_SYS_DBAT7U 0x00000000 558 #define CONFIG_SYS_IBAT7L 0x00000000 559 #define CONFIG_SYS_IBAT7U 0x00000000 560 561 /* 562 * Environment 563 */ 564 #ifndef CONFIG_SYS_RAMBOOT 565 #define CONFIG_ENV_ADDR \ 566 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 567 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 568 #else 569 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 570 #endif 571 #define CONFIG_ENV_SIZE 0x2000 572 573 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 574 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 575 576 /* 577 * BOOTP options 578 */ 579 #define CONFIG_BOOTP_BOOTFILESIZE 580 #define CONFIG_BOOTP_BOOTPATH 581 #define CONFIG_BOOTP_GATEWAY 582 #define CONFIG_BOOTP_HOSTNAME 583 584 #undef CONFIG_WATCHDOG /* watchdog disabled */ 585 586 /* 587 * Miscellaneous configurable options 588 */ 589 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 590 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 591 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 592 593 /* 594 * For booting Linux, the board info and command line data 595 * have to be in the first 8 MB of memory, since this is 596 * the maximum mapped by the Linux kernel during initialization. 597 */ 598 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 599 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 600 601 #if defined(CONFIG_CMD_KGDB) 602 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 603 #endif 604 605 /* 606 * Environment Configuration 607 */ 608 609 #define CONFIG_HAS_ETH0 1 610 #define CONFIG_HAS_ETH1 1 611 #define CONFIG_HAS_ETH2 1 612 #define CONFIG_HAS_ETH3 1 613 614 #define CONFIG_IPADDR 192.168.1.100 615 616 #define CONFIG_HOSTNAME unknown 617 #define CONFIG_ROOTPATH "/opt/nfsroot" 618 #define CONFIG_BOOTFILE "uImage" 619 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 620 621 #define CONFIG_SERVERIP 192.168.1.1 622 #define CONFIG_GATEWAYIP 192.168.1.1 623 #define CONFIG_NETMASK 255.255.255.0 624 625 /* default location for tftp and bootm */ 626 #define CONFIG_LOADADDR 0x10000000 627 628 #define CONFIG_EXTRA_ENV_SETTINGS \ 629 "netdev=eth0\0" \ 630 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 631 "tftpflash=tftpboot $loadaddr $uboot; " \ 632 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 633 " +$filesize; " \ 634 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 635 " +$filesize; " \ 636 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 637 " $filesize; " \ 638 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 639 " +$filesize; " \ 640 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 641 " $filesize\0" \ 642 "consoledev=ttyS0\0" \ 643 "ramdiskaddr=0x18000000\0" \ 644 "ramdiskfile=your.ramdisk.u-boot\0" \ 645 "fdtaddr=0x17c00000\0" \ 646 "fdtfile=mpc8641_hpcn.dtb\0" \ 647 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 648 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 649 "maxcpus=2" 650 651 #define CONFIG_NFSBOOTCOMMAND \ 652 "setenv bootargs root=/dev/nfs rw " \ 653 "nfsroot=$serverip:$rootpath " \ 654 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 655 "console=$consoledev,$baudrate $othbootargs;" \ 656 "tftp $loadaddr $bootfile;" \ 657 "tftp $fdtaddr $fdtfile;" \ 658 "bootm $loadaddr - $fdtaddr" 659 660 #define CONFIG_RAMBOOTCOMMAND \ 661 "setenv bootargs root=/dev/ram rw " \ 662 "console=$consoledev,$baudrate $othbootargs;" \ 663 "tftp $ramdiskaddr $ramdiskfile;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr $ramdiskaddr $fdtaddr" 667 668 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 669 670 #endif /* __CONFIG_H */ 671