1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * MPC8641HPCN board configuration file 11 * 12 * Make sure you change the MAC address and other network params first, 13 * search for CONFIG_SERVERIP, etc. in this file. 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 /* High Level Configuration Options */ 22 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 23 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 24 #define CONFIG_MP 1 /* support multiple processors */ 25 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 26 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ 27 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 28 29 /* 30 * default CCSRBAR is at 0xff700000 31 * assume U-Boot is less than 0.5MB 32 */ 33 #define CONFIG_SYS_TEXT_BASE 0xeff00000 34 35 #ifdef RUN_DIAG 36 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 37 #endif 38 39 /* 40 * virtual address to be used for temporary mappings. There 41 * should be 128k free at this VA. 42 */ 43 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 44 45 #define CONFIG_SYS_SRIO 46 #define CONFIG_SRIO1 /* SRIO port 1 */ 47 48 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 49 #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ 50 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ 51 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 53 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 54 55 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 56 #define CONFIG_ENV_OVERWRITE 57 58 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 59 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 60 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 61 62 #define CONFIG_ALTIVEC 1 63 64 /* 65 * L2CR setup -- make sure this is right for your board! 66 */ 67 #define CONFIG_SYS_L2 68 #define L2_INIT 0 69 #define L2_ENABLE (L2CR_L2E) 70 71 #ifndef CONFIG_SYS_CLK_FREQ 72 #ifndef __ASSEMBLY__ 73 extern unsigned long get_board_sys_clk(unsigned long dummy); 74 #endif 75 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 76 #endif 77 78 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 79 #define CONFIG_SYS_MEMTEST_END 0x00400000 80 81 /* 82 * With the exception of PCI Memory and Rapid IO, most devices will simply 83 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 84 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 85 */ 86 #ifdef CONFIG_PHYS_64BIT 87 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f 88 #else 89 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 90 #endif 91 92 /* 93 * Base addresses -- Note these are effective addresses where the 94 * actual resources get mapped (not physical addresses) 95 */ 96 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 97 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 98 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 99 100 /* Physical addresses */ 101 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 102 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH 103 #define CONFIG_SYS_CCSRBAR_PHYS \ 104 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 105 CONFIG_SYS_CCSRBAR_PHYS_HIGH) 106 107 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 108 109 /* 110 * DDR Setup 111 */ 112 #define CONFIG_SYS_FSL_DDR2 113 #undef CONFIG_FSL_DDR_INTERACTIVE 114 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 115 #define CONFIG_DDR_SPD 116 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 118 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 119 120 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 122 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 123 #define CONFIG_VERY_BIG_RAM 124 125 #define CONFIG_NUM_DDR_CONTROLLERS 2 126 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 127 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 128 129 /* 130 * I2C addresses of SPD EEPROMs 131 */ 132 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 133 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 134 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 135 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 136 137 /* 138 * These are used when DDR doesn't use SPD. 139 */ 140 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 141 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 142 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 143 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 144 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 145 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 146 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 147 #define CONFIG_SYS_DDR_MODE_1 0x00480432 148 #define CONFIG_SYS_DDR_MODE_2 0x00000000 149 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 150 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 151 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 152 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 153 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 154 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 155 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 156 157 #define CONFIG_ID_EEPROM 158 #define CONFIG_SYS_I2C_EEPROM_NXID 159 #define CONFIG_ID_EEPROM 160 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 161 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 162 163 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 164 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE 165 #define CONFIG_SYS_FLASH_BASE_PHYS \ 166 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 167 CONFIG_SYS_PHYS_ADDR_HIGH) 168 169 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 170 171 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 172 | 0x00001001) /* port size 16bit */ 173 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 174 175 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 176 | 0x00001001) /* port size 16bit */ 177 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 178 179 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 180 | 0x00000801) /* port size 8bit */ 181 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 182 183 /* 184 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 185 * The PIXIS and CF by themselves aren't large enough to take up the 128k 186 * required for the smallest BAT mapping, so there's a 64k hole. 187 */ 188 #define CONFIG_SYS_LBC_BASE 0xffde0000 189 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE 190 191 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 192 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 193 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) 194 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ 195 CONFIG_SYS_PHYS_ADDR_HIGH) 196 #define PIXIS_SIZE 0x00008000 /* 32k */ 197 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 198 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 199 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 200 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 201 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 202 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 203 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 204 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 205 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 206 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 207 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 208 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 209 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 210 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 211 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 212 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 213 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 214 215 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 216 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 217 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 221 222 #undef CONFIG_SYS_FLASH_CHECKSUM 223 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 225 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 226 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 227 228 #define CONFIG_FLASH_CFI_DRIVER 229 #define CONFIG_SYS_FLASH_CFI 230 #define CONFIG_SYS_FLASH_EMPTY_INFO 231 232 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 233 #define CONFIG_SYS_RAMBOOT 234 #else 235 #undef CONFIG_SYS_RAMBOOT 236 #endif 237 238 #if defined(CONFIG_SYS_RAMBOOT) 239 #undef CONFIG_SPD_EEPROM 240 #define CONFIG_SYS_SDRAM_SIZE 256 241 #endif 242 243 #undef CONFIG_CLOCKS_IN_MHZ 244 245 #define CONFIG_SYS_INIT_RAM_LOCK 1 246 #ifndef CONFIG_SYS_INIT_RAM_LOCK 247 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 248 #else 249 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 250 #endif 251 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 252 253 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 254 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 255 256 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 257 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 258 259 /* Serial Port */ 260 #define CONFIG_CONS_INDEX 1 261 #define CONFIG_SYS_NS16550_SERIAL 262 #define CONFIG_SYS_NS16550_REG_SIZE 1 263 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 264 265 #define CONFIG_SYS_BAUDRATE_TABLE \ 266 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 267 268 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 269 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 270 271 /* 272 * I2C 273 */ 274 #define CONFIG_SYS_I2C 275 #define CONFIG_SYS_I2C_FSL 276 #define CONFIG_SYS_FSL_I2C_SPEED 400000 277 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 278 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 279 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 280 281 /* 282 * RapidIO MMU 283 */ 284 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 287 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c 288 #else 289 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE 290 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 291 #endif 292 #define CONFIG_SYS_SRIO1_MEM_PHYS \ 293 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 294 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) 295 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 296 297 /* 298 * General PCI 299 * Addresses are mapped 1-1. 300 */ 301 302 #define CONFIG_SYS_PCIE1_NAME "ULI" 303 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 304 #ifdef CONFIG_PHYS_64BIT 305 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 306 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 307 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c 308 #else 309 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 310 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT 311 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 312 #endif 313 #define CONFIG_SYS_PCIE1_MEM_PHYS \ 314 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 315 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) 316 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 317 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 318 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 319 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT 320 #define CONFIG_SYS_PCIE1_IO_PHYS \ 321 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 322 CONFIG_SYS_PHYS_ADDR_HIGH) 323 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 324 325 #ifdef CONFIG_PHYS_64BIT 326 /* 327 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 328 * This will increase the amount of PCI address space available for 329 * for mapping RAM. 330 */ 331 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 332 #else 333 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 334 + CONFIG_SYS_PCIE1_MEM_SIZE) 335 #endif 336 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 337 + CONFIG_SYS_PCIE1_MEM_SIZE) 338 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ 339 + CONFIG_SYS_PCIE1_MEM_SIZE) 340 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 341 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 342 + CONFIG_SYS_PCIE1_MEM_SIZE) 343 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 344 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 345 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 346 + CONFIG_SYS_PCIE1_IO_SIZE) 347 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ 348 + CONFIG_SYS_PCIE1_IO_SIZE) 349 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 350 + CONFIG_SYS_PCIE1_IO_SIZE) 351 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 352 353 #if defined(CONFIG_PCI) 354 355 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 356 357 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 358 359 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 360 361 #undef CONFIG_EEPRO100 362 #undef CONFIG_TULIP 363 364 /************************************************************ 365 * USB support 366 ************************************************************/ 367 #define CONFIG_PCI_OHCI 1 368 #define CONFIG_USB_OHCI_NEW 1 369 #define CONFIG_USB_KEYBOARD 1 370 #define CONFIG_SYS_STDIO_DEREGISTER 371 #define CONFIG_SYS_USB_EVENT_POLL 1 372 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 373 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 374 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 375 376 /*PCIE video card used*/ 377 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 378 379 /*PCI video card used*/ 380 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 381 382 /* video */ 383 #define CONFIG_VIDEO 384 385 #if defined(CONFIG_VIDEO) 386 #define CONFIG_BIOSEMU 387 #define CONFIG_CFB_CONSOLE 388 #define CONFIG_VIDEO_SW_CURSOR 389 #define CONFIG_VGA_AS_SINGLE_DEVICE 390 #define CONFIG_ATI_RADEON_FB 391 #define CONFIG_VIDEO_LOGO 392 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 393 #endif 394 395 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 396 397 #define CONFIG_DOS_PARTITION 398 #define CONFIG_SCSI_AHCI 399 400 #ifdef CONFIG_SCSI_AHCI 401 #define CONFIG_LIBATA 402 #define CONFIG_SATA_ULI5288 403 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 404 #define CONFIG_SYS_SCSI_MAX_LUN 1 405 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 406 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 407 #endif 408 409 #endif /* CONFIG_PCI */ 410 411 #if defined(CONFIG_TSEC_ENET) 412 413 #define CONFIG_MII 1 /* MII PHY management */ 414 415 #define CONFIG_TSEC1 1 416 #define CONFIG_TSEC1_NAME "eTSEC1" 417 #define CONFIG_TSEC2 1 418 #define CONFIG_TSEC2_NAME "eTSEC2" 419 #define CONFIG_TSEC3 1 420 #define CONFIG_TSEC3_NAME "eTSEC3" 421 #define CONFIG_TSEC4 1 422 #define CONFIG_TSEC4_NAME "eTSEC4" 423 424 #define TSEC1_PHY_ADDR 0 425 #define TSEC2_PHY_ADDR 1 426 #define TSEC3_PHY_ADDR 2 427 #define TSEC4_PHY_ADDR 3 428 #define TSEC1_PHYIDX 0 429 #define TSEC2_PHYIDX 0 430 #define TSEC3_PHYIDX 0 431 #define TSEC4_PHYIDX 0 432 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 433 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 434 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 435 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 436 437 #define CONFIG_ETHPRIME "eTSEC1" 438 439 #endif /* CONFIG_TSEC_ENET */ 440 441 #ifdef CONFIG_PHYS_64BIT 442 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 443 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 444 445 /* Put physical address into the BAT format */ 446 #define BAT_PHYS_ADDR(low, high) \ 447 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) 448 /* Convert high/low pairs to actual 64-bit value */ 449 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) 450 #else 451 /* 32-bit systems just ignore the "high" bits */ 452 #define BAT_PHYS_ADDR(low, high) (low) 453 #define PAIRED_PHYS_TO_PHYS(low, high) (low) 454 #endif 455 456 /* 457 * BAT0 DDR 458 */ 459 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 460 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 461 462 /* 463 * BAT1 LBC (PIXIS/CF) 464 */ 465 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 466 CONFIG_SYS_PHYS_ADDR_HIGH) \ 467 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 468 BATL_GUARDEDSTORAGE) 469 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 470 | BATU_VS | BATU_VP) 471 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 472 CONFIG_SYS_PHYS_ADDR_HIGH) \ 473 | BATL_PP_RW | BATL_MEMCOHERENCE) 474 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 475 476 /* if CONFIG_PCI: 477 * BAT2 PCIE1 and PCIE1 MEM 478 * if CONFIG_RIO 479 * BAT2 Rapidio Memory 480 */ 481 #ifdef CONFIG_PCI 482 #define CONFIG_PCI_INDIRECT_BRIDGE 483 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 484 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 485 | BATL_PP_RW | BATL_CACHEINHIBIT \ 486 | BATL_GUARDEDSTORAGE) 487 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 488 | BATU_VS | BATU_VP) 489 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 490 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 491 | BATL_PP_RW | BATL_CACHEINHIBIT) 492 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 493 #else /* CONFIG_RIO */ 494 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 495 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 496 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 497 BATL_GUARDEDSTORAGE) 498 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 499 | BATU_VS | BATU_VP) 500 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 501 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 502 | BATL_PP_RW | BATL_CACHEINHIBIT) 503 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 504 #endif 505 506 /* 507 * BAT3 CCSR Space 508 */ 509 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 510 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 511 | BATL_PP_RW | BATL_CACHEINHIBIT \ 512 | BATL_GUARDEDSTORAGE) 513 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 514 | BATU_VP) 515 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 516 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 517 | BATL_PP_RW | BATL_CACHEINHIBIT) 518 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 519 520 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 521 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 522 | BATL_PP_RW | BATL_CACHEINHIBIT \ 523 | BATL_GUARDEDSTORAGE) 524 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 525 | BATU_BL_1M | BATU_VS | BATU_VP) 526 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 527 | BATL_PP_RW | BATL_CACHEINHIBIT) 528 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 529 #endif 530 531 /* 532 * BAT4 PCIE1_IO and PCIE2_IO 533 */ 534 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 535 CONFIG_SYS_PHYS_ADDR_HIGH) \ 536 | BATL_PP_RW | BATL_CACHEINHIBIT \ 537 | BATL_GUARDEDSTORAGE) 538 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 539 | BATU_VS | BATU_VP) 540 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 541 CONFIG_SYS_PHYS_ADDR_HIGH) \ 542 | BATL_PP_RW | BATL_CACHEINHIBIT) 543 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 544 545 /* 546 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 547 */ 548 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 549 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 550 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 551 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 552 553 /* 554 * BAT6 FLASH 555 */ 556 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 557 CONFIG_SYS_PHYS_ADDR_HIGH) \ 558 | BATL_PP_RW | BATL_CACHEINHIBIT \ 559 | BATL_GUARDEDSTORAGE) 560 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 561 | BATU_VP) 562 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 563 CONFIG_SYS_PHYS_ADDR_HIGH) \ 564 | BATL_PP_RW | BATL_MEMCOHERENCE) 565 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 566 567 /* Map the last 1M of flash where we're running from reset */ 568 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 569 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 570 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 571 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 572 | BATL_MEMCOHERENCE) 573 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 574 575 /* 576 * BAT7 FREE - used later for tmp mappings 577 */ 578 #define CONFIG_SYS_DBAT7L 0x00000000 579 #define CONFIG_SYS_DBAT7U 0x00000000 580 #define CONFIG_SYS_IBAT7L 0x00000000 581 #define CONFIG_SYS_IBAT7U 0x00000000 582 583 /* 584 * Environment 585 */ 586 #ifndef CONFIG_SYS_RAMBOOT 587 #define CONFIG_ENV_IS_IN_FLASH 1 588 #define CONFIG_ENV_ADDR \ 589 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 590 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 591 #else 592 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 593 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 594 #endif 595 #define CONFIG_ENV_SIZE 0x2000 596 597 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 598 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 599 600 /* 601 * BOOTP options 602 */ 603 #define CONFIG_BOOTP_BOOTFILESIZE 604 #define CONFIG_BOOTP_BOOTPATH 605 #define CONFIG_BOOTP_GATEWAY 606 #define CONFIG_BOOTP_HOSTNAME 607 608 /* 609 * Command line configuration. 610 */ 611 #define CONFIG_CMD_REGINFO 612 613 #if defined(CONFIG_PCI) 614 #define CONFIG_CMD_PCI 615 #define CONFIG_CMD_SCSI 616 #endif 617 618 #undef CONFIG_WATCHDOG /* watchdog disabled */ 619 620 /* 621 * Miscellaneous configurable options 622 */ 623 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 624 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 625 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 626 627 #if defined(CONFIG_CMD_KGDB) 628 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 629 #else 630 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 631 #endif 632 633 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 634 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 635 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 636 637 /* 638 * For booting Linux, the board info and command line data 639 * have to be in the first 8 MB of memory, since this is 640 * the maximum mapped by the Linux kernel during initialization. 641 */ 642 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 643 644 #if defined(CONFIG_CMD_KGDB) 645 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 646 #endif 647 648 /* 649 * Environment Configuration 650 */ 651 652 #define CONFIG_HAS_ETH0 1 653 #define CONFIG_HAS_ETH1 1 654 #define CONFIG_HAS_ETH2 1 655 #define CONFIG_HAS_ETH3 1 656 657 #define CONFIG_IPADDR 192.168.1.100 658 659 #define CONFIG_HOSTNAME unknown 660 #define CONFIG_ROOTPATH "/opt/nfsroot" 661 #define CONFIG_BOOTFILE "uImage" 662 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 663 664 #define CONFIG_SERVERIP 192.168.1.1 665 #define CONFIG_GATEWAYIP 192.168.1.1 666 #define CONFIG_NETMASK 255.255.255.0 667 668 /* default location for tftp and bootm */ 669 #define CONFIG_LOADADDR 1000000 670 671 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 672 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 673 674 #define CONFIG_BAUDRATE 115200 675 676 #define CONFIG_EXTRA_ENV_SETTINGS \ 677 "netdev=eth0\0" \ 678 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 679 "tftpflash=tftpboot $loadaddr $uboot; " \ 680 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 681 " +$filesize; " \ 682 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 683 " +$filesize; " \ 684 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 685 " $filesize; " \ 686 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 687 " +$filesize; " \ 688 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 689 " $filesize\0" \ 690 "consoledev=ttyS0\0" \ 691 "ramdiskaddr=2000000\0" \ 692 "ramdiskfile=your.ramdisk.u-boot\0" \ 693 "fdtaddr=c00000\0" \ 694 "fdtfile=mpc8641_hpcn.dtb\0" \ 695 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 696 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 697 "maxcpus=2" 698 699 #define CONFIG_NFSBOOTCOMMAND \ 700 "setenv bootargs root=/dev/nfs rw " \ 701 "nfsroot=$serverip:$rootpath " \ 702 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 703 "console=$consoledev,$baudrate $othbootargs;" \ 704 "tftp $loadaddr $bootfile;" \ 705 "tftp $fdtaddr $fdtfile;" \ 706 "bootm $loadaddr - $fdtaddr" 707 708 #define CONFIG_RAMBOOTCOMMAND \ 709 "setenv bootargs root=/dev/ram rw " \ 710 "console=$consoledev,$baudrate $othbootargs;" \ 711 "tftp $ramdiskaddr $ramdiskfile;" \ 712 "tftp $loadaddr $bootfile;" \ 713 "tftp $fdtaddr $fdtfile;" \ 714 "bootm $loadaddr $ramdiskaddr $fdtaddr" 715 716 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 717 718 #endif /* __CONFIG_H */ 719