1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * MPC8641HPCN board configuration file 11 * 12 * Make sure you change the MAC address and other network params first, 13 * search for CONFIG_SERVERIP, etc. in this file. 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MP 1 /* support multiple processors */ 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 23 24 /* 25 * default CCSRBAR is at 0xff700000 26 * assume U-Boot is less than 0.5MB 27 */ 28 #define CONFIG_SYS_TEXT_BASE 0xeff00000 29 30 #ifdef RUN_DIAG 31 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 32 #endif 33 34 /* 35 * virtual address to be used for temporary mappings. There 36 * should be 128k free at this VA. 37 */ 38 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 39 40 #define CONFIG_SYS_SRIO 41 #define CONFIG_SRIO1 /* SRIO port 1 */ 42 43 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ 44 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ 45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 46 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 52 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 53 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 54 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 55 56 #define CONFIG_ALTIVEC 1 57 58 /* 59 * L2CR setup -- make sure this is right for your board! 60 */ 61 #define CONFIG_SYS_L2 62 #define L2_INIT 0 63 #define L2_ENABLE (L2CR_L2E) 64 65 #ifndef CONFIG_SYS_CLK_FREQ 66 #ifndef __ASSEMBLY__ 67 extern unsigned long get_board_sys_clk(unsigned long dummy); 68 #endif 69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 70 #endif 71 72 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 73 #define CONFIG_SYS_MEMTEST_END 0x00400000 74 75 /* 76 * With the exception of PCI Memory and Rapid IO, most devices will simply 77 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 78 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 79 */ 80 #ifdef CONFIG_PHYS_64BIT 81 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f 82 #else 83 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 84 #endif 85 86 /* 87 * Base addresses -- Note these are effective addresses where the 88 * actual resources get mapped (not physical addresses) 89 */ 90 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 91 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 92 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 93 94 /* Physical addresses */ 95 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 96 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH 97 #define CONFIG_SYS_CCSRBAR_PHYS \ 98 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 99 CONFIG_SYS_CCSRBAR_PHYS_HIGH) 100 101 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 102 103 /* 104 * DDR Setup 105 */ 106 #define CONFIG_SYS_FSL_DDR2 107 #undef CONFIG_FSL_DDR_INTERACTIVE 108 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 109 #define CONFIG_DDR_SPD 110 111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 112 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 113 114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 116 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 117 #define CONFIG_VERY_BIG_RAM 118 119 #define CONFIG_NUM_DDR_CONTROLLERS 2 120 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 121 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 122 123 /* 124 * I2C addresses of SPD EEPROMs 125 */ 126 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 127 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 128 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 129 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 130 131 /* 132 * These are used when DDR doesn't use SPD. 133 */ 134 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 135 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 136 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 138 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 139 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 140 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 141 #define CONFIG_SYS_DDR_MODE_1 0x00480432 142 #define CONFIG_SYS_DDR_MODE_2 0x00000000 143 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 144 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 145 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 146 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 147 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 148 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 149 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 150 151 #define CONFIG_ID_EEPROM 152 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_ID_EEPROM 154 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 157 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 158 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE 159 #define CONFIG_SYS_FLASH_BASE_PHYS \ 160 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 161 CONFIG_SYS_PHYS_ADDR_HIGH) 162 163 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 164 165 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 166 | 0x00001001) /* port size 16bit */ 167 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 168 169 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 170 | 0x00001001) /* port size 16bit */ 171 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 172 173 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 174 | 0x00000801) /* port size 8bit */ 175 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 176 177 /* 178 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 179 * The PIXIS and CF by themselves aren't large enough to take up the 128k 180 * required for the smallest BAT mapping, so there's a 64k hole. 181 */ 182 #define CONFIG_SYS_LBC_BASE 0xffde0000 183 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE 184 185 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 186 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 187 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) 188 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ 189 CONFIG_SYS_PHYS_ADDR_HIGH) 190 #define PIXIS_SIZE 0x00008000 /* 32k */ 191 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 192 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 193 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 194 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 195 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 196 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 197 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 198 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 199 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 200 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 201 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 202 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 203 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 204 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 205 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 206 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 207 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 208 209 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 210 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 211 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 212 213 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 214 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 215 216 #undef CONFIG_SYS_FLASH_CHECKSUM 217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 220 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 221 222 #define CONFIG_FLASH_CFI_DRIVER 223 #define CONFIG_SYS_FLASH_CFI 224 #define CONFIG_SYS_FLASH_EMPTY_INFO 225 226 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 227 #define CONFIG_SYS_RAMBOOT 228 #else 229 #undef CONFIG_SYS_RAMBOOT 230 #endif 231 232 #if defined(CONFIG_SYS_RAMBOOT) 233 #undef CONFIG_SPD_EEPROM 234 #define CONFIG_SYS_SDRAM_SIZE 256 235 #endif 236 237 #undef CONFIG_CLOCKS_IN_MHZ 238 239 #define CONFIG_SYS_INIT_RAM_LOCK 1 240 #ifndef CONFIG_SYS_INIT_RAM_LOCK 241 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 242 #else 243 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 244 #endif 245 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 246 247 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 248 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 249 250 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 251 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 252 253 /* Serial Port */ 254 #define CONFIG_CONS_INDEX 1 255 #define CONFIG_SYS_NS16550_SERIAL 256 #define CONFIG_SYS_NS16550_REG_SIZE 1 257 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 258 259 #define CONFIG_SYS_BAUDRATE_TABLE \ 260 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 261 262 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 263 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 264 265 /* 266 * I2C 267 */ 268 #define CONFIG_SYS_I2C 269 #define CONFIG_SYS_I2C_FSL 270 #define CONFIG_SYS_FSL_I2C_SPEED 400000 271 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 272 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 273 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 274 275 /* 276 * RapidIO MMU 277 */ 278 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 279 #ifdef CONFIG_PHYS_64BIT 280 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 281 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c 282 #else 283 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE 284 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 285 #endif 286 #define CONFIG_SYS_SRIO1_MEM_PHYS \ 287 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 288 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) 289 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 290 291 /* 292 * General PCI 293 * Addresses are mapped 1-1. 294 */ 295 296 #define CONFIG_SYS_PCIE1_NAME "ULI" 297 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 298 #ifdef CONFIG_PHYS_64BIT 299 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 300 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 301 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c 302 #else 303 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 304 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT 305 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 306 #endif 307 #define CONFIG_SYS_PCIE1_MEM_PHYS \ 308 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 309 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) 310 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 311 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 312 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 313 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT 314 #define CONFIG_SYS_PCIE1_IO_PHYS \ 315 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 316 CONFIG_SYS_PHYS_ADDR_HIGH) 317 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 318 319 #ifdef CONFIG_PHYS_64BIT 320 /* 321 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 322 * This will increase the amount of PCI address space available for 323 * for mapping RAM. 324 */ 325 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 326 #else 327 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 328 + CONFIG_SYS_PCIE1_MEM_SIZE) 329 #endif 330 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 331 + CONFIG_SYS_PCIE1_MEM_SIZE) 332 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ 333 + CONFIG_SYS_PCIE1_MEM_SIZE) 334 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 335 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 336 + CONFIG_SYS_PCIE1_MEM_SIZE) 337 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 338 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 339 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 340 + CONFIG_SYS_PCIE1_IO_SIZE) 341 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ 342 + CONFIG_SYS_PCIE1_IO_SIZE) 343 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 344 + CONFIG_SYS_PCIE1_IO_SIZE) 345 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 346 347 #if defined(CONFIG_PCI) 348 349 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 350 351 #undef CONFIG_EEPRO100 352 #undef CONFIG_TULIP 353 354 /************************************************************ 355 * USB support 356 ************************************************************/ 357 #define CONFIG_PCI_OHCI 1 358 #define CONFIG_USB_OHCI_NEW 1 359 #define CONFIG_SYS_USB_EVENT_POLL 1 360 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 361 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 362 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 363 364 /*PCIE video card used*/ 365 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 366 367 /*PCI video card used*/ 368 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 369 370 /* video */ 371 372 #if defined(CONFIG_VIDEO) 373 #define CONFIG_BIOSEMU 374 #define CONFIG_ATI_RADEON_FB 375 #define CONFIG_VIDEO_LOGO 376 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 377 #endif 378 379 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 380 381 #define CONFIG_DOS_PARTITION 382 #define CONFIG_SCSI_AHCI 383 384 #ifdef CONFIG_SCSI_AHCI 385 #define CONFIG_LIBATA 386 #define CONFIG_SATA_ULI5288 387 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 388 #define CONFIG_SYS_SCSI_MAX_LUN 1 389 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 390 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 391 #endif 392 393 #endif /* CONFIG_PCI */ 394 395 #if defined(CONFIG_TSEC_ENET) 396 397 #define CONFIG_MII 1 /* MII PHY management */ 398 399 #define CONFIG_TSEC1 1 400 #define CONFIG_TSEC1_NAME "eTSEC1" 401 #define CONFIG_TSEC2 1 402 #define CONFIG_TSEC2_NAME "eTSEC2" 403 #define CONFIG_TSEC3 1 404 #define CONFIG_TSEC3_NAME "eTSEC3" 405 #define CONFIG_TSEC4 1 406 #define CONFIG_TSEC4_NAME "eTSEC4" 407 408 #define TSEC1_PHY_ADDR 0 409 #define TSEC2_PHY_ADDR 1 410 #define TSEC3_PHY_ADDR 2 411 #define TSEC4_PHY_ADDR 3 412 #define TSEC1_PHYIDX 0 413 #define TSEC2_PHYIDX 0 414 #define TSEC3_PHYIDX 0 415 #define TSEC4_PHYIDX 0 416 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 417 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 419 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 420 421 #define CONFIG_ETHPRIME "eTSEC1" 422 423 #endif /* CONFIG_TSEC_ENET */ 424 425 #ifdef CONFIG_PHYS_64BIT 426 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 427 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 428 429 /* Put physical address into the BAT format */ 430 #define BAT_PHYS_ADDR(low, high) \ 431 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) 432 /* Convert high/low pairs to actual 64-bit value */ 433 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) 434 #else 435 /* 32-bit systems just ignore the "high" bits */ 436 #define BAT_PHYS_ADDR(low, high) (low) 437 #define PAIRED_PHYS_TO_PHYS(low, high) (low) 438 #endif 439 440 /* 441 * BAT0 DDR 442 */ 443 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 444 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 445 446 /* 447 * BAT1 LBC (PIXIS/CF) 448 */ 449 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 450 CONFIG_SYS_PHYS_ADDR_HIGH) \ 451 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 452 BATL_GUARDEDSTORAGE) 453 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 454 | BATU_VS | BATU_VP) 455 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 456 CONFIG_SYS_PHYS_ADDR_HIGH) \ 457 | BATL_PP_RW | BATL_MEMCOHERENCE) 458 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 459 460 /* if CONFIG_PCI: 461 * BAT2 PCIE1 and PCIE1 MEM 462 * if CONFIG_RIO 463 * BAT2 Rapidio Memory 464 */ 465 #ifdef CONFIG_PCI 466 #define CONFIG_PCI_INDIRECT_BRIDGE 467 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 468 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 469 | BATL_PP_RW | BATL_CACHEINHIBIT \ 470 | BATL_GUARDEDSTORAGE) 471 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 472 | BATU_VS | BATU_VP) 473 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 474 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 475 | BATL_PP_RW | BATL_CACHEINHIBIT) 476 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 477 #else /* CONFIG_RIO */ 478 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 479 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 480 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 481 BATL_GUARDEDSTORAGE) 482 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 483 | BATU_VS | BATU_VP) 484 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 485 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 486 | BATL_PP_RW | BATL_CACHEINHIBIT) 487 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 488 #endif 489 490 /* 491 * BAT3 CCSR Space 492 */ 493 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 494 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 495 | BATL_PP_RW | BATL_CACHEINHIBIT \ 496 | BATL_GUARDEDSTORAGE) 497 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 498 | BATU_VP) 499 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 500 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 501 | BATL_PP_RW | BATL_CACHEINHIBIT) 502 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 503 504 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 505 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 506 | BATL_PP_RW | BATL_CACHEINHIBIT \ 507 | BATL_GUARDEDSTORAGE) 508 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 509 | BATU_BL_1M | BATU_VS | BATU_VP) 510 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 511 | BATL_PP_RW | BATL_CACHEINHIBIT) 512 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 513 #endif 514 515 /* 516 * BAT4 PCIE1_IO and PCIE2_IO 517 */ 518 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 519 CONFIG_SYS_PHYS_ADDR_HIGH) \ 520 | BATL_PP_RW | BATL_CACHEINHIBIT \ 521 | BATL_GUARDEDSTORAGE) 522 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 523 | BATU_VS | BATU_VP) 524 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 525 CONFIG_SYS_PHYS_ADDR_HIGH) \ 526 | BATL_PP_RW | BATL_CACHEINHIBIT) 527 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 528 529 /* 530 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 531 */ 532 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 533 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 534 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 535 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 536 537 /* 538 * BAT6 FLASH 539 */ 540 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 541 CONFIG_SYS_PHYS_ADDR_HIGH) \ 542 | BATL_PP_RW | BATL_CACHEINHIBIT \ 543 | BATL_GUARDEDSTORAGE) 544 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 545 | BATU_VP) 546 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 547 CONFIG_SYS_PHYS_ADDR_HIGH) \ 548 | BATL_PP_RW | BATL_MEMCOHERENCE) 549 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 550 551 /* Map the last 1M of flash where we're running from reset */ 552 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 553 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 554 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 555 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 556 | BATL_MEMCOHERENCE) 557 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 558 559 /* 560 * BAT7 FREE - used later for tmp mappings 561 */ 562 #define CONFIG_SYS_DBAT7L 0x00000000 563 #define CONFIG_SYS_DBAT7U 0x00000000 564 #define CONFIG_SYS_IBAT7L 0x00000000 565 #define CONFIG_SYS_IBAT7U 0x00000000 566 567 /* 568 * Environment 569 */ 570 #ifndef CONFIG_SYS_RAMBOOT 571 #define CONFIG_ENV_IS_IN_FLASH 1 572 #define CONFIG_ENV_ADDR \ 573 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 574 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 575 #else 576 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 577 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 578 #endif 579 #define CONFIG_ENV_SIZE 0x2000 580 581 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 582 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 583 584 /* 585 * BOOTP options 586 */ 587 #define CONFIG_BOOTP_BOOTFILESIZE 588 #define CONFIG_BOOTP_BOOTPATH 589 #define CONFIG_BOOTP_GATEWAY 590 #define CONFIG_BOOTP_HOSTNAME 591 592 /* 593 * Command line configuration. 594 */ 595 #define CONFIG_CMD_REGINFO 596 597 #if defined(CONFIG_PCI) 598 #define CONFIG_CMD_PCI 599 #define CONFIG_SCSI 600 #endif 601 602 #undef CONFIG_WATCHDOG /* watchdog disabled */ 603 604 /* 605 * Miscellaneous configurable options 606 */ 607 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 608 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 609 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 610 611 #if defined(CONFIG_CMD_KGDB) 612 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 613 #else 614 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 615 #endif 616 617 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 618 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 619 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 620 621 /* 622 * For booting Linux, the board info and command line data 623 * have to be in the first 8 MB of memory, since this is 624 * the maximum mapped by the Linux kernel during initialization. 625 */ 626 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 627 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 628 629 #if defined(CONFIG_CMD_KGDB) 630 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 631 #endif 632 633 /* 634 * Environment Configuration 635 */ 636 637 #define CONFIG_HAS_ETH0 1 638 #define CONFIG_HAS_ETH1 1 639 #define CONFIG_HAS_ETH2 1 640 #define CONFIG_HAS_ETH3 1 641 642 #define CONFIG_IPADDR 192.168.1.100 643 644 #define CONFIG_HOSTNAME unknown 645 #define CONFIG_ROOTPATH "/opt/nfsroot" 646 #define CONFIG_BOOTFILE "uImage" 647 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 648 649 #define CONFIG_SERVERIP 192.168.1.1 650 #define CONFIG_GATEWAYIP 192.168.1.1 651 #define CONFIG_NETMASK 255.255.255.0 652 653 /* default location for tftp and bootm */ 654 #define CONFIG_LOADADDR 0x10000000 655 656 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 657 658 #define CONFIG_BAUDRATE 115200 659 660 #define CONFIG_EXTRA_ENV_SETTINGS \ 661 "netdev=eth0\0" \ 662 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 663 "tftpflash=tftpboot $loadaddr $uboot; " \ 664 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 665 " +$filesize; " \ 666 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 667 " +$filesize; " \ 668 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 669 " $filesize; " \ 670 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 671 " +$filesize; " \ 672 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 673 " $filesize\0" \ 674 "consoledev=ttyS0\0" \ 675 "ramdiskaddr=0x18000000\0" \ 676 "ramdiskfile=your.ramdisk.u-boot\0" \ 677 "fdtaddr=0x17c00000\0" \ 678 "fdtfile=mpc8641_hpcn.dtb\0" \ 679 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 680 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 681 "maxcpus=2" 682 683 #define CONFIG_NFSBOOTCOMMAND \ 684 "setenv bootargs root=/dev/nfs rw " \ 685 "nfsroot=$serverip:$rootpath " \ 686 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 687 "console=$consoledev,$baudrate $othbootargs;" \ 688 "tftp $loadaddr $bootfile;" \ 689 "tftp $fdtaddr $fdtfile;" \ 690 "bootm $loadaddr - $fdtaddr" 691 692 #define CONFIG_RAMBOOTCOMMAND \ 693 "setenv bootargs root=/dev/ram rw " \ 694 "console=$consoledev,$baudrate $othbootargs;" \ 695 "tftp $ramdiskaddr $ramdiskfile;" \ 696 "tftp $loadaddr $bootfile;" \ 697 "tftp $fdtaddr $fdtfile;" \ 698 "bootm $loadaddr $ramdiskaddr $fdtaddr" 699 700 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 701 702 #endif /* __CONFIG_H */ 703