1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 42 #ifdef RUN_DIAG 43 #define CFG_DIAG_ADDR 0xff800000 44 #endif 45 46 #define CFG_RESET_ADDRESS 0xfff00100 47 48 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 49 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ 50 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ 51 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 52 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 57 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 58 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 59 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 60 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 61 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 62 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 63 #define CONFIG_NUM_DDR_CONTROLLERS 2 64 /* #define CONFIG_DDR_INTERLEAVE 1 */ 65 #define CACHE_LINE_INTERLEAVING 0x20000000 66 #define PAGE_INTERLEAVING 0x21000000 67 #define BANK_INTERLEAVING 0x22000000 68 #define SUPER_BANK_INTERLEAVING 0x23000000 69 70 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 71 72 #define CONFIG_ALTIVEC 1 73 74 /* 75 * L2CR setup -- make sure this is right for your board! 76 */ 77 #define CFG_L2 78 #define L2_INIT 0 79 #define L2_ENABLE (L2CR_L2E) 80 81 #ifndef CONFIG_SYS_CLK_FREQ 82 #ifndef __ASSEMBLY__ 83 extern unsigned long get_board_sys_clk(unsigned long dummy); 84 #endif 85 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 86 #endif 87 88 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 89 90 #undef CFG_DRAM_TEST /* memory test, takes time */ 91 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 92 #define CFG_MEMTEST_END 0x00400000 93 94 /* 95 * Base addresses -- Note these are effective addresses where the 96 * actual resources get mapped (not physical addresses) 97 */ 98 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 99 #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 100 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 101 102 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 103 #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) 104 105 /* 106 * DDR Setup 107 */ 108 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 109 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 110 #define CONFIG_VERY_BIG_RAM 111 112 #define MPC86xx_DDR_SDRAM_CLK_CNTL 113 114 #if defined(CONFIG_SPD_EEPROM) 115 /* 116 * Determine DDR configuration from I2C interface. 117 */ 118 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 119 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 120 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 121 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 122 123 #else 124 /* 125 * Manually set up DDR1 parameters 126 */ 127 128 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 129 130 #define CFG_DDR_CS0_BNDS 0x0000000F 131 #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 132 #define CFG_DDR_EXT_REFRESH 0x00000000 133 #define CFG_DDR_TIMING_0 0x00260802 134 #define CFG_DDR_TIMING_1 0x39357322 135 #define CFG_DDR_TIMING_2 0x14904cc8 136 #define CFG_DDR_MODE_1 0x00480432 137 #define CFG_DDR_MODE_2 0x00000000 138 #define CFG_DDR_INTERVAL 0x06090100 139 #define CFG_DDR_DATA_INIT 0xdeadbeef 140 #define CFG_DDR_CLK_CTRL 0x03800000 141 #define CFG_DDR_OCD_CTRL 0x00000000 142 #define CFG_DDR_OCD_STATUS 0x00000000 143 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 144 #define CFG_DDR_CONTROL2 0x04400000 145 146 /* Not used in fixed_sdram function */ 147 148 #define CFG_DDR_MODE 0x00000022 149 #define CFG_DDR_CS1_BNDS 0x00000000 150 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 151 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 152 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 153 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 154 #endif 155 156 #define CFG_ID_EEPROM 1 157 #ifdef CFG_ID_EEPROM 158 #define CONFIG_ID_EEPROM 159 #endif 160 #define ID_EEPROM_ADDR 0x57 161 162 /* 163 * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. 164 * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff 165 * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. 166 * However, when u-boot comes up, the flash_init needs hard start addresses 167 * to build its info table. For user convenience, the flash addresses is 168 * fe800000 and ff800000. That way, u-boot knows where the flash is 169 * and the user can download u-boot code from promjet to fef00000, a 170 * more intuitive location than fe700000. 171 * 172 * Note that, on switching the boot location, fef00000 becomes fff00000. 173 */ 174 #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ 175 #define CFG_FLASH_BASE2 0xff800000 176 177 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 178 179 #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ 180 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ 181 182 #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ 183 #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ 184 185 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 186 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 187 188 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 189 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 190 191 192 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 193 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 194 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 195 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 196 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 197 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 198 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 199 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 200 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 201 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 202 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 203 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 204 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 205 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 206 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 207 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 208 #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 209 210 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 211 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 212 213 #undef CFG_FLASH_CHECKSUM 214 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 215 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 216 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 217 218 #define CFG_FLASH_CFI_DRIVER 219 #define CFG_FLASH_CFI 220 #define CFG_FLASH_EMPTY_INFO 221 222 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 223 #define CFG_RAMBOOT 224 #else 225 #undef CFG_RAMBOOT 226 #endif 227 228 #if defined(CFG_RAMBOOT) 229 #undef CONFIG_SPD_EEPROM 230 #define CFG_SDRAM_SIZE 256 231 #endif 232 233 #undef CONFIG_CLOCKS_IN_MHZ 234 235 #define CONFIG_L1_INIT_RAM 236 #define CFG_INIT_RAM_LOCK 1 237 #ifndef CFG_INIT_RAM_LOCK 238 #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 239 #else 240 #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 241 #endif 242 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 243 244 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 245 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 246 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 247 248 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 249 #define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 250 251 /* Serial Port */ 252 #define CONFIG_CONS_INDEX 1 253 #undef CONFIG_SERIAL_SOFTWARE_FIFO 254 #define CFG_NS16550 255 #define CFG_NS16550_SERIAL 256 #define CFG_NS16550_REG_SIZE 1 257 #define CFG_NS16550_CLK get_bus_freq(0) 258 259 #define CFG_BAUDRATE_TABLE \ 260 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 261 262 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 263 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 264 265 /* Use the HUSH parser */ 266 #define CFG_HUSH_PARSER 267 #ifdef CFG_HUSH_PARSER 268 #define CFG_PROMPT_HUSH_PS2 "> " 269 #endif 270 271 /* 272 * Pass open firmware flat tree to kernel 273 */ 274 #define CONFIG_OF_LIBFDT 1 275 #define CONFIG_OF_BOARD_SETUP 1 276 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 277 278 279 #define CFG_64BIT_VSPRINTF 1 280 #define CFG_64BIT_STRTOUL 1 281 282 /* 283 * I2C 284 */ 285 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 286 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 287 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 288 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 289 #define CFG_I2C_SLAVE 0x7F 290 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 291 #define CFG_I2C_OFFSET 0x3100 292 293 /* 294 * RapidIO MMU 295 */ 296 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 297 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 298 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 299 300 /* 301 * General PCI 302 * Addresses are mapped 1-1. 303 */ 304 #define CFG_PCI1_MEM_BASE 0x80000000 305 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 306 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 307 #define CFG_PCI1_IO_BASE 0x00000000 308 #define CFG_PCI1_IO_PHYS 0xe2000000 309 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 310 311 /* PCI view of System Memory */ 312 #define CFG_PCI_MEMORY_BUS 0x00000000 313 #define CFG_PCI_MEMORY_PHYS 0x00000000 314 #define CFG_PCI_MEMORY_SIZE 0x80000000 315 316 /* For RTL8139 */ 317 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 318 #define _IO_BASE 0x00000000 319 320 #define CFG_PCI2_MEM_BASE 0xa0000000 321 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 322 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 323 #define CFG_PCI2_IO_BASE 0x00000000 324 #define CFG_PCI2_IO_PHYS 0xe3000000 325 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 326 327 #if defined(CONFIG_PCI) 328 329 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 330 331 #undef CFG_SCSI_SCAN_BUS_REVERSE 332 333 #define CONFIG_NET_MULTI 334 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 335 336 #define CONFIG_RTL8139 337 338 #undef CONFIG_EEPRO100 339 #undef CONFIG_TULIP 340 341 /************************************************************ 342 * USB support 343 ************************************************************/ 344 #define CONFIG_PCI_OHCI 1 345 #define CONFIG_USB_OHCI_NEW 1 346 #define CONFIG_USB_KEYBOARD 1 347 #define CFG_DEVICE_DEREGISTER 348 #define CFG_USB_EVENT_POLL 1 349 #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" 350 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 351 #define CFG_OHCI_SWAP_REG_ACCESS 1 352 353 #if !defined(CONFIG_PCI_PNP) 354 #define PCI_ENET0_IOADDR 0xe0000000 355 #define PCI_ENET0_MEMADDR 0xe0000000 356 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 357 #endif 358 359 /*PCIE video card used*/ 360 #define VIDEO_IO_OFFSET CFG_PCI2_IO_PHYS 361 362 /*PCI video card used*/ 363 /*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ 364 365 /* video */ 366 #define CONFIG_VIDEO 367 368 #if defined(CONFIG_VIDEO) 369 #define CONFIG_BIOSEMU 370 #define CONFIG_CFB_CONSOLE 371 #define CONFIG_VIDEO_SW_CURSOR 372 #define CONFIG_VGA_AS_SINGLE_DEVICE 373 #define CONFIG_ATI_RADEON_FB 374 #define CONFIG_VIDEO_LOGO 375 /*#define CONFIG_CONSOLE_CURSOR*/ 376 #define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS 377 #endif 378 379 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 380 381 #define CONFIG_DOS_PARTITION 382 #define CONFIG_SCSI_AHCI 383 384 #ifdef CONFIG_SCSI_AHCI 385 #define CONFIG_SATA_ULI5288 386 #define CFG_SCSI_MAX_SCSI_ID 4 387 #define CFG_SCSI_MAX_LUN 1 388 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 389 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 390 #endif 391 392 #define CONFIG_MPC86XX_PCI2 393 394 #endif /* CONFIG_PCI */ 395 396 #if defined(CONFIG_TSEC_ENET) 397 398 #ifndef CONFIG_NET_MULTI 399 #define CONFIG_NET_MULTI 1 400 #endif 401 402 #define CONFIG_MII 1 /* MII PHY management */ 403 404 #define CONFIG_TSEC1 1 405 #define CONFIG_TSEC1_NAME "eTSEC1" 406 #define CONFIG_TSEC2 1 407 #define CONFIG_TSEC2_NAME "eTSEC2" 408 #define CONFIG_TSEC3 1 409 #define CONFIG_TSEC3_NAME "eTSEC3" 410 #define CONFIG_TSEC4 1 411 #define CONFIG_TSEC4_NAME "eTSEC4" 412 413 #define TSEC1_PHY_ADDR 0 414 #define TSEC2_PHY_ADDR 1 415 #define TSEC3_PHY_ADDR 2 416 #define TSEC4_PHY_ADDR 3 417 #define TSEC1_PHYIDX 0 418 #define TSEC2_PHYIDX 0 419 #define TSEC3_PHYIDX 0 420 #define TSEC4_PHYIDX 0 421 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 422 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 424 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 425 426 #define CONFIG_ETHPRIME "eTSEC1" 427 428 #endif /* CONFIG_TSEC_ENET */ 429 430 /* 431 * BAT0 2G Cacheable, non-guarded 432 * 0x0000_0000 2G DDR 433 */ 434 #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 435 #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 436 #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 437 #define CFG_IBAT0U CFG_DBAT0U 438 439 /* 440 * BAT1 1G Cache-inhibited, guarded 441 * 0x8000_0000 512M PCI-Express 1 Memory 442 * 0xa000_0000 512M PCI-Express 2 Memory 443 * Changed it for operating from 0xd0000000 444 */ 445 #define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ 446 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 447 #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) 448 #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 449 #define CFG_IBAT1U CFG_DBAT1U 450 451 /* 452 * BAT2 512M Cache-inhibited, guarded 453 * 0xc000_0000 512M RapidIO Memory 454 */ 455 #define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ 456 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 457 #define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 458 #define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 459 #define CFG_IBAT2U CFG_DBAT2U 460 461 /* 462 * BAT3 4M Cache-inhibited, guarded 463 * 0xf800_0000 4M CCSR 464 */ 465 #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ 466 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 467 #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 468 #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 469 #define CFG_IBAT3U CFG_DBAT3U 470 471 /* 472 * BAT4 32M Cache-inhibited, guarded 473 * 0xe200_0000 16M PCI-Express 1 I/O 474 * 0xe300_0000 16M PCI-Express 2 I/0 475 * Note that this is at 0xe0000000 476 */ 477 #define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ 478 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 479 #define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 480 #define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 481 #define CFG_IBAT4U CFG_DBAT4U 482 483 /* 484 * BAT5 128K Cacheable, non-guarded 485 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 486 */ 487 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 488 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 489 #define CFG_IBAT5L CFG_DBAT5L 490 #define CFG_IBAT5U CFG_DBAT5U 491 492 /* 493 * BAT6 32M Cache-inhibited, guarded 494 * 0xfe00_0000 32M FLASH 495 */ 496 #define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 497 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 498 #define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 499 #define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 500 #define CFG_IBAT6U CFG_DBAT6U 501 502 #define CFG_DBAT7L 0x00000000 503 #define CFG_DBAT7U 0x00000000 504 #define CFG_IBAT7L 0x00000000 505 #define CFG_IBAT7U 0x00000000 506 507 /* 508 * Environment 509 */ 510 #ifndef CFG_RAMBOOT 511 #define CFG_ENV_IS_IN_FLASH 1 512 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) 513 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 514 #define CFG_ENV_SIZE 0x2000 515 #else 516 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 517 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 518 #define CFG_ENV_SIZE 0x2000 519 #endif 520 521 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 522 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 523 524 525 /* 526 * BOOTP options 527 */ 528 #define CONFIG_BOOTP_BOOTFILESIZE 529 #define CONFIG_BOOTP_BOOTPATH 530 #define CONFIG_BOOTP_GATEWAY 531 #define CONFIG_BOOTP_HOSTNAME 532 533 534 /* 535 * Command line configuration. 536 */ 537 #include <config_cmd_default.h> 538 539 #define CONFIG_CMD_PING 540 #define CONFIG_CMD_I2C 541 #define CONFIG_CMD_REGINFO 542 543 #if defined(CFG_RAMBOOT) 544 #undef CONFIG_CMD_ENV 545 #endif 546 547 #if defined(CONFIG_PCI) 548 #define CONFIG_CMD_PCI 549 #define CONFIG_CMD_SCSI 550 #define CONFIG_CMD_EXT2 551 #define CONFIG_CMD_USB 552 #endif 553 554 555 #undef CONFIG_WATCHDOG /* watchdog disabled */ 556 557 /* 558 * Miscellaneous configurable options 559 */ 560 #define CFG_LONGHELP /* undef to save memory */ 561 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 562 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 563 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 564 565 #if defined(CONFIG_CMD_KGDB) 566 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 567 #else 568 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 569 #endif 570 571 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 572 #define CFG_MAXARGS 16 /* max number of command args */ 573 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 574 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 575 576 /* 577 * For booting Linux, the board info and command line data 578 * have to be in the first 8 MB of memory, since this is 579 * the maximum mapped by the Linux kernel during initialization. 580 */ 581 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 582 583 /* 584 * Internal Definitions 585 * 586 * Boot Flags 587 */ 588 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 589 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 590 591 #if defined(CONFIG_CMD_KGDB) 592 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 593 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 594 #endif 595 596 /* 597 * Environment Configuration 598 */ 599 600 /* The mac addresses for all ethernet interface */ 601 #if defined(CONFIG_TSEC_ENET) 602 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 603 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 604 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 605 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 606 #endif 607 608 #define CONFIG_HAS_ETH0 1 609 #define CONFIG_HAS_ETH1 1 610 #define CONFIG_HAS_ETH2 1 611 #define CONFIG_HAS_ETH3 1 612 613 #define CONFIG_IPADDR 192.168.1.100 614 615 #define CONFIG_HOSTNAME unknown 616 #define CONFIG_ROOTPATH /opt/nfsroot 617 #define CONFIG_BOOTFILE uImage 618 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 619 620 #define CONFIG_SERVERIP 192.168.1.1 621 #define CONFIG_GATEWAYIP 192.168.1.1 622 #define CONFIG_NETMASK 255.255.255.0 623 624 /* default location for tftp and bootm */ 625 #define CONFIG_LOADADDR 1000000 626 627 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 628 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 629 630 #define CONFIG_BAUDRATE 115200 631 632 #define CONFIG_EXTRA_ENV_SETTINGS \ 633 "netdev=eth0\0" \ 634 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 635 "tftpflash=tftpboot $loadaddr $uboot; " \ 636 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 637 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 638 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 639 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 640 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 641 "consoledev=ttyS0\0" \ 642 "ramdiskaddr=2000000\0" \ 643 "ramdiskfile=your.ramdisk.u-boot\0" \ 644 "fdtaddr=c00000\0" \ 645 "fdtfile=mpc8641_hpcn.dtb\0" \ 646 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 647 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 648 "maxcpus=2" 649 650 651 #define CONFIG_NFSBOOTCOMMAND \ 652 "setenv bootargs root=/dev/nfs rw " \ 653 "nfsroot=$serverip:$rootpath " \ 654 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 655 "console=$consoledev,$baudrate $othbootargs;" \ 656 "tftp $loadaddr $bootfile;" \ 657 "tftp $fdtaddr $fdtfile;" \ 658 "bootm $loadaddr - $fdtaddr" 659 660 #define CONFIG_RAMBOOTCOMMAND \ 661 "setenv bootargs root=/dev/ram rw " \ 662 "console=$consoledev,$baudrate $othbootargs;" \ 663 "tftp $ramdiskaddr $ramdiskfile;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr $ramdiskaddr $fdtaddr" 667 668 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 669 670 #endif /* __CONFIG_H */ 671