1 /*
2  * Copyright 2006, 2010-2011 Freescale Semiconductor.
3  *
4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 /*
26  * MPC8641HPCN board configuration file
27  *
28  * Make sure you change the MAC address and other network params first,
29  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
30  */
31 
32 #ifndef __CONFIG_H
33 #define __CONFIG_H
34 
35 /* High Level Configuration Options */
36 #define CONFIG_MPC86xx		1	/* MPC86xx */
37 #define CONFIG_MPC8641		1	/* MPC8641 specific */
38 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
39 #define CONFIG_MP		1	/* support multiple processors */
40 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
41 /*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
42 #define CONFIG_ADDR_MAP		1	/* Use addr map */
43 
44 /*
45  * default CCSRBAR is at 0xff700000
46  * assume U-Boot is less than 0.5MB
47  */
48 #define	CONFIG_SYS_TEXT_BASE	0xeff00000
49 
50 #ifdef RUN_DIAG
51 #define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
52 #endif
53 
54 /*
55  * virtual address to be used for temporary mappings.  There
56  * should be 128k free at this VA.
57  */
58 #define CONFIG_SYS_SCRATCH_VA	0xe0000000
59 
60 #define CONFIG_SYS_SRIO
61 #define CONFIG_SRIO1			/* SRIO port 1 */
62 
63 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
64 #define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
65 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
66 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
67 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
68 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
69 
70 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
71 #define CONFIG_ENV_OVERWRITE
72 
73 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
74 #define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
75 #define CONFIG_SYS_NUM_ADDR_MAP 8	/* Number of addr map slots = 8 dbats */
76 
77 #define CONFIG_ALTIVEC		1
78 
79 /*
80  * L2CR setup -- make sure this is right for your board!
81  */
82 #define CONFIG_SYS_L2
83 #define L2_INIT		0
84 #define L2_ENABLE	(L2CR_L2E)
85 
86 #ifndef CONFIG_SYS_CLK_FREQ
87 #ifndef __ASSEMBLY__
88 extern unsigned long get_board_sys_clk(unsigned long dummy);
89 #endif
90 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
91 #endif
92 
93 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
94 #define CONFIG_SYS_MEMTEST_END		0x00400000
95 
96 /*
97  * With the exception of PCI Memory and Rapid IO, most devices will simply
98  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
99  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
100  */
101 #ifdef CONFIG_PHYS_64BIT
102 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
103 #else
104 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
105 #endif
106 
107 /*
108  * Base addresses -- Note these are effective addresses where the
109  * actual resources get mapped (not physical addresses)
110  */
111 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
112 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
113 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
114 
115 /* Physical addresses */
116 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
117 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
118 #define CONFIG_SYS_CCSRBAR_PHYS \
119 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
120 			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
121 
122 #define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
123 
124 /*
125  * DDR Setup
126  */
127 #define CONFIG_FSL_DDR2
128 #undef CONFIG_FSL_DDR_INTERACTIVE
129 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
130 #define CONFIG_DDR_SPD
131 
132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
133 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
134 
135 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
136 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
137 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
138 #define CONFIG_VERY_BIG_RAM
139 
140 #define CONFIG_NUM_DDR_CONTROLLERS	2
141 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
142 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
143 
144 /*
145  * I2C addresses of SPD EEPROMs
146  */
147 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
148 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
149 #define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
150 #define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
151 
152 
153 /*
154  * These are used when DDR doesn't use SPD.
155  */
156 #define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
157 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
158 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
159 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
160 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
161 #define CONFIG_SYS_DDR_TIMING_1	0x39357322
162 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
163 #define CONFIG_SYS_DDR_MODE_1		0x00480432
164 #define CONFIG_SYS_DDR_MODE_2		0x00000000
165 #define CONFIG_SYS_DDR_INTERVAL	0x06090100
166 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
167 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
168 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
169 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
170 #define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
171 #define CONFIG_SYS_DDR_CONTROL2	0x04400000
172 
173 #define CONFIG_ID_EEPROM
174 #define CONFIG_SYS_I2C_EEPROM_NXID
175 #define CONFIG_ID_EEPROM
176 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
177 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
178 
179 #define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
180 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
181 #define CONFIG_SYS_FLASH_BASE_PHYS \
182 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
183 			    CONFIG_SYS_PHYS_ADDR_HIGH)
184 
185 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
186 
187 #define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
188 				 | 0x00001001)	/* port size 16bit */
189 #define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
190 
191 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
192 				 | 0x00001001)	/* port size 16bit */
193 #define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
194 
195 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
196 				 | 0x00000801) /* port size 8bit */
197 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
198 
199 /*
200  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
201  * The PIXIS and CF by themselves aren't large enough to take up the 128k
202  * required for the smallest BAT mapping, so there's a 64k hole.
203  */
204 #define CONFIG_SYS_LBC_BASE		0xffde0000
205 #define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
206 
207 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
208 #define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
209 #define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
210 #define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
211 						    CONFIG_SYS_PHYS_ADDR_HIGH)
212 #define PIXIS_SIZE		0x00008000	/* 32k */
213 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
214 #define PIXIS_VER		0x1	/* Board version at offset 1 */
215 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
216 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
217 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
218 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
219 #define PIXIS_VCTL		0x10	/* VELA Control Register */
220 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
221 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
222 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
223 #define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
224 #define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
225 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
226 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
227 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
228 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
229 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
230 
231 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
232 #define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
233 #define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
234 
235 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
236 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
237 
238 #undef	CONFIG_SYS_FLASH_CHECKSUM
239 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
240 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
241 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
242 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
243 
244 #define CONFIG_FLASH_CFI_DRIVER
245 #define CONFIG_SYS_FLASH_CFI
246 #define CONFIG_SYS_FLASH_EMPTY_INFO
247 
248 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
249 #define CONFIG_SYS_RAMBOOT
250 #else
251 #undef	CONFIG_SYS_RAMBOOT
252 #endif
253 
254 #if defined(CONFIG_SYS_RAMBOOT)
255 #undef CONFIG_SPD_EEPROM
256 #define CONFIG_SYS_SDRAM_SIZE	256
257 #endif
258 
259 #undef CONFIG_CLOCKS_IN_MHZ
260 
261 #define CONFIG_SYS_INIT_RAM_LOCK	1
262 #ifndef CONFIG_SYS_INIT_RAM_LOCK
263 #define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
264 #else
265 #define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
266 #endif
267 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
268 
269 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
270 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
271 
272 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
273 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
274 
275 /* Serial Port */
276 #define CONFIG_CONS_INDEX     1
277 #define CONFIG_SYS_NS16550
278 #define CONFIG_SYS_NS16550_SERIAL
279 #define CONFIG_SYS_NS16550_REG_SIZE	1
280 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
281 
282 #define CONFIG_SYS_BAUDRATE_TABLE  \
283 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
284 
285 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
286 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
287 
288 /* Use the HUSH parser */
289 #define CONFIG_SYS_HUSH_PARSER
290 
291 /*
292  * Pass open firmware flat tree to kernel
293  */
294 #define CONFIG_OF_LIBFDT		1
295 #define CONFIG_OF_BOARD_SETUP		1
296 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
297 
298 /*
299  * I2C
300  */
301 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
302 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
303 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
304 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
305 #define CONFIG_SYS_I2C_SLAVE		0x7F
306 #define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
307 #define CONFIG_SYS_I2C_OFFSET		0x3100
308 
309 /*
310  * RapidIO MMU
311  */
312 #define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
313 #ifdef CONFIG_PHYS_64BIT
314 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
315 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
316 #else
317 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
318 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
319 #endif
320 #define CONFIG_SYS_SRIO1_MEM_PHYS \
321 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
322 			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
323 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
324 
325 /*
326  * General PCI
327  * Addresses are mapped 1-1.
328  */
329 
330 #define CONFIG_SYS_PCIE1_NAME		"ULI"
331 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
332 #ifdef CONFIG_PHYS_64BIT
333 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
334 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
335 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
336 #else
337 #define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
338 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
339 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
340 #endif
341 #define CONFIG_SYS_PCIE1_MEM_PHYS \
342 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
343 			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
344 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
345 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
346 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
347 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
348 #define CONFIG_SYS_PCIE1_IO_PHYS \
349 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
350 			    CONFIG_SYS_PHYS_ADDR_HIGH)
351 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
352 
353 #ifdef CONFIG_PHYS_64BIT
354 /*
355  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
356  * This will increase the amount of PCI address space available for
357  * for mapping RAM.
358  */
359 #define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
360 #else
361 #define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
362 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
363 #endif
364 #define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
365 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
366 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
367 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
368 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
369 #define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
370 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
371 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
372 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
373 #define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
374 					 + CONFIG_SYS_PCIE1_IO_SIZE)
375 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
376 					 + CONFIG_SYS_PCIE1_IO_SIZE)
377 #define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
378 					 + CONFIG_SYS_PCIE1_IO_SIZE)
379 #define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
380 
381 #if defined(CONFIG_PCI)
382 
383 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
384 
385 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
386 
387 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
388 
389 #define CONFIG_RTL8139
390 
391 #undef CONFIG_EEPRO100
392 #undef CONFIG_TULIP
393 
394 /************************************************************
395  * USB support
396  ************************************************************/
397 #define CONFIG_PCI_OHCI			1
398 #define CONFIG_USB_OHCI_NEW		1
399 #define CONFIG_USB_KEYBOARD		1
400 #define CONFIG_SYS_STDIO_DEREGISTER
401 #define CONFIG_SYS_USB_EVENT_POLL		1
402 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
403 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
404 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
405 
406 /*PCIE video card used*/
407 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
408 
409 /*PCI video card used*/
410 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
411 
412 /* video */
413 #define CONFIG_VIDEO
414 
415 #if defined(CONFIG_VIDEO)
416 #define CONFIG_BIOSEMU
417 #define CONFIG_CFB_CONSOLE
418 #define CONFIG_VIDEO_SW_CURSOR
419 #define CONFIG_VGA_AS_SINGLE_DEVICE
420 #define CONFIG_ATI_RADEON_FB
421 #define CONFIG_VIDEO_LOGO
422 /*#define CONFIG_CONSOLE_CURSOR*/
423 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
424 #endif
425 
426 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
427 
428 #define CONFIG_DOS_PARTITION
429 #define CONFIG_SCSI_AHCI
430 
431 #ifdef CONFIG_SCSI_AHCI
432 #define CONFIG_SATA_ULI5288
433 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
434 #define CONFIG_SYS_SCSI_MAX_LUN	1
435 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
436 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
437 #endif
438 
439 #endif	/* CONFIG_PCI */
440 
441 #if defined(CONFIG_TSEC_ENET)
442 
443 #define CONFIG_MII		1	/* MII PHY management */
444 
445 #define CONFIG_TSEC1		1
446 #define CONFIG_TSEC1_NAME	"eTSEC1"
447 #define CONFIG_TSEC2		1
448 #define CONFIG_TSEC2_NAME	"eTSEC2"
449 #define CONFIG_TSEC3		1
450 #define CONFIG_TSEC3_NAME	"eTSEC3"
451 #define CONFIG_TSEC4		1
452 #define CONFIG_TSEC4_NAME	"eTSEC4"
453 
454 #define TSEC1_PHY_ADDR		0
455 #define TSEC2_PHY_ADDR		1
456 #define TSEC3_PHY_ADDR		2
457 #define TSEC4_PHY_ADDR		3
458 #define TSEC1_PHYIDX		0
459 #define TSEC2_PHYIDX		0
460 #define TSEC3_PHYIDX		0
461 #define TSEC4_PHYIDX		0
462 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
463 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
464 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
465 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
466 
467 #define CONFIG_ETHPRIME		"eTSEC1"
468 
469 #endif	/* CONFIG_TSEC_ENET */
470 
471 
472 #ifdef CONFIG_PHYS_64BIT
473 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
474 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
475 
476 /* Put physical address into the BAT format */
477 #define BAT_PHYS_ADDR(low, high) \
478 	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
479 /* Convert high/low pairs to actual 64-bit value */
480 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
481 #else
482 /* 32-bit systems just ignore the "high" bits */
483 #define BAT_PHYS_ADDR(low, high)        (low)
484 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
485 #endif
486 
487 /*
488  * BAT0		DDR
489  */
490 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
491 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
492 
493 /*
494  * BAT1		LBC (PIXIS/CF)
495  */
496 #define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
497 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
498 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
499 				 BATL_GUARDEDSTORAGE)
500 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
501 				 | BATU_VS | BATU_VP)
502 #define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
503 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
504 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
505 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
506 
507 /* if CONFIG_PCI:
508  * BAT2		PCIE1 and PCIE1 MEM
509  * if CONFIG_RIO
510  * BAT2		Rapidio Memory
511  */
512 #ifdef CONFIG_PCI
513 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
514 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
515 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
516 				 | BATL_GUARDEDSTORAGE)
517 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
518 				 | BATU_VS | BATU_VP)
519 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
520 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
521 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
522 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
523 #else /* CONFIG_RIO */
524 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
525 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
526 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
527 				 BATL_GUARDEDSTORAGE)
528 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
529 				 | BATU_VS | BATU_VP)
530 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
531 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
532 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
533 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
534 #endif
535 
536 /*
537  * BAT3		CCSR Space
538  */
539 #define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
540 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
541 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
542 				 | BATL_GUARDEDSTORAGE)
543 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
544 				 | BATU_VP)
545 #define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
546 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
547 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
548 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
549 
550 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
551 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
552 				       | BATL_PP_RW | BATL_CACHEINHIBIT \
553 				       | BATL_GUARDEDSTORAGE)
554 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
555 				       | BATU_BL_1M | BATU_VS | BATU_VP)
556 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
557 				       | BATL_PP_RW | BATL_CACHEINHIBIT)
558 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
559 #endif
560 
561 /*
562  * BAT4		PCIE1_IO and PCIE2_IO
563  */
564 #define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
565 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
566 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
567 				 | BATL_GUARDEDSTORAGE)
568 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
569 				 | BATU_VS | BATU_VP)
570 #define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
571 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
572 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
573 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
574 
575 /*
576  * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
577  */
578 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
579 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
580 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
581 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
582 
583 /*
584  * BAT6		FLASH
585  */
586 #define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
587 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
588 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
589 				 | BATL_GUARDEDSTORAGE)
590 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
591 				 | BATU_VP)
592 #define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
593 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
594 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
595 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
596 
597 /* Map the last 1M of flash where we're running from reset */
598 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
599 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
600 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
601 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
602 				 | BATL_MEMCOHERENCE)
603 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
604 
605 /*
606  * BAT7		FREE - used later for tmp mappings
607  */
608 #define CONFIG_SYS_DBAT7L 0x00000000
609 #define CONFIG_SYS_DBAT7U 0x00000000
610 #define CONFIG_SYS_IBAT7L 0x00000000
611 #define CONFIG_SYS_IBAT7U 0x00000000
612 
613 /*
614  * Environment
615  */
616 #ifndef CONFIG_SYS_RAMBOOT
617     #define CONFIG_ENV_IS_IN_FLASH	1
618     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
619     #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
620 #else
621     #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
622     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
623 #endif
624 #define CONFIG_ENV_SIZE		0x2000
625 
626 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
627 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
628 
629 
630 /*
631  * BOOTP options
632  */
633 #define CONFIG_BOOTP_BOOTFILESIZE
634 #define CONFIG_BOOTP_BOOTPATH
635 #define CONFIG_BOOTP_GATEWAY
636 #define CONFIG_BOOTP_HOSTNAME
637 
638 
639 /*
640  * Command line configuration.
641  */
642 #include <config_cmd_default.h>
643 
644 #define CONFIG_CMD_PING
645 #define CONFIG_CMD_I2C
646 #define CONFIG_CMD_REGINFO
647 
648 #if defined(CONFIG_SYS_RAMBOOT)
649     #undef CONFIG_CMD_SAVEENV
650 #endif
651 
652 #if defined(CONFIG_PCI)
653     #define CONFIG_CMD_PCI
654     #define CONFIG_CMD_SCSI
655     #define CONFIG_CMD_EXT2
656     #define CONFIG_CMD_USB
657 #endif
658 
659 
660 #undef CONFIG_WATCHDOG			/* watchdog disabled */
661 
662 /*
663  * Miscellaneous configurable options
664  */
665 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
666 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
667 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
668 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
669 
670 #if defined(CONFIG_CMD_KGDB)
671     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
672 #else
673     #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
674 #endif
675 
676 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
677 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
678 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
679 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
680 
681 /*
682  * For booting Linux, the board info and command line data
683  * have to be in the first 8 MB of memory, since this is
684  * the maximum mapped by the Linux kernel during initialization.
685  */
686 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
687 
688 #if defined(CONFIG_CMD_KGDB)
689     #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
690     #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
691 #endif
692 
693 /*
694  * Environment Configuration
695  */
696 
697 /* The mac addresses for all ethernet interface */
698 #if defined(CONFIG_TSEC_ENET)
699 #define CONFIG_ETHADDR	 00:E0:0C:00:00:01
700 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
701 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
702 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
703 #endif
704 
705 #define CONFIG_HAS_ETH0		1
706 #define CONFIG_HAS_ETH1		1
707 #define CONFIG_HAS_ETH2		1
708 #define CONFIG_HAS_ETH3		1
709 
710 #define CONFIG_IPADDR		192.168.1.100
711 
712 #define CONFIG_HOSTNAME		unknown
713 #define CONFIG_ROOTPATH		"/opt/nfsroot"
714 #define CONFIG_BOOTFILE		"uImage"
715 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
716 
717 #define CONFIG_SERVERIP		192.168.1.1
718 #define CONFIG_GATEWAYIP	192.168.1.1
719 #define CONFIG_NETMASK		255.255.255.0
720 
721 /* default location for tftp and bootm */
722 #define CONFIG_LOADADDR		1000000
723 
724 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
725 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
726 
727 #define CONFIG_BAUDRATE	115200
728 
729 #define	CONFIG_EXTRA_ENV_SETTINGS					\
730 	"netdev=eth0\0"							\
731 	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
732 	"tftpflash=tftpboot $loadaddr $uboot; "				\
733 		"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
734 		"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
735 		"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
736 		"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
737 		"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
738 	"consoledev=ttyS0\0"						\
739 	"ramdiskaddr=2000000\0"						\
740 	"ramdiskfile=your.ramdisk.u-boot\0"				\
741 	"fdtaddr=c00000\0"						\
742 	"fdtfile=mpc8641_hpcn.dtb\0"					\
743 	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
744 	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
745 	"maxcpus=2"
746 
747 
748 #define CONFIG_NFSBOOTCOMMAND						\
749 	"setenv bootargs root=/dev/nfs rw "				\
750 	      "nfsroot=$serverip:$rootpath "				\
751 	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
752 	      "console=$consoledev,$baudrate $othbootargs;"		\
753 	"tftp $loadaddr $bootfile;"					\
754 	"tftp $fdtaddr $fdtfile;"					\
755 	"bootm $loadaddr - $fdtaddr"
756 
757 #define CONFIG_RAMBOOTCOMMAND						\
758 	"setenv bootargs root=/dev/ram rw "				\
759 	      "console=$consoledev,$baudrate $othbootargs;"		\
760 	"tftp $ramdiskaddr $ramdiskfile;"				\
761 	"tftp $loadaddr $bootfile;"					\
762 	"tftp $fdtaddr $fdtfile;"					\
763 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
764 
765 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
766 
767 #endif	/* __CONFIG_H */
768