1 /* 2 * Copyright 2006, 2010 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_MP 1 /* support multiple processors */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ 42 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 43 44 /* 45 * default CCSRBAR is at 0xff700000 46 * assume U-Boot is less than 0.5MB 47 */ 48 #define CONFIG_SYS_TEXT_BASE 0xeff00000 49 50 #ifdef RUN_DIAG 51 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 52 #endif 53 54 /* 55 * virtual address to be used for temporary mappings. There 56 * should be 128k free at this VA. 57 */ 58 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 59 60 /* 61 * set this to enable Rapid IO. PCI and RIO are mutually exclusive 62 */ 63 /*#define CONFIG_RIO 1*/ 64 65 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ 66 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 67 #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ 68 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ 69 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 70 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 71 #endif 72 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 73 74 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 75 #define CONFIG_ENV_OVERWRITE 76 77 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 78 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 79 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 80 81 #define CONFIG_ALTIVEC 1 82 83 /* 84 * L2CR setup -- make sure this is right for your board! 85 */ 86 #define CONFIG_SYS_L2 87 #define L2_INIT 0 88 #define L2_ENABLE (L2CR_L2E) 89 90 #ifndef CONFIG_SYS_CLK_FREQ 91 #ifndef __ASSEMBLY__ 92 extern unsigned long get_board_sys_clk(unsigned long dummy); 93 #endif 94 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 95 #endif 96 97 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 98 99 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 100 #define CONFIG_SYS_MEMTEST_END 0x00400000 101 102 /* 103 * With the exception of PCI Memory and Rapid IO, most devices will simply 104 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 105 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 106 */ 107 #ifdef CONFIG_PHYS_64BIT 108 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL 109 #else 110 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 111 #endif 112 113 /* 114 * Base addresses -- Note these are effective addresses where the 115 * actual resources get mapped (not physical addresses) 116 */ 117 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 118 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 119 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 120 121 /* Physical addresses */ 122 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 125 #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 126 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) 127 #else 128 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 129 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 130 #endif 131 132 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 133 134 /* 135 * DDR Setup 136 */ 137 #define CONFIG_FSL_DDR2 138 #undef CONFIG_FSL_DDR_INTERACTIVE 139 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 140 #define CONFIG_DDR_SPD 141 142 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 143 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 144 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 147 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 148 #define CONFIG_VERY_BIG_RAM 149 150 #define CONFIG_NUM_DDR_CONTROLLERS 2 151 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 152 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 153 154 /* 155 * I2C addresses of SPD EEPROMs 156 */ 157 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 158 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 159 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 160 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 161 162 163 /* 164 * These are used when DDR doesn't use SPD. 165 */ 166 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 167 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 168 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 169 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 170 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 171 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 172 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 173 #define CONFIG_SYS_DDR_MODE_1 0x00480432 174 #define CONFIG_SYS_DDR_MODE_2 0x00000000 175 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 176 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 177 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 178 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 179 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 180 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 181 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 182 183 #define CONFIG_ID_EEPROM 184 #define CONFIG_SYS_I2C_EEPROM_NXID 185 #define CONFIG_ID_EEPROM 186 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 187 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 188 189 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 190 #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ 191 | CONFIG_SYS_PHYS_ADDR_HIGH) 192 193 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 194 195 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 196 | 0x00001001) /* port size 16bit */ 197 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 198 199 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 200 | 0x00001001) /* port size 16bit */ 201 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 202 203 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 204 | 0x00000801) /* port size 8bit */ 205 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 206 207 /* 208 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 209 * The PIXIS and CF by themselves aren't large enough to take up the 128k 210 * required for the smallest BAT mapping, so there's a 64k hole. 211 */ 212 #define CONFIG_SYS_LBC_BASE 0xffde0000 213 #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ 214 | CONFIG_SYS_PHYS_ADDR_HIGH) 215 216 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 217 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 218 #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) 219 #define PIXIS_SIZE 0x00008000 /* 32k */ 220 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 221 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 222 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 223 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 224 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 225 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 226 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 227 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 228 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 229 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 230 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 231 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 232 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 233 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 234 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 235 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 236 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 237 238 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 239 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 240 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 241 242 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 243 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 244 245 #undef CONFIG_SYS_FLASH_CHECKSUM 246 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 247 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 249 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 250 251 #define CONFIG_FLASH_CFI_DRIVER 252 #define CONFIG_SYS_FLASH_CFI 253 #define CONFIG_SYS_FLASH_EMPTY_INFO 254 255 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 256 #define CONFIG_SYS_RAMBOOT 257 #else 258 #undef CONFIG_SYS_RAMBOOT 259 #endif 260 261 #if defined(CONFIG_SYS_RAMBOOT) 262 #undef CONFIG_SPD_EEPROM 263 #define CONFIG_SYS_SDRAM_SIZE 256 264 #endif 265 266 #undef CONFIG_CLOCKS_IN_MHZ 267 268 #define CONFIG_SYS_INIT_RAM_LOCK 1 269 #ifndef CONFIG_SYS_INIT_RAM_LOCK 270 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 271 #else 272 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 273 #endif 274 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 275 276 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 277 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 278 279 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 280 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 281 282 /* Serial Port */ 283 #define CONFIG_CONS_INDEX 1 284 #define CONFIG_SYS_NS16550 285 #define CONFIG_SYS_NS16550_SERIAL 286 #define CONFIG_SYS_NS16550_REG_SIZE 1 287 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 288 289 #define CONFIG_SYS_BAUDRATE_TABLE \ 290 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 291 292 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 293 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 294 295 /* Use the HUSH parser */ 296 #define CONFIG_SYS_HUSH_PARSER 297 #ifdef CONFIG_SYS_HUSH_PARSER 298 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 299 #endif 300 301 /* 302 * Pass open firmware flat tree to kernel 303 */ 304 #define CONFIG_OF_LIBFDT 1 305 #define CONFIG_OF_BOARD_SETUP 1 306 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 307 308 /* 309 * I2C 310 */ 311 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 312 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 313 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 314 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 315 #define CONFIG_SYS_I2C_SLAVE 0x7F 316 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 317 #define CONFIG_SYS_I2C_OFFSET 0x3100 318 319 /* 320 * RapidIO MMU 321 */ 322 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ 323 #ifdef CONFIG_PHYS_64BIT 324 #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL 325 #else 326 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 327 #endif 328 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 329 330 /* 331 * General PCI 332 * Addresses are mapped 1-1. 333 */ 334 335 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 336 #ifdef CONFIG_PHYS_64BIT 337 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 338 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL 339 #else 340 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 341 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT 342 #endif 343 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 344 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 345 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 346 #define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ 347 | CONFIG_SYS_PHYS_ADDR_HIGH) 348 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 349 350 #ifdef CONFIG_PHYS_64BIT 351 /* 352 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 353 * This will increase the amount of PCI address space available for 354 * for mapping RAM. 355 */ 356 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 357 #else 358 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 359 + CONFIG_SYS_PCIE1_MEM_SIZE) 360 #endif 361 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 362 + CONFIG_SYS_PCIE1_MEM_SIZE) 363 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 364 + CONFIG_SYS_PCIE1_MEM_SIZE) 365 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 366 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 367 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 368 + CONFIG_SYS_PCIE1_IO_SIZE) 369 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 370 + CONFIG_SYS_PCIE1_IO_SIZE) 371 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 372 373 #if defined(CONFIG_PCI) 374 375 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 376 377 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 378 379 #define CONFIG_NET_MULTI 380 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 381 382 #define CONFIG_RTL8139 383 384 #undef CONFIG_EEPRO100 385 #undef CONFIG_TULIP 386 387 /************************************************************ 388 * USB support 389 ************************************************************/ 390 #define CONFIG_PCI_OHCI 1 391 #define CONFIG_USB_OHCI_NEW 1 392 #define CONFIG_USB_KEYBOARD 1 393 #define CONFIG_SYS_STDIO_DEREGISTER 394 #define CONFIG_SYS_USB_EVENT_POLL 1 395 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 396 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 397 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 398 399 /*PCIE video card used*/ 400 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 401 402 /*PCI video card used*/ 403 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 404 405 /* video */ 406 #define CONFIG_VIDEO 407 408 #if defined(CONFIG_VIDEO) 409 #define CONFIG_BIOSEMU 410 #define CONFIG_CFB_CONSOLE 411 #define CONFIG_VIDEO_SW_CURSOR 412 #define CONFIG_VGA_AS_SINGLE_DEVICE 413 #define CONFIG_ATI_RADEON_FB 414 #define CONFIG_VIDEO_LOGO 415 /*#define CONFIG_CONSOLE_CURSOR*/ 416 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 417 #endif 418 419 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 420 421 #define CONFIG_DOS_PARTITION 422 #define CONFIG_SCSI_AHCI 423 424 #ifdef CONFIG_SCSI_AHCI 425 #define CONFIG_SATA_ULI5288 426 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 427 #define CONFIG_SYS_SCSI_MAX_LUN 1 428 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 429 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 430 #endif 431 432 #endif /* CONFIG_PCI */ 433 434 #if defined(CONFIG_TSEC_ENET) 435 436 #ifndef CONFIG_NET_MULTI 437 #define CONFIG_NET_MULTI 1 438 #endif 439 440 #define CONFIG_MII 1 /* MII PHY management */ 441 442 #define CONFIG_TSEC1 1 443 #define CONFIG_TSEC1_NAME "eTSEC1" 444 #define CONFIG_TSEC2 1 445 #define CONFIG_TSEC2_NAME "eTSEC2" 446 #define CONFIG_TSEC3 1 447 #define CONFIG_TSEC3_NAME "eTSEC3" 448 #define CONFIG_TSEC4 1 449 #define CONFIG_TSEC4_NAME "eTSEC4" 450 451 #define TSEC1_PHY_ADDR 0 452 #define TSEC2_PHY_ADDR 1 453 #define TSEC3_PHY_ADDR 2 454 #define TSEC4_PHY_ADDR 3 455 #define TSEC1_PHYIDX 0 456 #define TSEC2_PHYIDX 0 457 #define TSEC3_PHYIDX 0 458 #define TSEC4_PHYIDX 0 459 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 460 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 461 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 462 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 463 464 #define CONFIG_ETHPRIME "eTSEC1" 465 466 #endif /* CONFIG_TSEC_ENET */ 467 468 /* Contort an addr into the format needed for BATs */ 469 #ifdef CONFIG_PHYS_64BIT 470 #define BAT_PHYS_ADDR(x) ((unsigned long) \ 471 ((x & 0x00000000ffffffffULL) | \ 472 ((x & 0x0000000e00000000ULL) >> 24) | \ 473 ((x & 0x0000000100000000ULL) >> 30))) 474 #else 475 #define BAT_PHYS_ADDR(x) (x) 476 #endif 477 478 479 /* Put high physical address bits into the BAT format */ 480 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 481 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 482 483 /* 484 * BAT0 DDR 485 */ 486 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 487 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 488 489 /* 490 * BAT1 LBC (PIXIS/CF) 491 */ 492 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 493 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 494 BATL_GUARDEDSTORAGE) 495 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 496 | BATU_VS | BATU_VP) 497 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 498 | BATL_PP_RW | BATL_MEMCOHERENCE) 499 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 500 501 /* if CONFIG_PCI: 502 * BAT2 PCIE1 and PCIE1 MEM 503 * if CONFIG_RIO 504 * BAT2 Rapidio Memory 505 */ 506 #ifdef CONFIG_PCI 507 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ 508 | BATL_PP_RW | BATL_CACHEINHIBIT \ 509 | BATL_GUARDEDSTORAGE) 510 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 511 | BATU_VS | BATU_VP) 512 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ 513 | BATL_PP_RW | BATL_CACHEINHIBIT) 514 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 515 #else /* CONFIG_RIO */ 516 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 517 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 518 BATL_GUARDEDSTORAGE) 519 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ 520 | BATU_VS | BATU_VP) 521 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 522 | BATL_PP_RW | BATL_CACHEINHIBIT) 523 524 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ 525 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 526 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 527 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 528 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 529 #endif 530 531 /* 532 * BAT3 CCSR Space 533 * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs 534 * instead. The assembler chokes on ULL. 535 */ 536 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 537 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 538 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 539 | BATL_PP_RW | BATL_CACHEINHIBIT \ 540 | BATL_GUARDEDSTORAGE) 541 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 542 | BATU_VP) 543 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 544 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 545 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 546 | BATL_PP_RW | BATL_CACHEINHIBIT) 547 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 548 549 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 550 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 551 | BATL_PP_RW | BATL_CACHEINHIBIT \ 552 | BATL_GUARDEDSTORAGE) 553 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 554 | BATU_BL_1M | BATU_VS | BATU_VP) 555 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 556 | BATL_PP_RW | BATL_CACHEINHIBIT) 557 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 558 #endif 559 560 /* 561 * BAT4 PCIE1_IO and PCIE2_IO 562 */ 563 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ 564 | BATL_PP_RW | BATL_CACHEINHIBIT \ 565 | BATL_GUARDEDSTORAGE) 566 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 567 | BATU_VS | BATU_VP) 568 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ 569 | BATL_PP_RW | BATL_CACHEINHIBIT) 570 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 571 572 /* 573 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 574 */ 575 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 576 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 577 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 578 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 579 580 /* 581 * BAT6 FLASH 582 */ 583 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 584 | BATL_PP_RW | BATL_CACHEINHIBIT \ 585 | BATL_GUARDEDSTORAGE) 586 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 587 | BATU_VP) 588 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 589 | BATL_PP_RW | BATL_MEMCOHERENCE) 590 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 591 592 /* Map the last 1M of flash where we're running from reset */ 593 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 594 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 595 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 596 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 597 | BATL_MEMCOHERENCE) 598 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 599 600 /* 601 * BAT7 FREE - used later for tmp mappings 602 */ 603 #define CONFIG_SYS_DBAT7L 0x00000000 604 #define CONFIG_SYS_DBAT7U 0x00000000 605 #define CONFIG_SYS_IBAT7L 0x00000000 606 #define CONFIG_SYS_IBAT7U 0x00000000 607 608 /* 609 * Environment 610 */ 611 #ifndef CONFIG_SYS_RAMBOOT 612 #define CONFIG_ENV_IS_IN_FLASH 1 613 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 614 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 615 #else 616 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 617 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 618 #endif 619 #define CONFIG_ENV_SIZE 0x2000 620 621 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 622 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 623 624 625 /* 626 * BOOTP options 627 */ 628 #define CONFIG_BOOTP_BOOTFILESIZE 629 #define CONFIG_BOOTP_BOOTPATH 630 #define CONFIG_BOOTP_GATEWAY 631 #define CONFIG_BOOTP_HOSTNAME 632 633 634 /* 635 * Command line configuration. 636 */ 637 #include <config_cmd_default.h> 638 639 #define CONFIG_CMD_PING 640 #define CONFIG_CMD_I2C 641 #define CONFIG_CMD_REGINFO 642 643 #if defined(CONFIG_SYS_RAMBOOT) 644 #undef CONFIG_CMD_SAVEENV 645 #endif 646 647 #if defined(CONFIG_PCI) 648 #define CONFIG_CMD_PCI 649 #define CONFIG_CMD_SCSI 650 #define CONFIG_CMD_EXT2 651 #define CONFIG_CMD_USB 652 #endif 653 654 655 #undef CONFIG_WATCHDOG /* watchdog disabled */ 656 657 /* 658 * Miscellaneous configurable options 659 */ 660 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 661 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 662 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 663 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 664 665 #if defined(CONFIG_CMD_KGDB) 666 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 667 #else 668 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 669 #endif 670 671 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 672 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 673 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 674 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 675 676 /* 677 * For booting Linux, the board info and command line data 678 * have to be in the first 8 MB of memory, since this is 679 * the maximum mapped by the Linux kernel during initialization. 680 */ 681 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 682 683 #if defined(CONFIG_CMD_KGDB) 684 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 685 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 686 #endif 687 688 /* 689 * Environment Configuration 690 */ 691 692 /* The mac addresses for all ethernet interface */ 693 #if defined(CONFIG_TSEC_ENET) 694 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 695 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 696 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 697 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 698 #endif 699 700 #define CONFIG_HAS_ETH0 1 701 #define CONFIG_HAS_ETH1 1 702 #define CONFIG_HAS_ETH2 1 703 #define CONFIG_HAS_ETH3 1 704 705 #define CONFIG_IPADDR 192.168.1.100 706 707 #define CONFIG_HOSTNAME unknown 708 #define CONFIG_ROOTPATH /opt/nfsroot 709 #define CONFIG_BOOTFILE uImage 710 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 711 712 #define CONFIG_SERVERIP 192.168.1.1 713 #define CONFIG_GATEWAYIP 192.168.1.1 714 #define CONFIG_NETMASK 255.255.255.0 715 716 /* default location for tftp and bootm */ 717 #define CONFIG_LOADADDR 1000000 718 719 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 720 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 721 722 #define CONFIG_BAUDRATE 115200 723 724 #define CONFIG_EXTRA_ENV_SETTINGS \ 725 "netdev=eth0\0" \ 726 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 727 "tftpflash=tftpboot $loadaddr $uboot; " \ 728 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 729 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 730 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 731 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 732 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 733 "consoledev=ttyS0\0" \ 734 "ramdiskaddr=2000000\0" \ 735 "ramdiskfile=your.ramdisk.u-boot\0" \ 736 "fdtaddr=c00000\0" \ 737 "fdtfile=mpc8641_hpcn.dtb\0" \ 738 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 739 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 740 "maxcpus=2" 741 742 743 #define CONFIG_NFSBOOTCOMMAND \ 744 "setenv bootargs root=/dev/nfs rw " \ 745 "nfsroot=$serverip:$rootpath " \ 746 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 747 "console=$consoledev,$baudrate $othbootargs;" \ 748 "tftp $loadaddr $bootfile;" \ 749 "tftp $fdtaddr $fdtfile;" \ 750 "bootm $loadaddr - $fdtaddr" 751 752 #define CONFIG_RAMBOOTCOMMAND \ 753 "setenv bootargs root=/dev/ram rw " \ 754 "console=$consoledev,$baudrate $othbootargs;" \ 755 "tftp $ramdiskaddr $ramdiskfile;" \ 756 "tftp $loadaddr $bootfile;" \ 757 "tftp $fdtaddr $fdtfile;" \ 758 "bootm $loadaddr $ramdiskaddr $fdtaddr" 759 760 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 761 762 #endif /* __CONFIG_H */ 763