1 /*
2  * Copyright 2006, 2010-2011 Freescale Semiconductor.
3  *
4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 /*
10  * MPC8641HPCN board configuration file
11  *
12  * Make sure you change the MAC address and other network params first,
13  * search for CONFIG_SERVERIP, etc. in this file.
14  */
15 
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18 
19 #define CONFIG_SYS_GENERIC_BOARD
20 #define CONFIG_DISPLAY_BOARDINFO
21 
22 /* High Level Configuration Options */
23 #define CONFIG_MPC8641		1	/* MPC8641 specific */
24 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
25 #define CONFIG_MP		1	/* support multiple processors */
26 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
27 /*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
28 #define CONFIG_ADDR_MAP		1	/* Use addr map */
29 
30 /*
31  * default CCSRBAR is at 0xff700000
32  * assume U-Boot is less than 0.5MB
33  */
34 #define	CONFIG_SYS_TEXT_BASE	0xeff00000
35 
36 #ifdef RUN_DIAG
37 #define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
38 #endif
39 
40 /*
41  * virtual address to be used for temporary mappings.  There
42  * should be 128k free at this VA.
43  */
44 #define CONFIG_SYS_SCRATCH_VA	0xe0000000
45 
46 #define CONFIG_SYS_SRIO
47 #define CONFIG_SRIO1			/* SRIO port 1 */
48 
49 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
50 #define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
51 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
52 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
53 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
54 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
55 
56 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
57 #define CONFIG_ENV_OVERWRITE
58 
59 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
60 #define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
61 #define CONFIG_SYS_NUM_ADDR_MAP 8	/* Number of addr map slots = 8 dbats */
62 
63 #define CONFIG_ALTIVEC		1
64 
65 /*
66  * L2CR setup -- make sure this is right for your board!
67  */
68 #define CONFIG_SYS_L2
69 #define L2_INIT		0
70 #define L2_ENABLE	(L2CR_L2E)
71 
72 #ifndef CONFIG_SYS_CLK_FREQ
73 #ifndef __ASSEMBLY__
74 extern unsigned long get_board_sys_clk(unsigned long dummy);
75 #endif
76 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
77 #endif
78 
79 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
80 #define CONFIG_SYS_MEMTEST_END		0x00400000
81 
82 /*
83  * With the exception of PCI Memory and Rapid IO, most devices will simply
84  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
85  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
86  */
87 #ifdef CONFIG_PHYS_64BIT
88 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
89 #else
90 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
91 #endif
92 
93 /*
94  * Base addresses -- Note these are effective addresses where the
95  * actual resources get mapped (not physical addresses)
96  */
97 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
98 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
99 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
100 
101 /* Physical addresses */
102 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
103 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
104 #define CONFIG_SYS_CCSRBAR_PHYS \
105 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
106 			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
107 
108 #define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
109 
110 /*
111  * DDR Setup
112  */
113 #define CONFIG_SYS_FSL_DDR2
114 #undef CONFIG_FSL_DDR_INTERACTIVE
115 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
116 #define CONFIG_DDR_SPD
117 
118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
119 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
120 
121 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
122 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
123 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
124 #define CONFIG_VERY_BIG_RAM
125 
126 #define CONFIG_NUM_DDR_CONTROLLERS	2
127 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
128 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
129 
130 /*
131  * I2C addresses of SPD EEPROMs
132  */
133 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
134 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
135 #define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
136 #define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
137 
138 
139 /*
140  * These are used when DDR doesn't use SPD.
141  */
142 #define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
143 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
144 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
145 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
146 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
147 #define CONFIG_SYS_DDR_TIMING_1	0x39357322
148 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
149 #define CONFIG_SYS_DDR_MODE_1		0x00480432
150 #define CONFIG_SYS_DDR_MODE_2		0x00000000
151 #define CONFIG_SYS_DDR_INTERVAL	0x06090100
152 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
153 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
154 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
155 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
156 #define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
157 #define CONFIG_SYS_DDR_CONTROL2	0x04400000
158 
159 #define CONFIG_ID_EEPROM
160 #define CONFIG_SYS_I2C_EEPROM_NXID
161 #define CONFIG_ID_EEPROM
162 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
163 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
164 
165 #define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
166 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
167 #define CONFIG_SYS_FLASH_BASE_PHYS \
168 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
169 			    CONFIG_SYS_PHYS_ADDR_HIGH)
170 
171 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
172 
173 #define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
174 				 | 0x00001001)	/* port size 16bit */
175 #define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
176 
177 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
178 				 | 0x00001001)	/* port size 16bit */
179 #define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
180 
181 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
182 				 | 0x00000801) /* port size 8bit */
183 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
184 
185 /*
186  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
187  * The PIXIS and CF by themselves aren't large enough to take up the 128k
188  * required for the smallest BAT mapping, so there's a 64k hole.
189  */
190 #define CONFIG_SYS_LBC_BASE		0xffde0000
191 #define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
192 
193 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
194 #define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
195 #define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
196 #define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
197 						    CONFIG_SYS_PHYS_ADDR_HIGH)
198 #define PIXIS_SIZE		0x00008000	/* 32k */
199 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
200 #define PIXIS_VER		0x1	/* Board version at offset 1 */
201 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
202 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
203 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
204 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
205 #define PIXIS_VCTL		0x10	/* VELA Control Register */
206 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
207 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
208 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
209 #define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
210 #define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
211 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
212 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
213 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
214 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
215 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
216 
217 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
218 #define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
219 #define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
220 
221 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
222 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
223 
224 #undef	CONFIG_SYS_FLASH_CHECKSUM
225 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
226 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
227 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
228 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
229 
230 #define CONFIG_FLASH_CFI_DRIVER
231 #define CONFIG_SYS_FLASH_CFI
232 #define CONFIG_SYS_FLASH_EMPTY_INFO
233 
234 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
235 #define CONFIG_SYS_RAMBOOT
236 #else
237 #undef	CONFIG_SYS_RAMBOOT
238 #endif
239 
240 #if defined(CONFIG_SYS_RAMBOOT)
241 #undef CONFIG_SPD_EEPROM
242 #define CONFIG_SYS_SDRAM_SIZE	256
243 #endif
244 
245 #undef CONFIG_CLOCKS_IN_MHZ
246 
247 #define CONFIG_SYS_INIT_RAM_LOCK	1
248 #ifndef CONFIG_SYS_INIT_RAM_LOCK
249 #define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
250 #else
251 #define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
252 #endif
253 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
254 
255 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
256 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
257 
258 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
259 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
260 
261 /* Serial Port */
262 #define CONFIG_CONS_INDEX     1
263 #define CONFIG_SYS_NS16550
264 #define CONFIG_SYS_NS16550_SERIAL
265 #define CONFIG_SYS_NS16550_REG_SIZE	1
266 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
267 
268 #define CONFIG_SYS_BAUDRATE_TABLE  \
269 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
270 
271 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
272 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
273 
274 /* Use the HUSH parser */
275 #define CONFIG_SYS_HUSH_PARSER
276 
277 /*
278  * Pass open firmware flat tree to kernel
279  */
280 #define CONFIG_OF_LIBFDT		1
281 #define CONFIG_OF_BOARD_SETUP		1
282 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
283 
284 /*
285  * I2C
286  */
287 #define CONFIG_SYS_I2C
288 #define CONFIG_SYS_I2C_FSL
289 #define CONFIG_SYS_FSL_I2C_SPEED	400000
290 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
291 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
292 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
293 
294 /*
295  * RapidIO MMU
296  */
297 #define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
298 #ifdef CONFIG_PHYS_64BIT
299 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
300 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
301 #else
302 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
303 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
304 #endif
305 #define CONFIG_SYS_SRIO1_MEM_PHYS \
306 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
307 			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
308 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
309 
310 /*
311  * General PCI
312  * Addresses are mapped 1-1.
313  */
314 
315 #define CONFIG_SYS_PCIE1_NAME		"ULI"
316 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
317 #ifdef CONFIG_PHYS_64BIT
318 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
319 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
320 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
321 #else
322 #define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
323 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
324 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
325 #endif
326 #define CONFIG_SYS_PCIE1_MEM_PHYS \
327 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
328 			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
329 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
330 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
331 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
332 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
333 #define CONFIG_SYS_PCIE1_IO_PHYS \
334 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
335 			    CONFIG_SYS_PHYS_ADDR_HIGH)
336 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
337 
338 #ifdef CONFIG_PHYS_64BIT
339 /*
340  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
341  * This will increase the amount of PCI address space available for
342  * for mapping RAM.
343  */
344 #define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
345 #else
346 #define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
347 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
348 #endif
349 #define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
350 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
351 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
352 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
353 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
354 #define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
355 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
356 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
357 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
358 #define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
359 					 + CONFIG_SYS_PCIE1_IO_SIZE)
360 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
361 					 + CONFIG_SYS_PCIE1_IO_SIZE)
362 #define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
363 					 + CONFIG_SYS_PCIE1_IO_SIZE)
364 #define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
365 
366 #if defined(CONFIG_PCI)
367 
368 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
369 
370 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
371 
372 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
373 
374 #define CONFIG_RTL8139
375 
376 #undef CONFIG_EEPRO100
377 #undef CONFIG_TULIP
378 
379 /************************************************************
380  * USB support
381  ************************************************************/
382 #define CONFIG_PCI_OHCI			1
383 #define CONFIG_USB_OHCI_NEW		1
384 #define CONFIG_USB_KEYBOARD		1
385 #define CONFIG_SYS_STDIO_DEREGISTER
386 #define CONFIG_SYS_USB_EVENT_POLL		1
387 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
388 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
389 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
390 
391 /*PCIE video card used*/
392 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
393 
394 /*PCI video card used*/
395 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
396 
397 /* video */
398 #define CONFIG_VIDEO
399 
400 #if defined(CONFIG_VIDEO)
401 #define CONFIG_BIOSEMU
402 #define CONFIG_CFB_CONSOLE
403 #define CONFIG_VIDEO_SW_CURSOR
404 #define CONFIG_VGA_AS_SINGLE_DEVICE
405 #define CONFIG_ATI_RADEON_FB
406 #define CONFIG_VIDEO_LOGO
407 /*#define CONFIG_CONSOLE_CURSOR*/
408 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
409 #endif
410 
411 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
412 
413 #define CONFIG_DOS_PARTITION
414 #define CONFIG_SCSI_AHCI
415 
416 #ifdef CONFIG_SCSI_AHCI
417 #define CONFIG_LIBATA
418 #define CONFIG_SATA_ULI5288
419 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
420 #define CONFIG_SYS_SCSI_MAX_LUN	1
421 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
422 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
423 #endif
424 
425 #endif	/* CONFIG_PCI */
426 
427 #if defined(CONFIG_TSEC_ENET)
428 
429 #define CONFIG_MII		1	/* MII PHY management */
430 
431 #define CONFIG_TSEC1		1
432 #define CONFIG_TSEC1_NAME	"eTSEC1"
433 #define CONFIG_TSEC2		1
434 #define CONFIG_TSEC2_NAME	"eTSEC2"
435 #define CONFIG_TSEC3		1
436 #define CONFIG_TSEC3_NAME	"eTSEC3"
437 #define CONFIG_TSEC4		1
438 #define CONFIG_TSEC4_NAME	"eTSEC4"
439 
440 #define TSEC1_PHY_ADDR		0
441 #define TSEC2_PHY_ADDR		1
442 #define TSEC3_PHY_ADDR		2
443 #define TSEC4_PHY_ADDR		3
444 #define TSEC1_PHYIDX		0
445 #define TSEC2_PHYIDX		0
446 #define TSEC3_PHYIDX		0
447 #define TSEC4_PHYIDX		0
448 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
449 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
450 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
451 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
452 
453 #define CONFIG_ETHPRIME		"eTSEC1"
454 
455 #endif	/* CONFIG_TSEC_ENET */
456 
457 
458 #ifdef CONFIG_PHYS_64BIT
459 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
460 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
461 
462 /* Put physical address into the BAT format */
463 #define BAT_PHYS_ADDR(low, high) \
464 	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
465 /* Convert high/low pairs to actual 64-bit value */
466 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
467 #else
468 /* 32-bit systems just ignore the "high" bits */
469 #define BAT_PHYS_ADDR(low, high)        (low)
470 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
471 #endif
472 
473 /*
474  * BAT0		DDR
475  */
476 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
477 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
478 
479 /*
480  * BAT1		LBC (PIXIS/CF)
481  */
482 #define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
483 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
484 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
485 				 BATL_GUARDEDSTORAGE)
486 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
487 				 | BATU_VS | BATU_VP)
488 #define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
489 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
490 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
491 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
492 
493 /* if CONFIG_PCI:
494  * BAT2		PCIE1 and PCIE1 MEM
495  * if CONFIG_RIO
496  * BAT2		Rapidio Memory
497  */
498 #ifdef CONFIG_PCI
499 #define CONFIG_PCI_INDIRECT_BRIDGE
500 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
501 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
502 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
503 				 | BATL_GUARDEDSTORAGE)
504 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
505 				 | BATU_VS | BATU_VP)
506 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
507 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
508 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
509 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
510 #else /* CONFIG_RIO */
511 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
512 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
513 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
514 				 BATL_GUARDEDSTORAGE)
515 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
516 				 | BATU_VS | BATU_VP)
517 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
518 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
519 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
520 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
521 #endif
522 
523 /*
524  * BAT3		CCSR Space
525  */
526 #define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
527 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
528 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
529 				 | BATL_GUARDEDSTORAGE)
530 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
531 				 | BATU_VP)
532 #define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
533 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
534 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
535 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
536 
537 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
538 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
539 				       | BATL_PP_RW | BATL_CACHEINHIBIT \
540 				       | BATL_GUARDEDSTORAGE)
541 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
542 				       | BATU_BL_1M | BATU_VS | BATU_VP)
543 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
544 				       | BATL_PP_RW | BATL_CACHEINHIBIT)
545 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
546 #endif
547 
548 /*
549  * BAT4		PCIE1_IO and PCIE2_IO
550  */
551 #define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
552 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
553 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
554 				 | BATL_GUARDEDSTORAGE)
555 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
556 				 | BATU_VS | BATU_VP)
557 #define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
558 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
559 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
560 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
561 
562 /*
563  * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
564  */
565 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
566 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
567 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
568 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
569 
570 /*
571  * BAT6		FLASH
572  */
573 #define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
574 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
575 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
576 				 | BATL_GUARDEDSTORAGE)
577 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
578 				 | BATU_VP)
579 #define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
580 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
581 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
582 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
583 
584 /* Map the last 1M of flash where we're running from reset */
585 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
586 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
587 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
588 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
589 				 | BATL_MEMCOHERENCE)
590 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
591 
592 /*
593  * BAT7		FREE - used later for tmp mappings
594  */
595 #define CONFIG_SYS_DBAT7L 0x00000000
596 #define CONFIG_SYS_DBAT7U 0x00000000
597 #define CONFIG_SYS_IBAT7L 0x00000000
598 #define CONFIG_SYS_IBAT7U 0x00000000
599 
600 /*
601  * Environment
602  */
603 #ifndef CONFIG_SYS_RAMBOOT
604     #define CONFIG_ENV_IS_IN_FLASH	1
605     #define CONFIG_ENV_ADDR		\
606 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
607     #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
608 #else
609     #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
610     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
611 #endif
612 #define CONFIG_ENV_SIZE		0x2000
613 
614 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
615 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
616 
617 
618 /*
619  * BOOTP options
620  */
621 #define CONFIG_BOOTP_BOOTFILESIZE
622 #define CONFIG_BOOTP_BOOTPATH
623 #define CONFIG_BOOTP_GATEWAY
624 #define CONFIG_BOOTP_HOSTNAME
625 
626 
627 /*
628  * Command line configuration.
629  */
630 #define CONFIG_CMD_PING
631 #define CONFIG_CMD_I2C
632 #define CONFIG_CMD_REGINFO
633 
634 #if defined(CONFIG_PCI)
635     #define CONFIG_CMD_PCI
636     #define CONFIG_CMD_SCSI
637     #define CONFIG_CMD_EXT2
638     #define CONFIG_CMD_USB
639 #endif
640 
641 
642 #undef CONFIG_WATCHDOG			/* watchdog disabled */
643 
644 /*
645  * Miscellaneous configurable options
646  */
647 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
648 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
649 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
650 
651 #if defined(CONFIG_CMD_KGDB)
652     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
653 #else
654     #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
655 #endif
656 
657 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
658 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
659 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
660 
661 /*
662  * For booting Linux, the board info and command line data
663  * have to be in the first 8 MB of memory, since this is
664  * the maximum mapped by the Linux kernel during initialization.
665  */
666 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
667 
668 #if defined(CONFIG_CMD_KGDB)
669     #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
670 #endif
671 
672 /*
673  * Environment Configuration
674  */
675 
676 #define CONFIG_HAS_ETH0		1
677 #define CONFIG_HAS_ETH1		1
678 #define CONFIG_HAS_ETH2		1
679 #define CONFIG_HAS_ETH3		1
680 
681 #define CONFIG_IPADDR		192.168.1.100
682 
683 #define CONFIG_HOSTNAME		unknown
684 #define CONFIG_ROOTPATH		"/opt/nfsroot"
685 #define CONFIG_BOOTFILE		"uImage"
686 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
687 
688 #define CONFIG_SERVERIP		192.168.1.1
689 #define CONFIG_GATEWAYIP	192.168.1.1
690 #define CONFIG_NETMASK		255.255.255.0
691 
692 /* default location for tftp and bootm */
693 #define CONFIG_LOADADDR		1000000
694 
695 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
696 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
697 
698 #define CONFIG_BAUDRATE	115200
699 
700 #define	CONFIG_EXTRA_ENV_SETTINGS					\
701 	"netdev=eth0\0"							\
702 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
703 	"tftpflash=tftpboot $loadaddr $uboot; "				\
704 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
705 			" +$filesize; "	\
706 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
707 			" +$filesize; "	\
708 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
709 			" $filesize; "	\
710 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
711 			" +$filesize; "	\
712 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
713 			" $filesize\0"	\
714 	"consoledev=ttyS0\0"						\
715 	"ramdiskaddr=2000000\0"						\
716 	"ramdiskfile=your.ramdisk.u-boot\0"				\
717 	"fdtaddr=c00000\0"						\
718 	"fdtfile=mpc8641_hpcn.dtb\0"					\
719 	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
720 	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
721 	"maxcpus=2"
722 
723 
724 #define CONFIG_NFSBOOTCOMMAND						\
725 	"setenv bootargs root=/dev/nfs rw "				\
726 	      "nfsroot=$serverip:$rootpath "				\
727 	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
728 	      "console=$consoledev,$baudrate $othbootargs;"		\
729 	"tftp $loadaddr $bootfile;"					\
730 	"tftp $fdtaddr $fdtfile;"					\
731 	"bootm $loadaddr - $fdtaddr"
732 
733 #define CONFIG_RAMBOOTCOMMAND						\
734 	"setenv bootargs root=/dev/ram rw "				\
735 	      "console=$consoledev,$baudrate $othbootargs;"		\
736 	"tftp $ramdiskaddr $ramdiskfile;"				\
737 	"tftp $loadaddr $bootfile;"					\
738 	"tftp $fdtaddr $fdtfile;"					\
739 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
740 
741 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
742 
743 #endif	/* __CONFIG_H */
744