1 /*
2  * Copyright 2006, 2010-2011 Freescale Semiconductor.
3  *
4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 /*
10  * MPC8641HPCN board configuration file
11  *
12  * Make sure you change the MAC address and other network params first,
13  * search for CONFIG_SERVERIP, etc. in this file.
14  */
15 
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18 
19 #define CONFIG_DISPLAY_BOARDINFO
20 
21 /* High Level Configuration Options */
22 #define CONFIG_MPC8641		1	/* MPC8641 specific */
23 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
24 #define CONFIG_MP		1	/* support multiple processors */
25 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
26 /*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
27 #define CONFIG_ADDR_MAP		1	/* Use addr map */
28 
29 /*
30  * default CCSRBAR is at 0xff700000
31  * assume U-Boot is less than 0.5MB
32  */
33 #define	CONFIG_SYS_TEXT_BASE	0xeff00000
34 
35 #ifdef RUN_DIAG
36 #define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
37 #endif
38 
39 /*
40  * virtual address to be used for temporary mappings.  There
41  * should be 128k free at this VA.
42  */
43 #define CONFIG_SYS_SCRATCH_VA	0xe0000000
44 
45 #define CONFIG_SYS_SRIO
46 #define CONFIG_SRIO1			/* SRIO port 1 */
47 
48 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
49 #define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
50 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
51 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
52 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
53 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
54 
55 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
56 #define CONFIG_ENV_OVERWRITE
57 
58 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
59 #define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
60 #define CONFIG_SYS_NUM_ADDR_MAP 8	/* Number of addr map slots = 8 dbats */
61 
62 #define CONFIG_ALTIVEC		1
63 
64 /*
65  * L2CR setup -- make sure this is right for your board!
66  */
67 #define CONFIG_SYS_L2
68 #define L2_INIT		0
69 #define L2_ENABLE	(L2CR_L2E)
70 
71 #ifndef CONFIG_SYS_CLK_FREQ
72 #ifndef __ASSEMBLY__
73 extern unsigned long get_board_sys_clk(unsigned long dummy);
74 #endif
75 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
76 #endif
77 
78 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
79 #define CONFIG_SYS_MEMTEST_END		0x00400000
80 
81 /*
82  * With the exception of PCI Memory and Rapid IO, most devices will simply
83  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
84  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
85  */
86 #ifdef CONFIG_PHYS_64BIT
87 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
88 #else
89 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
90 #endif
91 
92 /*
93  * Base addresses -- Note these are effective addresses where the
94  * actual resources get mapped (not physical addresses)
95  */
96 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
97 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
98 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
99 
100 /* Physical addresses */
101 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
102 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
103 #define CONFIG_SYS_CCSRBAR_PHYS \
104 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
105 			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
106 
107 #define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
108 
109 /*
110  * DDR Setup
111  */
112 #define CONFIG_SYS_FSL_DDR2
113 #undef CONFIG_FSL_DDR_INTERACTIVE
114 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
115 #define CONFIG_DDR_SPD
116 
117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
118 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
119 
120 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
121 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
122 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
123 #define CONFIG_VERY_BIG_RAM
124 
125 #define CONFIG_NUM_DDR_CONTROLLERS	2
126 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
127 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
128 
129 /*
130  * I2C addresses of SPD EEPROMs
131  */
132 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
133 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
134 #define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
135 #define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
136 
137 
138 /*
139  * These are used when DDR doesn't use SPD.
140  */
141 #define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
142 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
143 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
144 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
145 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
146 #define CONFIG_SYS_DDR_TIMING_1	0x39357322
147 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
148 #define CONFIG_SYS_DDR_MODE_1		0x00480432
149 #define CONFIG_SYS_DDR_MODE_2		0x00000000
150 #define CONFIG_SYS_DDR_INTERVAL	0x06090100
151 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
152 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
153 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
154 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
155 #define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
156 #define CONFIG_SYS_DDR_CONTROL2	0x04400000
157 
158 #define CONFIG_ID_EEPROM
159 #define CONFIG_SYS_I2C_EEPROM_NXID
160 #define CONFIG_ID_EEPROM
161 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
162 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
163 
164 #define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
165 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
166 #define CONFIG_SYS_FLASH_BASE_PHYS \
167 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
168 			    CONFIG_SYS_PHYS_ADDR_HIGH)
169 
170 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
171 
172 #define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
173 				 | 0x00001001)	/* port size 16bit */
174 #define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
175 
176 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
177 				 | 0x00001001)	/* port size 16bit */
178 #define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
179 
180 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
181 				 | 0x00000801) /* port size 8bit */
182 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
183 
184 /*
185  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
186  * The PIXIS and CF by themselves aren't large enough to take up the 128k
187  * required for the smallest BAT mapping, so there's a 64k hole.
188  */
189 #define CONFIG_SYS_LBC_BASE		0xffde0000
190 #define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
191 
192 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
193 #define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
194 #define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
195 #define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
196 						    CONFIG_SYS_PHYS_ADDR_HIGH)
197 #define PIXIS_SIZE		0x00008000	/* 32k */
198 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
199 #define PIXIS_VER		0x1	/* Board version at offset 1 */
200 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
201 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
202 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
203 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
204 #define PIXIS_VCTL		0x10	/* VELA Control Register */
205 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
206 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
207 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
208 #define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
209 #define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
210 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
211 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
212 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
213 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
214 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
215 
216 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
217 #define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
218 #define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
219 
220 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
221 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
222 
223 #undef	CONFIG_SYS_FLASH_CHECKSUM
224 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
225 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
226 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
227 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
228 
229 #define CONFIG_FLASH_CFI_DRIVER
230 #define CONFIG_SYS_FLASH_CFI
231 #define CONFIG_SYS_FLASH_EMPTY_INFO
232 
233 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
234 #define CONFIG_SYS_RAMBOOT
235 #else
236 #undef	CONFIG_SYS_RAMBOOT
237 #endif
238 
239 #if defined(CONFIG_SYS_RAMBOOT)
240 #undef CONFIG_SPD_EEPROM
241 #define CONFIG_SYS_SDRAM_SIZE	256
242 #endif
243 
244 #undef CONFIG_CLOCKS_IN_MHZ
245 
246 #define CONFIG_SYS_INIT_RAM_LOCK	1
247 #ifndef CONFIG_SYS_INIT_RAM_LOCK
248 #define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
249 #else
250 #define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
251 #endif
252 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
253 
254 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
255 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
256 
257 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
258 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
259 
260 /* Serial Port */
261 #define CONFIG_CONS_INDEX     1
262 #define CONFIG_SYS_NS16550_SERIAL
263 #define CONFIG_SYS_NS16550_REG_SIZE	1
264 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
265 
266 #define CONFIG_SYS_BAUDRATE_TABLE  \
267 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
268 
269 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
270 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
271 
272 /* Use the HUSH parser */
273 #define CONFIG_SYS_HUSH_PARSER
274 
275 /*
276  * I2C
277  */
278 #define CONFIG_SYS_I2C
279 #define CONFIG_SYS_I2C_FSL
280 #define CONFIG_SYS_FSL_I2C_SPEED	400000
281 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
282 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
283 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
284 
285 /*
286  * RapidIO MMU
287  */
288 #define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
289 #ifdef CONFIG_PHYS_64BIT
290 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
291 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
292 #else
293 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
294 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
295 #endif
296 #define CONFIG_SYS_SRIO1_MEM_PHYS \
297 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
298 			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
299 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
300 
301 /*
302  * General PCI
303  * Addresses are mapped 1-1.
304  */
305 
306 #define CONFIG_SYS_PCIE1_NAME		"ULI"
307 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
308 #ifdef CONFIG_PHYS_64BIT
309 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
310 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
311 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
312 #else
313 #define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
314 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
315 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
316 #endif
317 #define CONFIG_SYS_PCIE1_MEM_PHYS \
318 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
319 			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
320 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
321 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
322 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
323 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
324 #define CONFIG_SYS_PCIE1_IO_PHYS \
325 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
326 			    CONFIG_SYS_PHYS_ADDR_HIGH)
327 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
328 
329 #ifdef CONFIG_PHYS_64BIT
330 /*
331  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
332  * This will increase the amount of PCI address space available for
333  * for mapping RAM.
334  */
335 #define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
336 #else
337 #define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
338 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
339 #endif
340 #define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
341 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
342 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
343 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
344 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
345 #define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
346 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
347 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
348 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
349 #define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
350 					 + CONFIG_SYS_PCIE1_IO_SIZE)
351 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
352 					 + CONFIG_SYS_PCIE1_IO_SIZE)
353 #define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
354 					 + CONFIG_SYS_PCIE1_IO_SIZE)
355 #define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
356 
357 #if defined(CONFIG_PCI)
358 
359 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
360 
361 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
362 
363 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
364 
365 
366 #undef CONFIG_EEPRO100
367 #undef CONFIG_TULIP
368 
369 /************************************************************
370  * USB support
371  ************************************************************/
372 #define CONFIG_PCI_OHCI			1
373 #define CONFIG_USB_OHCI_NEW		1
374 #define CONFIG_USB_KEYBOARD		1
375 #define CONFIG_SYS_STDIO_DEREGISTER
376 #define CONFIG_SYS_USB_EVENT_POLL		1
377 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
378 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
379 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
380 
381 /*PCIE video card used*/
382 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
383 
384 /*PCI video card used*/
385 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
386 
387 /* video */
388 #define CONFIG_VIDEO
389 
390 #if defined(CONFIG_VIDEO)
391 #define CONFIG_BIOSEMU
392 #define CONFIG_CFB_CONSOLE
393 #define CONFIG_VIDEO_SW_CURSOR
394 #define CONFIG_VGA_AS_SINGLE_DEVICE
395 #define CONFIG_ATI_RADEON_FB
396 #define CONFIG_VIDEO_LOGO
397 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
398 #endif
399 
400 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
401 
402 #define CONFIG_DOS_PARTITION
403 #define CONFIG_SCSI_AHCI
404 
405 #ifdef CONFIG_SCSI_AHCI
406 #define CONFIG_LIBATA
407 #define CONFIG_SATA_ULI5288
408 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
409 #define CONFIG_SYS_SCSI_MAX_LUN	1
410 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
411 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
412 #endif
413 
414 #endif	/* CONFIG_PCI */
415 
416 #if defined(CONFIG_TSEC_ENET)
417 
418 #define CONFIG_MII		1	/* MII PHY management */
419 
420 #define CONFIG_TSEC1		1
421 #define CONFIG_TSEC1_NAME	"eTSEC1"
422 #define CONFIG_TSEC2		1
423 #define CONFIG_TSEC2_NAME	"eTSEC2"
424 #define CONFIG_TSEC3		1
425 #define CONFIG_TSEC3_NAME	"eTSEC3"
426 #define CONFIG_TSEC4		1
427 #define CONFIG_TSEC4_NAME	"eTSEC4"
428 
429 #define TSEC1_PHY_ADDR		0
430 #define TSEC2_PHY_ADDR		1
431 #define TSEC3_PHY_ADDR		2
432 #define TSEC4_PHY_ADDR		3
433 #define TSEC1_PHYIDX		0
434 #define TSEC2_PHYIDX		0
435 #define TSEC3_PHYIDX		0
436 #define TSEC4_PHYIDX		0
437 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
438 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
439 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
440 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
441 
442 #define CONFIG_ETHPRIME		"eTSEC1"
443 
444 #endif	/* CONFIG_TSEC_ENET */
445 
446 
447 #ifdef CONFIG_PHYS_64BIT
448 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
449 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
450 
451 /* Put physical address into the BAT format */
452 #define BAT_PHYS_ADDR(low, high) \
453 	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
454 /* Convert high/low pairs to actual 64-bit value */
455 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
456 #else
457 /* 32-bit systems just ignore the "high" bits */
458 #define BAT_PHYS_ADDR(low, high)        (low)
459 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
460 #endif
461 
462 /*
463  * BAT0		DDR
464  */
465 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
466 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
467 
468 /*
469  * BAT1		LBC (PIXIS/CF)
470  */
471 #define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
472 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
473 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
474 				 BATL_GUARDEDSTORAGE)
475 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
476 				 | BATU_VS | BATU_VP)
477 #define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
478 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
479 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
480 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
481 
482 /* if CONFIG_PCI:
483  * BAT2		PCIE1 and PCIE1 MEM
484  * if CONFIG_RIO
485  * BAT2		Rapidio Memory
486  */
487 #ifdef CONFIG_PCI
488 #define CONFIG_PCI_INDIRECT_BRIDGE
489 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
490 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
491 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
492 				 | BATL_GUARDEDSTORAGE)
493 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
494 				 | BATU_VS | BATU_VP)
495 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
496 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
497 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
498 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
499 #else /* CONFIG_RIO */
500 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
501 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
502 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
503 				 BATL_GUARDEDSTORAGE)
504 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
505 				 | BATU_VS | BATU_VP)
506 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
507 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
508 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
509 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
510 #endif
511 
512 /*
513  * BAT3		CCSR Space
514  */
515 #define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
516 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
517 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
518 				 | BATL_GUARDEDSTORAGE)
519 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
520 				 | BATU_VP)
521 #define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
522 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
523 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
524 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
525 
526 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
527 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
528 				       | BATL_PP_RW | BATL_CACHEINHIBIT \
529 				       | BATL_GUARDEDSTORAGE)
530 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
531 				       | BATU_BL_1M | BATU_VS | BATU_VP)
532 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
533 				       | BATL_PP_RW | BATL_CACHEINHIBIT)
534 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
535 #endif
536 
537 /*
538  * BAT4		PCIE1_IO and PCIE2_IO
539  */
540 #define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
541 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
542 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
543 				 | BATL_GUARDEDSTORAGE)
544 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
545 				 | BATU_VS | BATU_VP)
546 #define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
547 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
548 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
549 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
550 
551 /*
552  * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
553  */
554 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
555 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
556 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
557 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
558 
559 /*
560  * BAT6		FLASH
561  */
562 #define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
563 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
564 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
565 				 | BATL_GUARDEDSTORAGE)
566 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
567 				 | BATU_VP)
568 #define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
569 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
570 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
571 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
572 
573 /* Map the last 1M of flash where we're running from reset */
574 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
575 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
576 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
577 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
578 				 | BATL_MEMCOHERENCE)
579 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
580 
581 /*
582  * BAT7		FREE - used later for tmp mappings
583  */
584 #define CONFIG_SYS_DBAT7L 0x00000000
585 #define CONFIG_SYS_DBAT7U 0x00000000
586 #define CONFIG_SYS_IBAT7L 0x00000000
587 #define CONFIG_SYS_IBAT7U 0x00000000
588 
589 /*
590  * Environment
591  */
592 #ifndef CONFIG_SYS_RAMBOOT
593     #define CONFIG_ENV_IS_IN_FLASH	1
594     #define CONFIG_ENV_ADDR		\
595 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
596     #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
597 #else
598     #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
599     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
600 #endif
601 #define CONFIG_ENV_SIZE		0x2000
602 
603 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
604 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
605 
606 
607 /*
608  * BOOTP options
609  */
610 #define CONFIG_BOOTP_BOOTFILESIZE
611 #define CONFIG_BOOTP_BOOTPATH
612 #define CONFIG_BOOTP_GATEWAY
613 #define CONFIG_BOOTP_HOSTNAME
614 
615 
616 /*
617  * Command line configuration.
618  */
619 #define CONFIG_CMD_PING
620 #define CONFIG_CMD_I2C
621 #define CONFIG_CMD_REGINFO
622 
623 #if defined(CONFIG_PCI)
624     #define CONFIG_CMD_PCI
625     #define CONFIG_CMD_SCSI
626     #define CONFIG_CMD_EXT2
627     #define CONFIG_CMD_USB
628 #endif
629 
630 
631 #undef CONFIG_WATCHDOG			/* watchdog disabled */
632 
633 /*
634  * Miscellaneous configurable options
635  */
636 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
637 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
638 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
639 
640 #if defined(CONFIG_CMD_KGDB)
641     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
642 #else
643     #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
644 #endif
645 
646 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
647 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
648 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
649 
650 /*
651  * For booting Linux, the board info and command line data
652  * have to be in the first 8 MB of memory, since this is
653  * the maximum mapped by the Linux kernel during initialization.
654  */
655 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
656 
657 #if defined(CONFIG_CMD_KGDB)
658     #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
659 #endif
660 
661 /*
662  * Environment Configuration
663  */
664 
665 #define CONFIG_HAS_ETH0		1
666 #define CONFIG_HAS_ETH1		1
667 #define CONFIG_HAS_ETH2		1
668 #define CONFIG_HAS_ETH3		1
669 
670 #define CONFIG_IPADDR		192.168.1.100
671 
672 #define CONFIG_HOSTNAME		unknown
673 #define CONFIG_ROOTPATH		"/opt/nfsroot"
674 #define CONFIG_BOOTFILE		"uImage"
675 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
676 
677 #define CONFIG_SERVERIP		192.168.1.1
678 #define CONFIG_GATEWAYIP	192.168.1.1
679 #define CONFIG_NETMASK		255.255.255.0
680 
681 /* default location for tftp and bootm */
682 #define CONFIG_LOADADDR		1000000
683 
684 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
685 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
686 
687 #define CONFIG_BAUDRATE	115200
688 
689 #define	CONFIG_EXTRA_ENV_SETTINGS					\
690 	"netdev=eth0\0"							\
691 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
692 	"tftpflash=tftpboot $loadaddr $uboot; "				\
693 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
694 			" +$filesize; "	\
695 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
696 			" +$filesize; "	\
697 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
698 			" $filesize; "	\
699 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
700 			" +$filesize; "	\
701 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
702 			" $filesize\0"	\
703 	"consoledev=ttyS0\0"						\
704 	"ramdiskaddr=2000000\0"						\
705 	"ramdiskfile=your.ramdisk.u-boot\0"				\
706 	"fdtaddr=c00000\0"						\
707 	"fdtfile=mpc8641_hpcn.dtb\0"					\
708 	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
709 	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
710 	"maxcpus=2"
711 
712 
713 #define CONFIG_NFSBOOTCOMMAND						\
714 	"setenv bootargs root=/dev/nfs rw "				\
715 	      "nfsroot=$serverip:$rootpath "				\
716 	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
717 	      "console=$consoledev,$baudrate $othbootargs;"		\
718 	"tftp $loadaddr $bootfile;"					\
719 	"tftp $fdtaddr $fdtfile;"					\
720 	"bootm $loadaddr - $fdtaddr"
721 
722 #define CONFIG_RAMBOOTCOMMAND						\
723 	"setenv bootargs root=/dev/ram rw "				\
724 	      "console=$consoledev,$baudrate $othbootargs;"		\
725 	"tftp $ramdiskaddr $ramdiskfile;"				\
726 	"tftp $loadaddr $bootfile;"					\
727 	"tftp $fdtaddr $fdtfile;"					\
728 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
729 
730 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
731 
732 #endif	/* __CONFIG_H */
733