1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 42 #ifdef RUN_DIAG 43 #define CFG_DIAG_ADDR 0xff800000 44 #endif 45 46 #define CFG_RESET_ADDRESS 0xfff00100 47 48 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 49 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ 50 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ 51 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 52 53 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 54 #define CONFIG_ENV_OVERWRITE 55 56 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 57 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 58 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 59 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 60 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 61 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 62 #define CONFIG_NUM_DDR_CONTROLLERS 2 63 /* #define CONFIG_DDR_INTERLEAVE 1 */ 64 #define CACHE_LINE_INTERLEAVING 0x20000000 65 #define PAGE_INTERLEAVING 0x21000000 66 #define BANK_INTERLEAVING 0x22000000 67 #define SUPER_BANK_INTERLEAVING 0x23000000 68 69 70 #define CONFIG_ALTIVEC 1 71 72 /* 73 * L2CR setup -- make sure this is right for your board! 74 */ 75 #define CFG_L2 76 #define L2_INIT 0 77 #define L2_ENABLE (L2CR_L2E) 78 79 #ifndef CONFIG_SYS_CLK_FREQ 80 #ifndef __ASSEMBLY__ 81 extern unsigned long get_board_sys_clk(unsigned long dummy); 82 #endif 83 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 84 #endif 85 86 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 87 88 #undef CFG_DRAM_TEST /* memory test, takes time */ 89 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 90 #define CFG_MEMTEST_END 0x00400000 91 92 /* 93 * Base addresses -- Note these are effective addresses where the 94 * actual resources get mapped (not physical addresses) 95 */ 96 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 97 #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ 98 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 99 100 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 101 #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) 102 103 /* 104 * DDR Setup 105 */ 106 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 107 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 108 #define CONFIG_VERY_BIG_RAM 109 110 #define MPC86xx_DDR_SDRAM_CLK_CNTL 111 112 #if defined(CONFIG_SPD_EEPROM) 113 /* 114 * Determine DDR configuration from I2C interface. 115 */ 116 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 117 #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ 118 #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ 119 #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ 120 121 #else 122 /* 123 * Manually set up DDR1 parameters 124 */ 125 126 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 127 128 #define CFG_DDR_CS0_BNDS 0x0000000F 129 #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 130 #define CFG_DDR_EXT_REFRESH 0x00000000 131 #define CFG_DDR_TIMING_0 0x00260802 132 #define CFG_DDR_TIMING_1 0x39357322 133 #define CFG_DDR_TIMING_2 0x14904cc8 134 #define CFG_DDR_MODE_1 0x00480432 135 #define CFG_DDR_MODE_2 0x00000000 136 #define CFG_DDR_INTERVAL 0x06090100 137 #define CFG_DDR_DATA_INIT 0xdeadbeef 138 #define CFG_DDR_CLK_CTRL 0x03800000 139 #define CFG_DDR_OCD_CTRL 0x00000000 140 #define CFG_DDR_OCD_STATUS 0x00000000 141 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 142 #define CFG_DDR_CONTROL2 0x04400000 143 144 /* Not used in fixed_sdram function */ 145 146 #define CFG_DDR_MODE 0x00000022 147 #define CFG_DDR_CS1_BNDS 0x00000000 148 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 149 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 150 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 151 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 152 #endif 153 154 #define CFG_ID_EEPROM 1 155 #define ID_EEPROM_ADDR 0x57 156 157 /* 158 * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. 159 * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff 160 * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. 161 * However, when u-boot comes up, the flash_init needs hard start addresses 162 * to build its info table. For user convenience, the flash addresses is 163 * fe800000 and ff800000. That way, u-boot knows where the flash is 164 * and the user can download u-boot code from promjet to fef00000, a 165 * more intuitive location than fe700000. 166 * 167 * Note that, on switching the boot location, fef00000 becomes fff00000. 168 */ 169 #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ 170 #define CFG_FLASH_BASE2 0xff800000 171 172 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 173 174 #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ 175 #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ 176 177 #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ 178 #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ 179 180 #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ 181 #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ 182 183 #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ 184 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 185 186 187 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 188 #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ 189 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 190 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 191 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 192 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 193 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 194 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 195 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 196 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 197 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 198 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 199 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 200 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 201 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 202 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 203 #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 204 205 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 206 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ 207 208 #undef CFG_FLASH_CHECKSUM 209 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 210 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 211 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 212 213 #define CFG_FLASH_CFI_DRIVER 214 #define CFG_FLASH_CFI 215 #define CFG_FLASH_EMPTY_INFO 216 217 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 218 #define CFG_RAMBOOT 219 #else 220 #undef CFG_RAMBOOT 221 #endif 222 223 #if defined(CFG_RAMBOOT) 224 #undef CONFIG_SPD_EEPROM 225 #define CFG_SDRAM_SIZE 256 226 #endif 227 228 #undef CONFIG_CLOCKS_IN_MHZ 229 230 #define CONFIG_L1_INIT_RAM 231 #define CFG_INIT_RAM_LOCK 1 232 #ifndef CFG_INIT_RAM_LOCK 233 #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 234 #else 235 #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 236 #endif 237 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 238 239 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 240 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 241 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 242 243 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 244 #define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 245 246 /* Serial Port */ 247 #define CONFIG_CONS_INDEX 1 248 #undef CONFIG_SERIAL_SOFTWARE_FIFO 249 #define CFG_NS16550 250 #define CFG_NS16550_SERIAL 251 #define CFG_NS16550_REG_SIZE 1 252 #define CFG_NS16550_CLK get_bus_freq(0) 253 254 #define CFG_BAUDRATE_TABLE \ 255 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 256 257 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 258 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 259 260 /* Use the HUSH parser */ 261 #define CFG_HUSH_PARSER 262 #ifdef CFG_HUSH_PARSER 263 #define CFG_PROMPT_HUSH_PS2 "> " 264 #endif 265 266 /* 267 * Pass open firmware flat tree to kernel 268 */ 269 #define CONFIG_OF_LIBFDT 1 270 #define CONFIG_OF_BOARD_SETUP 1 271 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 272 273 274 #define CFG_64BIT_VSPRINTF 1 275 #define CFG_64BIT_STRTOUL 1 276 277 /* 278 * I2C 279 */ 280 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 281 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 282 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 283 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 284 #define CFG_I2C_SLAVE 0x7F 285 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 286 #define CFG_I2C_OFFSET 0x3100 287 288 /* 289 * RapidIO MMU 290 */ 291 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 292 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 293 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 294 295 /* 296 * General PCI 297 * Addresses are mapped 1-1. 298 */ 299 #define CFG_PCI1_MEM_BASE 0x80000000 300 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 301 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 302 #define CFG_PCI1_IO_BASE 0x00000000 303 #define CFG_PCI1_IO_PHYS 0xe2000000 304 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 305 306 /* PCI view of System Memory */ 307 #define CFG_PCI_MEMORY_BUS 0x00000000 308 #define CFG_PCI_MEMORY_PHYS 0x00000000 309 #define CFG_PCI_MEMORY_SIZE 0x80000000 310 311 /* For RTL8139 */ 312 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 313 #define _IO_BASE 0x00000000 314 315 #define CFG_PCI2_MEM_BASE 0xa0000000 316 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 317 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ 318 #define CFG_PCI2_IO_BASE 0x00000000 319 #define CFG_PCI2_IO_PHYS 0xe3000000 320 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ 321 322 #if defined(CONFIG_PCI) 323 324 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 325 326 #undef CFG_SCSI_SCAN_BUS_REVERSE 327 328 #define CONFIG_NET_MULTI 329 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 330 331 #define CONFIG_RTL8139 332 333 #undef CONFIG_EEPRO100 334 #undef CONFIG_TULIP 335 336 /************************************************************ 337 * USB support 338 ************************************************************/ 339 #define CONFIG_PCI_OHCI 1 340 #define CONFIG_USB_OHCI_NEW 1 341 #define CONFIG_USB_KEYBOARD 1 342 #define CFG_DEVICE_DEREGISTER 343 #define CFG_USB_EVENT_POLL 1 344 #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" 345 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 346 #define CFG_OHCI_SWAP_REG_ACCESS 1 347 348 #if !defined(CONFIG_PCI_PNP) 349 #define PCI_ENET0_IOADDR 0xe0000000 350 #define PCI_ENET0_MEMADDR 0xe0000000 351 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 352 #endif 353 354 /*PCIE video card used*/ 355 #define VIDEO_IO_OFFSET CFG_PCI2_IO_PHYS 356 357 /*PCI video card used*/ 358 /*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ 359 360 /* video */ 361 #define CONFIG_VIDEO 362 363 #if defined(CONFIG_VIDEO) 364 #define CONFIG_BIOSEMU 365 #define CONFIG_CFB_CONSOLE 366 #define CONFIG_VIDEO_SW_CURSOR 367 #define CONFIG_VGA_AS_SINGLE_DEVICE 368 #define CONFIG_ATI_RADEON_FB 369 #define CONFIG_VIDEO_LOGO 370 /*#define CONFIG_CONSOLE_CURSOR*/ 371 #define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS 372 #endif 373 374 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 375 376 #define CONFIG_DOS_PARTITION 377 #define CONFIG_SCSI_AHCI 378 379 #ifdef CONFIG_SCSI_AHCI 380 #define CONFIG_SATA_ULI5288 381 #define CFG_SCSI_MAX_SCSI_ID 4 382 #define CFG_SCSI_MAX_LUN 1 383 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 384 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 385 #endif 386 387 #define CONFIG_MPC86XX_PCI2 388 389 #endif /* CONFIG_PCI */ 390 391 #if defined(CONFIG_TSEC_ENET) 392 393 #ifndef CONFIG_NET_MULTI 394 #define CONFIG_NET_MULTI 1 395 #endif 396 397 #define CONFIG_MII 1 /* MII PHY management */ 398 399 #define CONFIG_TSEC1 1 400 #define CONFIG_TSEC1_NAME "eTSEC1" 401 #define CONFIG_TSEC2 1 402 #define CONFIG_TSEC2_NAME "eTSEC2" 403 #define CONFIG_TSEC3 1 404 #define CONFIG_TSEC3_NAME "eTSEC3" 405 #define CONFIG_TSEC4 1 406 #define CONFIG_TSEC4_NAME "eTSEC4" 407 408 #define TSEC1_PHY_ADDR 0 409 #define TSEC2_PHY_ADDR 1 410 #define TSEC3_PHY_ADDR 2 411 #define TSEC4_PHY_ADDR 3 412 #define TSEC1_PHYIDX 0 413 #define TSEC2_PHYIDX 0 414 #define TSEC3_PHYIDX 0 415 #define TSEC4_PHYIDX 0 416 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 417 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 419 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 420 421 #define CONFIG_ETHPRIME "eTSEC1" 422 423 #endif /* CONFIG_TSEC_ENET */ 424 425 /* 426 * BAT0 2G Cacheable, non-guarded 427 * 0x0000_0000 2G DDR 428 */ 429 #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 430 #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 431 #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 432 #define CFG_IBAT0U CFG_DBAT0U 433 434 /* 435 * BAT1 1G Cache-inhibited, guarded 436 * 0x8000_0000 512M PCI-Express 1 Memory 437 * 0xa000_0000 512M PCI-Express 2 Memory 438 * Changed it for operating from 0xd0000000 439 */ 440 #define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ 441 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 442 #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) 443 #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 444 #define CFG_IBAT1U CFG_DBAT1U 445 446 /* 447 * BAT2 512M Cache-inhibited, guarded 448 * 0xc000_0000 512M RapidIO Memory 449 */ 450 #define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ 451 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 452 #define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 453 #define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 454 #define CFG_IBAT2U CFG_DBAT2U 455 456 /* 457 * BAT3 4M Cache-inhibited, guarded 458 * 0xf800_0000 4M CCSR 459 */ 460 #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ 461 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 462 #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) 463 #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 464 #define CFG_IBAT3U CFG_DBAT3U 465 466 /* 467 * BAT4 32M Cache-inhibited, guarded 468 * 0xe200_0000 16M PCI-Express 1 I/O 469 * 0xe300_0000 16M PCI-Express 2 I/0 470 * Note that this is at 0xe0000000 471 */ 472 #define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ 473 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 474 #define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 475 #define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 476 #define CFG_IBAT4U CFG_DBAT4U 477 478 /* 479 * BAT5 128K Cacheable, non-guarded 480 * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 481 */ 482 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 483 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 484 #define CFG_IBAT5L CFG_DBAT5L 485 #define CFG_IBAT5U CFG_DBAT5U 486 487 /* 488 * BAT6 32M Cache-inhibited, guarded 489 * 0xfe00_0000 32M FLASH 490 */ 491 #define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ 492 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 493 #define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) 494 #define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) 495 #define CFG_IBAT6U CFG_DBAT6U 496 497 #define CFG_DBAT7L 0x00000000 498 #define CFG_DBAT7U 0x00000000 499 #define CFG_IBAT7L 0x00000000 500 #define CFG_IBAT7U 0x00000000 501 502 /* 503 * Environment 504 */ 505 #ifndef CFG_RAMBOOT 506 #define CFG_ENV_IS_IN_FLASH 1 507 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) 508 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 509 #define CFG_ENV_SIZE 0x2000 510 #else 511 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 512 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 513 #define CFG_ENV_SIZE 0x2000 514 #endif 515 516 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 517 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 518 519 520 /* 521 * BOOTP options 522 */ 523 #define CONFIG_BOOTP_BOOTFILESIZE 524 #define CONFIG_BOOTP_BOOTPATH 525 #define CONFIG_BOOTP_GATEWAY 526 #define CONFIG_BOOTP_HOSTNAME 527 528 529 /* 530 * Command line configuration. 531 */ 532 #include <config_cmd_default.h> 533 534 #define CONFIG_CMD_PING 535 #define CONFIG_CMD_I2C 536 537 #if defined(CFG_RAMBOOT) 538 #undef CONFIG_CMD_ENV 539 #endif 540 541 #if defined(CONFIG_PCI) 542 #define CONFIG_CMD_PCI 543 #define CONFIG_CMD_SCSI 544 #define CONFIG_CMD_EXT2 545 #define CONFIG_CMD_USB 546 #endif 547 548 549 #undef CONFIG_WATCHDOG /* watchdog disabled */ 550 551 /* 552 * Miscellaneous configurable options 553 */ 554 #define CFG_LONGHELP /* undef to save memory */ 555 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 556 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 557 558 #if defined(CONFIG_CMD_KGDB) 559 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 560 #else 561 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 562 #endif 563 564 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 565 #define CFG_MAXARGS 16 /* max number of command args */ 566 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 567 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 568 569 /* 570 * For booting Linux, the board info and command line data 571 * have to be in the first 8 MB of memory, since this is 572 * the maximum mapped by the Linux kernel during initialization. 573 */ 574 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 575 576 /* Cache Configuration */ 577 #define CFG_DCACHE_SIZE 32768 578 #define CFG_CACHELINE_SIZE 32 579 #if defined(CONFIG_CMD_KGDB) 580 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ 581 #endif 582 583 /* 584 * Internal Definitions 585 * 586 * Boot Flags 587 */ 588 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 589 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 590 591 #if defined(CONFIG_CMD_KGDB) 592 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 593 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 594 #endif 595 596 /* 597 * Environment Configuration 598 */ 599 600 /* The mac addresses for all ethernet interface */ 601 #if defined(CONFIG_TSEC_ENET) 602 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 603 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 604 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 605 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 606 #endif 607 608 #define CONFIG_HAS_ETH0 1 609 #define CONFIG_HAS_ETH1 1 610 #define CONFIG_HAS_ETH2 1 611 #define CONFIG_HAS_ETH3 1 612 613 #define CONFIG_IPADDR 192.168.1.100 614 615 #define CONFIG_HOSTNAME unknown 616 #define CONFIG_ROOTPATH /opt/nfsroot 617 #define CONFIG_BOOTFILE uImage 618 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 619 620 #define CONFIG_SERVERIP 192.168.1.1 621 #define CONFIG_GATEWAYIP 192.168.1.1 622 #define CONFIG_NETMASK 255.255.255.0 623 624 /* default location for tftp and bootm */ 625 #define CONFIG_LOADADDR 1000000 626 627 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 628 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 629 630 #define CONFIG_BAUDRATE 115200 631 632 #define CONFIG_EXTRA_ENV_SETTINGS \ 633 "netdev=eth0\0" \ 634 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 635 "tftpflash=tftpboot $loadaddr $uboot; " \ 636 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 637 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 638 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 639 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 640 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 641 "consoledev=ttyS0\0" \ 642 "ramdiskaddr=2000000\0" \ 643 "ramdiskfile=your.ramdisk.u-boot\0" \ 644 "fdtaddr=c00000\0" \ 645 "fdtfile=mpc8641_hpcn.dtb\0" \ 646 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 647 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 648 "maxcpus=2" 649 650 651 #define CONFIG_NFSBOOTCOMMAND \ 652 "setenv bootargs root=/dev/nfs rw " \ 653 "nfsroot=$serverip:$rootpath " \ 654 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 655 "console=$consoledev,$baudrate $othbootargs;" \ 656 "tftp $loadaddr $bootfile;" \ 657 "tftp $fdtaddr $fdtfile;" \ 658 "bootm $loadaddr - $fdtaddr" 659 660 #define CONFIG_RAMBOOTCOMMAND \ 661 "setenv bootargs root=/dev/ram rw " \ 662 "console=$consoledev,$baudrate $othbootargs;" \ 663 "tftp $ramdiskaddr $ramdiskfile;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr $ramdiskaddr $fdtaddr" 667 668 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 669 670 #endif /* __CONFIG_H */ 671