1 /* 2 * Copyright 2006, 2010 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_MP 1 /* support multiple processors */ 40 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 41 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ 42 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 43 44 #ifdef RUN_DIAG 45 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 46 #endif 47 48 /* 49 * virtual address to be used for temporary mappings. There 50 * should be 128k free at this VA. 51 */ 52 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 53 54 /* 55 * set this to enable Rapid IO. PCI and RIO are mutually exclusive 56 */ 57 /*#define CONFIG_RIO 1*/ 58 59 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ 60 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 61 #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ 62 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ 63 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 65 #endif 66 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 67 68 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 69 #define CONFIG_ENV_OVERWRITE 70 71 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 72 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 73 74 #define CONFIG_ALTIVEC 1 75 76 /* 77 * L2CR setup -- make sure this is right for your board! 78 */ 79 #define CONFIG_SYS_L2 80 #define L2_INIT 0 81 #define L2_ENABLE (L2CR_L2E) 82 83 #ifndef CONFIG_SYS_CLK_FREQ 84 #ifndef __ASSEMBLY__ 85 extern unsigned long get_board_sys_clk(unsigned long dummy); 86 #endif 87 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 88 #endif 89 90 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 91 92 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 93 #define CONFIG_SYS_MEMTEST_END 0x00400000 94 95 /* 96 * With the exception of PCI Memory and Rapid IO, most devices will simply 97 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 98 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 99 */ 100 #ifdef CONFIG_PHYS_64BIT 101 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL 102 #else 103 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 104 #endif 105 106 /* 107 * Base addresses -- Note these are effective addresses where the 108 * actual resources get mapped (not physical addresses) 109 */ 110 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 111 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 112 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 113 114 /* Physical addresses */ 115 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 118 #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 119 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) 120 #else 121 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 122 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 123 #endif 124 125 /* 126 * DDR Setup 127 */ 128 #define CONFIG_FSL_DDR2 129 #undef CONFIG_FSL_DDR_INTERACTIVE 130 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 131 #define CONFIG_DDR_SPD 132 133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 134 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 135 136 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 137 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 138 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 139 #define CONFIG_VERY_BIG_RAM 140 141 #define CONFIG_NUM_DDR_CONTROLLERS 2 142 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 143 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 144 145 /* 146 * I2C addresses of SPD EEPROMs 147 */ 148 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 149 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 150 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 151 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 152 153 154 /* 155 * These are used when DDR doesn't use SPD. 156 */ 157 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 158 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 159 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 160 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 161 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 162 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 163 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 164 #define CONFIG_SYS_DDR_MODE_1 0x00480432 165 #define CONFIG_SYS_DDR_MODE_2 0x00000000 166 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 167 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 168 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 169 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 170 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 171 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 172 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 173 174 #define CONFIG_ID_EEPROM 175 #define CONFIG_SYS_I2C_EEPROM_NXID 176 #define CONFIG_ID_EEPROM 177 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 178 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 179 180 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 181 #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ 182 | CONFIG_SYS_PHYS_ADDR_HIGH) 183 184 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 185 186 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 187 | 0x00001001) /* port size 16bit */ 188 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 189 190 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 191 | 0x00001001) /* port size 16bit */ 192 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 193 194 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 195 | 0x00000801) /* port size 8bit */ 196 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 197 198 /* 199 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 200 * The PIXIS and CF by themselves aren't large enough to take up the 128k 201 * required for the smallest BAT mapping, so there's a 64k hole. 202 */ 203 #define CONFIG_SYS_LBC_BASE 0xffde0000 204 #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ 205 | CONFIG_SYS_PHYS_ADDR_HIGH) 206 207 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 208 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 209 #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) 210 #define PIXIS_SIZE 0x00008000 /* 32k */ 211 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 212 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 213 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 214 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 215 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 216 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 217 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 218 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 219 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 220 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 221 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 222 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 223 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 224 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 225 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 226 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 227 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 228 229 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 230 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 231 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 232 233 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 234 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 235 236 #undef CONFIG_SYS_FLASH_CHECKSUM 237 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 238 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 239 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 240 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 241 242 #define CONFIG_FLASH_CFI_DRIVER 243 #define CONFIG_SYS_FLASH_CFI 244 #define CONFIG_SYS_FLASH_EMPTY_INFO 245 246 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 247 #define CONFIG_SYS_RAMBOOT 248 #else 249 #undef CONFIG_SYS_RAMBOOT 250 #endif 251 252 #if defined(CONFIG_SYS_RAMBOOT) 253 #undef CONFIG_SPD_EEPROM 254 #define CONFIG_SYS_SDRAM_SIZE 256 255 #endif 256 257 #undef CONFIG_CLOCKS_IN_MHZ 258 259 #define CONFIG_SYS_INIT_RAM_LOCK 1 260 #ifndef CONFIG_SYS_INIT_RAM_LOCK 261 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 262 #else 263 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 264 #endif 265 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 266 267 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 268 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 269 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 270 271 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 272 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 273 274 /* Serial Port */ 275 #define CONFIG_CONS_INDEX 1 276 #undef CONFIG_SERIAL_SOFTWARE_FIFO 277 #define CONFIG_SYS_NS16550 278 #define CONFIG_SYS_NS16550_SERIAL 279 #define CONFIG_SYS_NS16550_REG_SIZE 1 280 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 281 282 #define CONFIG_SYS_BAUDRATE_TABLE \ 283 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 284 285 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 286 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 287 288 /* Use the HUSH parser */ 289 #define CONFIG_SYS_HUSH_PARSER 290 #ifdef CONFIG_SYS_HUSH_PARSER 291 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 292 #endif 293 294 /* 295 * Pass open firmware flat tree to kernel 296 */ 297 #define CONFIG_OF_LIBFDT 1 298 #define CONFIG_OF_BOARD_SETUP 1 299 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 300 301 /* 302 * I2C 303 */ 304 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 305 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 306 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 307 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 308 #define CONFIG_SYS_I2C_SLAVE 0x7F 309 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 310 #define CONFIG_SYS_I2C_OFFSET 0x3100 311 312 /* 313 * RapidIO MMU 314 */ 315 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ 316 #ifdef CONFIG_PHYS_64BIT 317 #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL 318 #else 319 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 320 #endif 321 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 322 323 /* 324 * General PCI 325 * Addresses are mapped 1-1. 326 */ 327 328 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 329 #ifdef CONFIG_PHYS_64BIT 330 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 331 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL 332 #else 333 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 334 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT 335 #endif 336 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 337 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 338 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 339 #define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ 340 | CONFIG_SYS_PHYS_ADDR_HIGH) 341 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 342 343 #ifdef CONFIG_PHYS_64BIT 344 /* 345 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 346 * This will increase the amount of PCI address space available for 347 * for mapping RAM. 348 */ 349 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 350 #else 351 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 352 + CONFIG_SYS_PCIE1_MEM_SIZE) 353 #endif 354 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 355 + CONFIG_SYS_PCIE1_MEM_SIZE) 356 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 357 + CONFIG_SYS_PCIE1_MEM_SIZE) 358 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 359 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 360 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 361 + CONFIG_SYS_PCIE1_IO_SIZE) 362 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 363 + CONFIG_SYS_PCIE1_IO_SIZE) 364 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 365 366 #if defined(CONFIG_PCI) 367 368 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 369 370 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 371 372 #define CONFIG_NET_MULTI 373 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 374 375 #define CONFIG_RTL8139 376 377 #undef CONFIG_EEPRO100 378 #undef CONFIG_TULIP 379 380 /************************************************************ 381 * USB support 382 ************************************************************/ 383 #define CONFIG_PCI_OHCI 1 384 #define CONFIG_USB_OHCI_NEW 1 385 #define CONFIG_USB_KEYBOARD 1 386 #define CONFIG_SYS_STDIO_DEREGISTER 387 #define CONFIG_SYS_USB_EVENT_POLL 1 388 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 389 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 390 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 391 392 /*PCIE video card used*/ 393 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 394 395 /*PCI video card used*/ 396 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 397 398 /* video */ 399 #define CONFIG_VIDEO 400 401 #if defined(CONFIG_VIDEO) 402 #define CONFIG_BIOSEMU 403 #define CONFIG_CFB_CONSOLE 404 #define CONFIG_VIDEO_SW_CURSOR 405 #define CONFIG_VGA_AS_SINGLE_DEVICE 406 #define CONFIG_ATI_RADEON_FB 407 #define CONFIG_VIDEO_LOGO 408 /*#define CONFIG_CONSOLE_CURSOR*/ 409 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 410 #endif 411 412 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 413 414 #define CONFIG_DOS_PARTITION 415 #define CONFIG_SCSI_AHCI 416 417 #ifdef CONFIG_SCSI_AHCI 418 #define CONFIG_SATA_ULI5288 419 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 420 #define CONFIG_SYS_SCSI_MAX_LUN 1 421 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 422 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 423 #endif 424 425 #endif /* CONFIG_PCI */ 426 427 #if defined(CONFIG_TSEC_ENET) 428 429 #ifndef CONFIG_NET_MULTI 430 #define CONFIG_NET_MULTI 1 431 #endif 432 433 #define CONFIG_MII 1 /* MII PHY management */ 434 435 #define CONFIG_TSEC1 1 436 #define CONFIG_TSEC1_NAME "eTSEC1" 437 #define CONFIG_TSEC2 1 438 #define CONFIG_TSEC2_NAME "eTSEC2" 439 #define CONFIG_TSEC3 1 440 #define CONFIG_TSEC3_NAME "eTSEC3" 441 #define CONFIG_TSEC4 1 442 #define CONFIG_TSEC4_NAME "eTSEC4" 443 444 #define TSEC1_PHY_ADDR 0 445 #define TSEC2_PHY_ADDR 1 446 #define TSEC3_PHY_ADDR 2 447 #define TSEC4_PHY_ADDR 3 448 #define TSEC1_PHYIDX 0 449 #define TSEC2_PHYIDX 0 450 #define TSEC3_PHYIDX 0 451 #define TSEC4_PHYIDX 0 452 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 453 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 454 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 455 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 456 457 #define CONFIG_ETHPRIME "eTSEC1" 458 459 #endif /* CONFIG_TSEC_ENET */ 460 461 /* Contort an addr into the format needed for BATs */ 462 #ifdef CONFIG_PHYS_64BIT 463 #define BAT_PHYS_ADDR(x) ((unsigned long) \ 464 ((x & 0x00000000ffffffffULL) | \ 465 ((x & 0x0000000e00000000ULL) >> 24) | \ 466 ((x & 0x0000000100000000ULL) >> 30))) 467 #else 468 #define BAT_PHYS_ADDR(x) (x) 469 #endif 470 471 472 /* Put high physical address bits into the BAT format */ 473 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 474 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 475 476 /* 477 * BAT0 DDR 478 */ 479 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 480 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 481 482 /* 483 * BAT1 LBC (PIXIS/CF) 484 */ 485 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 486 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 487 BATL_GUARDEDSTORAGE) 488 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 489 | BATU_VS | BATU_VP) 490 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 491 | BATL_PP_RW | BATL_MEMCOHERENCE) 492 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 493 494 /* if CONFIG_PCI: 495 * BAT2 PCIE1 and PCIE1 MEM 496 * if CONFIG_RIO 497 * BAT2 Rapidio Memory 498 */ 499 #ifdef CONFIG_PCI 500 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ 501 | BATL_PP_RW | BATL_CACHEINHIBIT \ 502 | BATL_GUARDEDSTORAGE) 503 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 504 | BATU_VS | BATU_VP) 505 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ 506 | BATL_PP_RW | BATL_CACHEINHIBIT) 507 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 508 #else /* CONFIG_RIO */ 509 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 510 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 511 BATL_GUARDEDSTORAGE) 512 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ 513 | BATU_VS | BATU_VP) 514 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 515 | BATL_PP_RW | BATL_CACHEINHIBIT) 516 517 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ 518 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 519 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 520 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 521 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 522 #endif 523 524 /* 525 * BAT3 CCSR Space 526 * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs 527 * instead. The assembler chokes on ULL. 528 */ 529 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 530 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 531 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 532 | BATL_PP_RW | BATL_CACHEINHIBIT \ 533 | BATL_GUARDEDSTORAGE) 534 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 535 | BATU_VP) 536 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 537 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 538 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 539 | BATL_PP_RW | BATL_CACHEINHIBIT) 540 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 541 542 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 543 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 544 | BATL_PP_RW | BATL_CACHEINHIBIT \ 545 | BATL_GUARDEDSTORAGE) 546 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 547 | BATU_BL_1M | BATU_VS | BATU_VP) 548 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 549 | BATL_PP_RW | BATL_CACHEINHIBIT) 550 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 551 #endif 552 553 /* 554 * BAT4 PCIE1_IO and PCIE2_IO 555 */ 556 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ 557 | BATL_PP_RW | BATL_CACHEINHIBIT \ 558 | BATL_GUARDEDSTORAGE) 559 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 560 | BATU_VS | BATU_VP) 561 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ 562 | BATL_PP_RW | BATL_CACHEINHIBIT) 563 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 564 565 /* 566 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 567 */ 568 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 569 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 570 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 571 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 572 573 /* 574 * BAT6 FLASH 575 */ 576 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 577 | BATL_PP_RW | BATL_CACHEINHIBIT \ 578 | BATL_GUARDEDSTORAGE) 579 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 580 | BATU_VP) 581 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 582 | BATL_PP_RW | BATL_MEMCOHERENCE) 583 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 584 585 /* Map the last 1M of flash where we're running from reset */ 586 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 587 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 588 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 589 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 590 | BATL_MEMCOHERENCE) 591 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 592 593 /* 594 * BAT7 FREE - used later for tmp mappings 595 */ 596 #define CONFIG_SYS_DBAT7L 0x00000000 597 #define CONFIG_SYS_DBAT7U 0x00000000 598 #define CONFIG_SYS_IBAT7L 0x00000000 599 #define CONFIG_SYS_IBAT7U 0x00000000 600 601 /* 602 * Environment 603 */ 604 #ifndef CONFIG_SYS_RAMBOOT 605 #define CONFIG_ENV_IS_IN_FLASH 1 606 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 607 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 608 #else 609 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 610 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 611 #endif 612 #define CONFIG_ENV_SIZE 0x2000 613 614 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 615 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 616 617 618 /* 619 * BOOTP options 620 */ 621 #define CONFIG_BOOTP_BOOTFILESIZE 622 #define CONFIG_BOOTP_BOOTPATH 623 #define CONFIG_BOOTP_GATEWAY 624 #define CONFIG_BOOTP_HOSTNAME 625 626 627 /* 628 * Command line configuration. 629 */ 630 #include <config_cmd_default.h> 631 632 #define CONFIG_CMD_PING 633 #define CONFIG_CMD_I2C 634 #define CONFIG_CMD_REGINFO 635 636 #if defined(CONFIG_SYS_RAMBOOT) 637 #undef CONFIG_CMD_SAVEENV 638 #endif 639 640 #if defined(CONFIG_PCI) 641 #define CONFIG_CMD_PCI 642 #define CONFIG_CMD_SCSI 643 #define CONFIG_CMD_EXT2 644 #define CONFIG_CMD_USB 645 #endif 646 647 648 #undef CONFIG_WATCHDOG /* watchdog disabled */ 649 650 /* 651 * Miscellaneous configurable options 652 */ 653 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 654 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 655 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 656 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 657 658 #if defined(CONFIG_CMD_KGDB) 659 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 660 #else 661 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 662 #endif 663 664 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 665 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 666 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 667 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 668 669 /* 670 * For booting Linux, the board info and command line data 671 * have to be in the first 8 MB of memory, since this is 672 * the maximum mapped by the Linux kernel during initialization. 673 */ 674 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 675 676 /* 677 * Internal Definitions 678 * 679 * Boot Flags 680 */ 681 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 682 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 683 684 #if defined(CONFIG_CMD_KGDB) 685 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 686 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 687 #endif 688 689 /* 690 * Environment Configuration 691 */ 692 693 /* The mac addresses for all ethernet interface */ 694 #if defined(CONFIG_TSEC_ENET) 695 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 696 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 697 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 698 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 699 #endif 700 701 #define CONFIG_HAS_ETH0 1 702 #define CONFIG_HAS_ETH1 1 703 #define CONFIG_HAS_ETH2 1 704 #define CONFIG_HAS_ETH3 1 705 706 #define CONFIG_IPADDR 192.168.1.100 707 708 #define CONFIG_HOSTNAME unknown 709 #define CONFIG_ROOTPATH /opt/nfsroot 710 #define CONFIG_BOOTFILE uImage 711 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 712 713 #define CONFIG_SERVERIP 192.168.1.1 714 #define CONFIG_GATEWAYIP 192.168.1.1 715 #define CONFIG_NETMASK 255.255.255.0 716 717 /* default location for tftp and bootm */ 718 #define CONFIG_LOADADDR 1000000 719 720 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 721 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 722 723 #define CONFIG_BAUDRATE 115200 724 725 #define CONFIG_EXTRA_ENV_SETTINGS \ 726 "netdev=eth0\0" \ 727 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 728 "tftpflash=tftpboot $loadaddr $uboot; " \ 729 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 730 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 731 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 732 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 733 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 734 "consoledev=ttyS0\0" \ 735 "ramdiskaddr=2000000\0" \ 736 "ramdiskfile=your.ramdisk.u-boot\0" \ 737 "fdtaddr=c00000\0" \ 738 "fdtfile=mpc8641_hpcn.dtb\0" \ 739 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 740 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 741 "maxcpus=2" 742 743 744 #define CONFIG_NFSBOOTCOMMAND \ 745 "setenv bootargs root=/dev/nfs rw " \ 746 "nfsroot=$serverip:$rootpath " \ 747 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 748 "console=$consoledev,$baudrate $othbootargs;" \ 749 "tftp $loadaddr $bootfile;" \ 750 "tftp $fdtaddr $fdtfile;" \ 751 "bootm $loadaddr - $fdtaddr" 752 753 #define CONFIG_RAMBOOTCOMMAND \ 754 "setenv bootargs root=/dev/ram rw " \ 755 "console=$consoledev,$baudrate $othbootargs;" \ 756 "tftp $ramdiskaddr $ramdiskfile;" \ 757 "tftp $loadaddr $bootfile;" \ 758 "tftp $fdtaddr $fdtfile;" \ 759 "bootm $loadaddr $ramdiskaddr $fdtaddr" 760 761 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 762 763 #endif /* __CONFIG_H */ 764