1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * MPC8641HPCN board configuration file 11 * 12 * Make sure you change the MAC address and other network params first, 13 * search for CONFIG_SERVERIP, etc. in this file. 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_MP 1 /* support multiple processors */ 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 23 24 /* 25 * default CCSRBAR is at 0xff700000 26 * assume U-Boot is less than 0.5MB 27 */ 28 29 #ifdef RUN_DIAG 30 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 31 #endif 32 33 /* 34 * virtual address to be used for temporary mappings. There 35 * should be 128k free at this VA. 36 */ 37 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 38 39 #define CONFIG_SYS_SRIO 40 #define CONFIG_SRIO1 /* SRIO port 1 */ 41 42 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ 43 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 47 #define CONFIG_ENV_OVERWRITE 48 49 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 50 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 51 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 52 53 #define CONFIG_ALTIVEC 1 54 55 /* 56 * L2CR setup -- make sure this is right for your board! 57 */ 58 #define CONFIG_SYS_L2 59 #define L2_INIT 0 60 #define L2_ENABLE (L2CR_L2E) 61 62 #ifndef CONFIG_SYS_CLK_FREQ 63 #ifndef __ASSEMBLY__ 64 extern unsigned long get_board_sys_clk(unsigned long dummy); 65 #endif 66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 67 #endif 68 69 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 70 #define CONFIG_SYS_MEMTEST_END 0x00400000 71 72 /* 73 * With the exception of PCI Memory and Rapid IO, most devices will simply 74 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 75 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 76 */ 77 #ifdef CONFIG_PHYS_64BIT 78 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f 79 #else 80 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 81 #endif 82 83 /* 84 * Base addresses -- Note these are effective addresses where the 85 * actual resources get mapped (not physical addresses) 86 */ 87 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 88 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 89 90 /* Physical addresses */ 91 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 92 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH 93 #define CONFIG_SYS_CCSRBAR_PHYS \ 94 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 95 CONFIG_SYS_CCSRBAR_PHYS_HIGH) 96 97 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 98 99 /* 100 * DDR Setup 101 */ 102 #define CONFIG_FSL_DDR_INTERACTIVE 103 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 104 #define CONFIG_DDR_SPD 105 106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 107 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 108 109 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 110 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 111 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 112 #define CONFIG_VERY_BIG_RAM 113 114 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 115 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 116 117 /* 118 * I2C addresses of SPD EEPROMs 119 */ 120 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 121 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 122 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 123 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 124 125 /* 126 * These are used when DDR doesn't use SPD. 127 */ 128 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 129 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 130 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 131 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 132 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 133 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 134 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 135 #define CONFIG_SYS_DDR_MODE_1 0x00480432 136 #define CONFIG_SYS_DDR_MODE_2 0x00000000 137 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 138 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 139 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 140 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 141 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 142 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 143 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 144 145 #define CONFIG_ID_EEPROM 146 #define CONFIG_SYS_I2C_EEPROM_NXID 147 #define CONFIG_ID_EEPROM 148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 150 151 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 152 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE 153 #define CONFIG_SYS_FLASH_BASE_PHYS \ 154 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 155 CONFIG_SYS_PHYS_ADDR_HIGH) 156 157 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 158 159 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 160 | 0x00001001) /* port size 16bit */ 161 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 162 163 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 164 | 0x00001001) /* port size 16bit */ 165 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 166 167 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 168 | 0x00000801) /* port size 8bit */ 169 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 170 171 /* 172 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 173 * The PIXIS and CF by themselves aren't large enough to take up the 128k 174 * required for the smallest BAT mapping, so there's a 64k hole. 175 */ 176 #define CONFIG_SYS_LBC_BASE 0xffde0000 177 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE 178 179 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 180 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 181 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) 182 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ 183 CONFIG_SYS_PHYS_ADDR_HIGH) 184 #define PIXIS_SIZE 0x00008000 /* 32k */ 185 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 186 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 187 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 188 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 189 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 190 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 191 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 192 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 193 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 194 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 195 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 196 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 197 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 198 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 199 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 200 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 201 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 202 203 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 204 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 205 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 206 207 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 208 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 209 210 #undef CONFIG_SYS_FLASH_CHECKSUM 211 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 212 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 214 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 215 216 #define CONFIG_FLASH_CFI_DRIVER 217 #define CONFIG_SYS_FLASH_CFI 218 #define CONFIG_SYS_FLASH_EMPTY_INFO 219 220 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 221 #define CONFIG_SYS_RAMBOOT 222 #else 223 #undef CONFIG_SYS_RAMBOOT 224 #endif 225 226 #if defined(CONFIG_SYS_RAMBOOT) 227 #undef CONFIG_SPD_EEPROM 228 #define CONFIG_SYS_SDRAM_SIZE 256 229 #endif 230 231 #undef CONFIG_CLOCKS_IN_MHZ 232 233 #define CONFIG_SYS_INIT_RAM_LOCK 1 234 #ifndef CONFIG_SYS_INIT_RAM_LOCK 235 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 236 #else 237 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 238 #endif 239 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 240 241 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 242 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 243 244 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 245 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 246 247 /* Serial Port */ 248 #define CONFIG_SYS_NS16550_SERIAL 249 #define CONFIG_SYS_NS16550_REG_SIZE 1 250 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 251 252 #define CONFIG_SYS_BAUDRATE_TABLE \ 253 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 254 255 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 256 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 257 258 /* 259 * I2C 260 */ 261 #define CONFIG_SYS_I2C 262 #define CONFIG_SYS_I2C_FSL 263 #define CONFIG_SYS_FSL_I2C_SPEED 400000 264 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 265 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 266 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 267 268 /* 269 * RapidIO MMU 270 */ 271 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 272 #ifdef CONFIG_PHYS_64BIT 273 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 274 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c 275 #else 276 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE 277 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 278 #endif 279 #define CONFIG_SYS_SRIO1_MEM_PHYS \ 280 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 281 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) 282 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 283 284 /* 285 * General PCI 286 * Addresses are mapped 1-1. 287 */ 288 289 #define CONFIG_SYS_PCIE1_NAME "ULI" 290 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 293 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 294 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c 295 #else 296 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 297 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT 298 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 299 #endif 300 #define CONFIG_SYS_PCIE1_MEM_PHYS \ 301 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 302 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) 303 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 304 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 305 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 306 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT 307 #define CONFIG_SYS_PCIE1_IO_PHYS \ 308 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 309 CONFIG_SYS_PHYS_ADDR_HIGH) 310 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 311 312 #ifdef CONFIG_PHYS_64BIT 313 /* 314 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 315 * This will increase the amount of PCI address space available for 316 * for mapping RAM. 317 */ 318 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 319 #else 320 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 321 + CONFIG_SYS_PCIE1_MEM_SIZE) 322 #endif 323 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 324 + CONFIG_SYS_PCIE1_MEM_SIZE) 325 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ 326 + CONFIG_SYS_PCIE1_MEM_SIZE) 327 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 328 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 329 + CONFIG_SYS_PCIE1_MEM_SIZE) 330 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 331 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 332 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 333 + CONFIG_SYS_PCIE1_IO_SIZE) 334 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ 335 + CONFIG_SYS_PCIE1_IO_SIZE) 336 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 337 + CONFIG_SYS_PCIE1_IO_SIZE) 338 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 339 340 #if defined(CONFIG_PCI) 341 342 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 343 344 #undef CONFIG_EEPRO100 345 #undef CONFIG_TULIP 346 347 /************************************************************ 348 * USB support 349 ************************************************************/ 350 #define CONFIG_PCI_OHCI 1 351 #define CONFIG_USB_OHCI_NEW 1 352 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 353 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 354 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 355 356 /*PCIE video card used*/ 357 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 358 359 /*PCI video card used*/ 360 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 361 362 /* video */ 363 364 #if defined(CONFIG_VIDEO) 365 #define CONFIG_BIOSEMU 366 #define CONFIG_ATI_RADEON_FB 367 #define CONFIG_VIDEO_LOGO 368 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 369 #endif 370 371 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 372 373 #ifdef CONFIG_SCSI_AHCI 374 #define CONFIG_SATA_ULI5288 375 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 376 #define CONFIG_SYS_SCSI_MAX_LUN 1 377 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 378 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 379 #endif 380 381 #endif /* CONFIG_PCI */ 382 383 #if defined(CONFIG_TSEC_ENET) 384 385 #define CONFIG_MII 1 /* MII PHY management */ 386 387 #define CONFIG_TSEC1 1 388 #define CONFIG_TSEC1_NAME "eTSEC1" 389 #define CONFIG_TSEC2 1 390 #define CONFIG_TSEC2_NAME "eTSEC2" 391 #define CONFIG_TSEC3 1 392 #define CONFIG_TSEC3_NAME "eTSEC3" 393 #define CONFIG_TSEC4 1 394 #define CONFIG_TSEC4_NAME "eTSEC4" 395 396 #define TSEC1_PHY_ADDR 0 397 #define TSEC2_PHY_ADDR 1 398 #define TSEC3_PHY_ADDR 2 399 #define TSEC4_PHY_ADDR 3 400 #define TSEC1_PHYIDX 0 401 #define TSEC2_PHYIDX 0 402 #define TSEC3_PHYIDX 0 403 #define TSEC4_PHYIDX 0 404 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 405 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 406 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 407 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 408 409 #define CONFIG_ETHPRIME "eTSEC1" 410 411 #endif /* CONFIG_TSEC_ENET */ 412 413 #ifdef CONFIG_PHYS_64BIT 414 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 415 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 416 417 /* Put physical address into the BAT format */ 418 #define BAT_PHYS_ADDR(low, high) \ 419 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) 420 /* Convert high/low pairs to actual 64-bit value */ 421 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) 422 #else 423 /* 32-bit systems just ignore the "high" bits */ 424 #define BAT_PHYS_ADDR(low, high) (low) 425 #define PAIRED_PHYS_TO_PHYS(low, high) (low) 426 #endif 427 428 /* 429 * BAT0 DDR 430 */ 431 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 432 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 433 434 /* 435 * BAT1 LBC (PIXIS/CF) 436 */ 437 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 438 CONFIG_SYS_PHYS_ADDR_HIGH) \ 439 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 440 BATL_GUARDEDSTORAGE) 441 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 442 | BATU_VS | BATU_VP) 443 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 444 CONFIG_SYS_PHYS_ADDR_HIGH) \ 445 | BATL_PP_RW | BATL_MEMCOHERENCE) 446 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 447 448 /* if CONFIG_PCI: 449 * BAT2 PCIE1 and PCIE1 MEM 450 * if CONFIG_RIO 451 * BAT2 Rapidio Memory 452 */ 453 #ifdef CONFIG_PCI 454 #define CONFIG_PCI_INDIRECT_BRIDGE 455 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 456 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 457 | BATL_PP_RW | BATL_CACHEINHIBIT \ 458 | BATL_GUARDEDSTORAGE) 459 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 460 | BATU_VS | BATU_VP) 461 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 462 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 463 | BATL_PP_RW | BATL_CACHEINHIBIT) 464 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 465 #else /* CONFIG_RIO */ 466 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 467 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 468 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 469 BATL_GUARDEDSTORAGE) 470 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 471 | BATU_VS | BATU_VP) 472 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 473 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 474 | BATL_PP_RW | BATL_CACHEINHIBIT) 475 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 476 #endif 477 478 /* 479 * BAT3 CCSR Space 480 */ 481 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 482 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 483 | BATL_PP_RW | BATL_CACHEINHIBIT \ 484 | BATL_GUARDEDSTORAGE) 485 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 486 | BATU_VP) 487 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 488 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 489 | BATL_PP_RW | BATL_CACHEINHIBIT) 490 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 491 492 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 493 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 494 | BATL_PP_RW | BATL_CACHEINHIBIT \ 495 | BATL_GUARDEDSTORAGE) 496 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 497 | BATU_BL_1M | BATU_VS | BATU_VP) 498 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 499 | BATL_PP_RW | BATL_CACHEINHIBIT) 500 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 501 #endif 502 503 /* 504 * BAT4 PCIE1_IO and PCIE2_IO 505 */ 506 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 507 CONFIG_SYS_PHYS_ADDR_HIGH) \ 508 | BATL_PP_RW | BATL_CACHEINHIBIT \ 509 | BATL_GUARDEDSTORAGE) 510 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 511 | BATU_VS | BATU_VP) 512 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 513 CONFIG_SYS_PHYS_ADDR_HIGH) \ 514 | BATL_PP_RW | BATL_CACHEINHIBIT) 515 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 516 517 /* 518 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 519 */ 520 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 521 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 522 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 523 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 524 525 /* 526 * BAT6 FLASH 527 */ 528 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 529 CONFIG_SYS_PHYS_ADDR_HIGH) \ 530 | BATL_PP_RW | BATL_CACHEINHIBIT \ 531 | BATL_GUARDEDSTORAGE) 532 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 533 | BATU_VP) 534 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 535 CONFIG_SYS_PHYS_ADDR_HIGH) \ 536 | BATL_PP_RW | BATL_MEMCOHERENCE) 537 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 538 539 /* Map the last 1M of flash where we're running from reset */ 540 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 541 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 542 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 543 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 544 | BATL_MEMCOHERENCE) 545 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 546 547 /* 548 * BAT7 FREE - used later for tmp mappings 549 */ 550 #define CONFIG_SYS_DBAT7L 0x00000000 551 #define CONFIG_SYS_DBAT7U 0x00000000 552 #define CONFIG_SYS_IBAT7L 0x00000000 553 #define CONFIG_SYS_IBAT7U 0x00000000 554 555 /* 556 * Environment 557 */ 558 #ifndef CONFIG_SYS_RAMBOOT 559 #define CONFIG_ENV_ADDR \ 560 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 561 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 562 #else 563 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 564 #endif 565 #define CONFIG_ENV_SIZE 0x2000 566 567 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 568 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 569 570 /* 571 * BOOTP options 572 */ 573 #define CONFIG_BOOTP_BOOTFILESIZE 574 575 #undef CONFIG_WATCHDOG /* watchdog disabled */ 576 577 /* 578 * Miscellaneous configurable options 579 */ 580 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 581 582 /* 583 * For booting Linux, the board info and command line data 584 * have to be in the first 8 MB of memory, since this is 585 * the maximum mapped by the Linux kernel during initialization. 586 */ 587 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 588 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 589 590 #if defined(CONFIG_CMD_KGDB) 591 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 592 #endif 593 594 /* 595 * Environment Configuration 596 */ 597 598 #define CONFIG_HAS_ETH0 1 599 #define CONFIG_HAS_ETH1 1 600 #define CONFIG_HAS_ETH2 1 601 #define CONFIG_HAS_ETH3 1 602 603 #define CONFIG_IPADDR 192.168.1.100 604 605 #define CONFIG_HOSTNAME "unknown" 606 #define CONFIG_ROOTPATH "/opt/nfsroot" 607 #define CONFIG_BOOTFILE "uImage" 608 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 609 610 #define CONFIG_SERVERIP 192.168.1.1 611 #define CONFIG_GATEWAYIP 192.168.1.1 612 #define CONFIG_NETMASK 255.255.255.0 613 614 /* default location for tftp and bootm */ 615 #define CONFIG_LOADADDR 0x10000000 616 617 #define CONFIG_EXTRA_ENV_SETTINGS \ 618 "netdev=eth0\0" \ 619 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 620 "tftpflash=tftpboot $loadaddr $uboot; " \ 621 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 622 " +$filesize; " \ 623 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 624 " +$filesize; " \ 625 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 626 " $filesize; " \ 627 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 628 " +$filesize; " \ 629 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 630 " $filesize\0" \ 631 "consoledev=ttyS0\0" \ 632 "ramdiskaddr=0x18000000\0" \ 633 "ramdiskfile=your.ramdisk.u-boot\0" \ 634 "fdtaddr=0x17c00000\0" \ 635 "fdtfile=mpc8641_hpcn.dtb\0" \ 636 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 637 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 638 "maxcpus=2" 639 640 #define CONFIG_NFSBOOTCOMMAND \ 641 "setenv bootargs root=/dev/nfs rw " \ 642 "nfsroot=$serverip:$rootpath " \ 643 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 644 "console=$consoledev,$baudrate $othbootargs;" \ 645 "tftp $loadaddr $bootfile;" \ 646 "tftp $fdtaddr $fdtfile;" \ 647 "bootm $loadaddr - $fdtaddr" 648 649 #define CONFIG_RAMBOOTCOMMAND \ 650 "setenv bootargs root=/dev/ram rw " \ 651 "console=$consoledev,$baudrate $othbootargs;" \ 652 "tftp $ramdiskaddr $ramdiskfile;" \ 653 "tftp $loadaddr $bootfile;" \ 654 "tftp $fdtaddr $fdtfile;" \ 655 "bootm $loadaddr $ramdiskaddr $fdtaddr" 656 657 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 658 659 #endif /* __CONFIG_H */ 660