1 /* 2 * Copyright 2006, 2010-2011 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * MPC8641HPCN board configuration file 11 * 12 * Make sure you change the MAC address and other network params first, 13 * search for CONFIG_SERVERIP, etc. in this file. 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 /* High Level Configuration Options */ 22 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 23 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 24 #define CONFIG_MP 1 /* support multiple processors */ 25 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 26 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 27 28 /* 29 * default CCSRBAR is at 0xff700000 30 * assume U-Boot is less than 0.5MB 31 */ 32 #define CONFIG_SYS_TEXT_BASE 0xeff00000 33 34 #ifdef RUN_DIAG 35 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 36 #endif 37 38 /* 39 * virtual address to be used for temporary mappings. There 40 * should be 128k free at this VA. 41 */ 42 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 43 44 #define CONFIG_SYS_SRIO 45 #define CONFIG_SRIO1 /* SRIO port 1 */ 46 47 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 48 #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ 49 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 52 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 57 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 58 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 59 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 60 61 #define CONFIG_ALTIVEC 1 62 63 /* 64 * L2CR setup -- make sure this is right for your board! 65 */ 66 #define CONFIG_SYS_L2 67 #define L2_INIT 0 68 #define L2_ENABLE (L2CR_L2E) 69 70 #ifndef CONFIG_SYS_CLK_FREQ 71 #ifndef __ASSEMBLY__ 72 extern unsigned long get_board_sys_clk(unsigned long dummy); 73 #endif 74 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 75 #endif 76 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 /* 81 * With the exception of PCI Memory and Rapid IO, most devices will simply 82 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 83 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 84 */ 85 #ifdef CONFIG_PHYS_64BIT 86 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f 87 #else 88 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 89 #endif 90 91 /* 92 * Base addresses -- Note these are effective addresses where the 93 * actual resources get mapped (not physical addresses) 94 */ 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 96 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 97 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 98 99 /* Physical addresses */ 100 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 101 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH 102 #define CONFIG_SYS_CCSRBAR_PHYS \ 103 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 104 CONFIG_SYS_CCSRBAR_PHYS_HIGH) 105 106 #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ 107 108 /* 109 * DDR Setup 110 */ 111 #define CONFIG_SYS_FSL_DDR2 112 #undef CONFIG_FSL_DDR_INTERACTIVE 113 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 114 #define CONFIG_DDR_SPD 115 116 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 117 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 118 119 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 120 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 121 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 122 #define CONFIG_VERY_BIG_RAM 123 124 #define CONFIG_NUM_DDR_CONTROLLERS 2 125 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 126 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 127 128 /* 129 * I2C addresses of SPD EEPROMs 130 */ 131 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 132 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 133 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 134 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 135 136 /* 137 * These are used when DDR doesn't use SPD. 138 */ 139 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 141 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 142 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 143 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 144 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 145 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 146 #define CONFIG_SYS_DDR_MODE_1 0x00480432 147 #define CONFIG_SYS_DDR_MODE_2 0x00000000 148 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 149 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 150 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 151 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 152 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 153 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 154 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 155 156 #define CONFIG_ID_EEPROM 157 #define CONFIG_SYS_I2C_EEPROM_NXID 158 #define CONFIG_ID_EEPROM 159 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 160 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 161 162 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 163 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE 164 #define CONFIG_SYS_FLASH_BASE_PHYS \ 165 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 166 CONFIG_SYS_PHYS_ADDR_HIGH) 167 168 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 169 170 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 171 | 0x00001001) /* port size 16bit */ 172 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 173 174 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 175 | 0x00001001) /* port size 16bit */ 176 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 177 178 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 179 | 0x00000801) /* port size 8bit */ 180 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 181 182 /* 183 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 184 * The PIXIS and CF by themselves aren't large enough to take up the 128k 185 * required for the smallest BAT mapping, so there's a 64k hole. 186 */ 187 #define CONFIG_SYS_LBC_BASE 0xffde0000 188 #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE 189 190 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 191 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 192 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) 193 #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ 194 CONFIG_SYS_PHYS_ADDR_HIGH) 195 #define PIXIS_SIZE 0x00008000 /* 32k */ 196 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 197 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 198 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 199 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 200 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 201 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 202 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 203 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 204 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 205 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 206 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ 207 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ 208 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 209 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 210 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 211 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 212 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 213 214 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 215 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 216 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 220 221 #undef CONFIG_SYS_FLASH_CHECKSUM 222 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 223 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 224 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 225 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 226 227 #define CONFIG_FLASH_CFI_DRIVER 228 #define CONFIG_SYS_FLASH_CFI 229 #define CONFIG_SYS_FLASH_EMPTY_INFO 230 231 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 232 #define CONFIG_SYS_RAMBOOT 233 #else 234 #undef CONFIG_SYS_RAMBOOT 235 #endif 236 237 #if defined(CONFIG_SYS_RAMBOOT) 238 #undef CONFIG_SPD_EEPROM 239 #define CONFIG_SYS_SDRAM_SIZE 256 240 #endif 241 242 #undef CONFIG_CLOCKS_IN_MHZ 243 244 #define CONFIG_SYS_INIT_RAM_LOCK 1 245 #ifndef CONFIG_SYS_INIT_RAM_LOCK 246 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 247 #else 248 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 249 #endif 250 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 251 252 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 253 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 254 255 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 256 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 257 258 /* Serial Port */ 259 #define CONFIG_CONS_INDEX 1 260 #define CONFIG_SYS_NS16550_SERIAL 261 #define CONFIG_SYS_NS16550_REG_SIZE 1 262 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 263 264 #define CONFIG_SYS_BAUDRATE_TABLE \ 265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 266 267 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 268 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 269 270 /* 271 * I2C 272 */ 273 #define CONFIG_SYS_I2C 274 #define CONFIG_SYS_I2C_FSL 275 #define CONFIG_SYS_FSL_I2C_SPEED 400000 276 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 277 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 278 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 279 280 /* 281 * RapidIO MMU 282 */ 283 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ 284 #ifdef CONFIG_PHYS_64BIT 285 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 286 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c 287 #else 288 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE 289 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 290 #endif 291 #define CONFIG_SYS_SRIO1_MEM_PHYS \ 292 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 293 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) 294 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ 295 296 /* 297 * General PCI 298 * Addresses are mapped 1-1. 299 */ 300 301 #define CONFIG_SYS_PCIE1_NAME "ULI" 302 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 303 #ifdef CONFIG_PHYS_64BIT 304 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 305 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 306 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c 307 #else 308 #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT 309 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT 310 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 311 #endif 312 #define CONFIG_SYS_PCIE1_MEM_PHYS \ 313 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 314 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) 315 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 316 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 317 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 318 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT 319 #define CONFIG_SYS_PCIE1_IO_PHYS \ 320 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 321 CONFIG_SYS_PHYS_ADDR_HIGH) 322 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ 323 324 #ifdef CONFIG_PHYS_64BIT 325 /* 326 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. 327 * This will increase the amount of PCI address space available for 328 * for mapping RAM. 329 */ 330 #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS 331 #else 332 #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ 333 + CONFIG_SYS_PCIE1_MEM_SIZE) 334 #endif 335 #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ 336 + CONFIG_SYS_PCIE1_MEM_SIZE) 337 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ 338 + CONFIG_SYS_PCIE1_MEM_SIZE) 339 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 340 #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ 341 + CONFIG_SYS_PCIE1_MEM_SIZE) 342 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 343 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 344 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ 345 + CONFIG_SYS_PCIE1_IO_SIZE) 346 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ 347 + CONFIG_SYS_PCIE1_IO_SIZE) 348 #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ 349 + CONFIG_SYS_PCIE1_IO_SIZE) 350 #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE 351 352 #if defined(CONFIG_PCI) 353 354 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 355 356 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 357 358 #undef CONFIG_EEPRO100 359 #undef CONFIG_TULIP 360 361 /************************************************************ 362 * USB support 363 ************************************************************/ 364 #define CONFIG_PCI_OHCI 1 365 #define CONFIG_USB_OHCI_NEW 1 366 #define CONFIG_USB_KEYBOARD 1 367 #define CONFIG_SYS_STDIO_DEREGISTER 368 #define CONFIG_SYS_USB_EVENT_POLL 1 369 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 370 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 371 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 372 373 /*PCIE video card used*/ 374 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT 375 376 /*PCI video card used*/ 377 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ 378 379 /* video */ 380 #define CONFIG_VIDEO 381 382 #if defined(CONFIG_VIDEO) 383 #define CONFIG_BIOSEMU 384 #define CONFIG_CFB_CONSOLE 385 #define CONFIG_VIDEO_SW_CURSOR 386 #define CONFIG_VGA_AS_SINGLE_DEVICE 387 #define CONFIG_ATI_RADEON_FB 388 #define CONFIG_VIDEO_LOGO 389 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT 390 #endif 391 392 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 393 394 #define CONFIG_DOS_PARTITION 395 #define CONFIG_SCSI_AHCI 396 397 #ifdef CONFIG_SCSI_AHCI 398 #define CONFIG_LIBATA 399 #define CONFIG_SATA_ULI5288 400 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 401 #define CONFIG_SYS_SCSI_MAX_LUN 1 402 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 403 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 404 #endif 405 406 #endif /* CONFIG_PCI */ 407 408 #if defined(CONFIG_TSEC_ENET) 409 410 #define CONFIG_MII 1 /* MII PHY management */ 411 412 #define CONFIG_TSEC1 1 413 #define CONFIG_TSEC1_NAME "eTSEC1" 414 #define CONFIG_TSEC2 1 415 #define CONFIG_TSEC2_NAME "eTSEC2" 416 #define CONFIG_TSEC3 1 417 #define CONFIG_TSEC3_NAME "eTSEC3" 418 #define CONFIG_TSEC4 1 419 #define CONFIG_TSEC4_NAME "eTSEC4" 420 421 #define TSEC1_PHY_ADDR 0 422 #define TSEC2_PHY_ADDR 1 423 #define TSEC3_PHY_ADDR 2 424 #define TSEC4_PHY_ADDR 3 425 #define TSEC1_PHYIDX 0 426 #define TSEC2_PHYIDX 0 427 #define TSEC3_PHYIDX 0 428 #define TSEC4_PHYIDX 0 429 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 430 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 431 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 432 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 433 434 #define CONFIG_ETHPRIME "eTSEC1" 435 436 #endif /* CONFIG_TSEC_ENET */ 437 438 #ifdef CONFIG_PHYS_64BIT 439 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 440 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 441 442 /* Put physical address into the BAT format */ 443 #define BAT_PHYS_ADDR(low, high) \ 444 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) 445 /* Convert high/low pairs to actual 64-bit value */ 446 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) 447 #else 448 /* 32-bit systems just ignore the "high" bits */ 449 #define BAT_PHYS_ADDR(low, high) (low) 450 #define PAIRED_PHYS_TO_PHYS(low, high) (low) 451 #endif 452 453 /* 454 * BAT0 DDR 455 */ 456 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 457 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 458 459 /* 460 * BAT1 LBC (PIXIS/CF) 461 */ 462 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 463 CONFIG_SYS_PHYS_ADDR_HIGH) \ 464 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 465 BATL_GUARDEDSTORAGE) 466 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 467 | BATU_VS | BATU_VP) 468 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ 469 CONFIG_SYS_PHYS_ADDR_HIGH) \ 470 | BATL_PP_RW | BATL_MEMCOHERENCE) 471 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 472 473 /* if CONFIG_PCI: 474 * BAT2 PCIE1 and PCIE1 MEM 475 * if CONFIG_RIO 476 * BAT2 Rapidio Memory 477 */ 478 #ifdef CONFIG_PCI 479 #define CONFIG_PCI_INDIRECT_BRIDGE 480 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 481 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 482 | BATL_PP_RW | BATL_CACHEINHIBIT \ 483 | BATL_GUARDEDSTORAGE) 484 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ 485 | BATU_VS | BATU_VP) 486 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ 487 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ 488 | BATL_PP_RW | BATL_CACHEINHIBIT) 489 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 490 #else /* CONFIG_RIO */ 491 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 492 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 493 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 494 BATL_GUARDEDSTORAGE) 495 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ 496 | BATU_VS | BATU_VP) 497 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ 498 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ 499 | BATL_PP_RW | BATL_CACHEINHIBIT) 500 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 501 #endif 502 503 /* 504 * BAT3 CCSR Space 505 */ 506 #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 507 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 508 | BATL_PP_RW | BATL_CACHEINHIBIT \ 509 | BATL_GUARDEDSTORAGE) 510 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 511 | BATU_VP) 512 #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ 513 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 514 | BATL_PP_RW | BATL_CACHEINHIBIT) 515 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 516 517 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 518 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 519 | BATL_PP_RW | BATL_CACHEINHIBIT \ 520 | BATL_GUARDEDSTORAGE) 521 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 522 | BATU_BL_1M | BATU_VS | BATU_VP) 523 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 524 | BATL_PP_RW | BATL_CACHEINHIBIT) 525 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 526 #endif 527 528 /* 529 * BAT4 PCIE1_IO and PCIE2_IO 530 */ 531 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 532 CONFIG_SYS_PHYS_ADDR_HIGH) \ 533 | BATL_PP_RW | BATL_CACHEINHIBIT \ 534 | BATL_GUARDEDSTORAGE) 535 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ 536 | BATU_VS | BATU_VP) 537 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ 538 CONFIG_SYS_PHYS_ADDR_HIGH) \ 539 | BATL_PP_RW | BATL_CACHEINHIBIT) 540 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 541 542 /* 543 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 544 */ 545 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 546 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 547 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 548 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 549 550 /* 551 * BAT6 FLASH 552 */ 553 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 554 CONFIG_SYS_PHYS_ADDR_HIGH) \ 555 | BATL_PP_RW | BATL_CACHEINHIBIT \ 556 | BATL_GUARDEDSTORAGE) 557 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 558 | BATU_VP) 559 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ 560 CONFIG_SYS_PHYS_ADDR_HIGH) \ 561 | BATL_PP_RW | BATL_MEMCOHERENCE) 562 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 563 564 /* Map the last 1M of flash where we're running from reset */ 565 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 566 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 567 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 568 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 569 | BATL_MEMCOHERENCE) 570 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 571 572 /* 573 * BAT7 FREE - used later for tmp mappings 574 */ 575 #define CONFIG_SYS_DBAT7L 0x00000000 576 #define CONFIG_SYS_DBAT7U 0x00000000 577 #define CONFIG_SYS_IBAT7L 0x00000000 578 #define CONFIG_SYS_IBAT7U 0x00000000 579 580 /* 581 * Environment 582 */ 583 #ifndef CONFIG_SYS_RAMBOOT 584 #define CONFIG_ENV_IS_IN_FLASH 1 585 #define CONFIG_ENV_ADDR \ 586 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 587 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 588 #else 589 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 590 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 591 #endif 592 #define CONFIG_ENV_SIZE 0x2000 593 594 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 595 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 596 597 /* 598 * BOOTP options 599 */ 600 #define CONFIG_BOOTP_BOOTFILESIZE 601 #define CONFIG_BOOTP_BOOTPATH 602 #define CONFIG_BOOTP_GATEWAY 603 #define CONFIG_BOOTP_HOSTNAME 604 605 /* 606 * Command line configuration. 607 */ 608 #define CONFIG_CMD_REGINFO 609 610 #if defined(CONFIG_PCI) 611 #define CONFIG_CMD_PCI 612 #define CONFIG_SCSI 613 #endif 614 615 #undef CONFIG_WATCHDOG /* watchdog disabled */ 616 617 /* 618 * Miscellaneous configurable options 619 */ 620 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 621 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 622 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 623 624 #if defined(CONFIG_CMD_KGDB) 625 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 626 #else 627 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 628 #endif 629 630 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 631 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 632 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 633 634 /* 635 * For booting Linux, the board info and command line data 636 * have to be in the first 8 MB of memory, since this is 637 * the maximum mapped by the Linux kernel during initialization. 638 */ 639 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 640 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 641 642 #if defined(CONFIG_CMD_KGDB) 643 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 644 #endif 645 646 /* 647 * Environment Configuration 648 */ 649 650 #define CONFIG_HAS_ETH0 1 651 #define CONFIG_HAS_ETH1 1 652 #define CONFIG_HAS_ETH2 1 653 #define CONFIG_HAS_ETH3 1 654 655 #define CONFIG_IPADDR 192.168.1.100 656 657 #define CONFIG_HOSTNAME unknown 658 #define CONFIG_ROOTPATH "/opt/nfsroot" 659 #define CONFIG_BOOTFILE "uImage" 660 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 661 662 #define CONFIG_SERVERIP 192.168.1.1 663 #define CONFIG_GATEWAYIP 192.168.1.1 664 #define CONFIG_NETMASK 255.255.255.0 665 666 /* default location for tftp and bootm */ 667 #define CONFIG_LOADADDR 0x10000000 668 669 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 670 671 #define CONFIG_BAUDRATE 115200 672 673 #define CONFIG_EXTRA_ENV_SETTINGS \ 674 "netdev=eth0\0" \ 675 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 676 "tftpflash=tftpboot $loadaddr $uboot; " \ 677 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 678 " +$filesize; " \ 679 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 680 " +$filesize; " \ 681 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 682 " $filesize; " \ 683 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 684 " +$filesize; " \ 685 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 686 " $filesize\0" \ 687 "consoledev=ttyS0\0" \ 688 "ramdiskaddr=0x18000000\0" \ 689 "ramdiskfile=your.ramdisk.u-boot\0" \ 690 "fdtaddr=0x17c00000\0" \ 691 "fdtfile=mpc8641_hpcn.dtb\0" \ 692 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 693 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 694 "maxcpus=2" 695 696 #define CONFIG_NFSBOOTCOMMAND \ 697 "setenv bootargs root=/dev/nfs rw " \ 698 "nfsroot=$serverip:$rootpath " \ 699 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 700 "console=$consoledev,$baudrate $othbootargs;" \ 701 "tftp $loadaddr $bootfile;" \ 702 "tftp $fdtaddr $fdtfile;" \ 703 "bootm $loadaddr - $fdtaddr" 704 705 #define CONFIG_RAMBOOTCOMMAND \ 706 "setenv bootargs root=/dev/ram rw " \ 707 "console=$consoledev,$baudrate $othbootargs;" \ 708 "tftp $ramdiskaddr $ramdiskfile;" \ 709 "tftp $loadaddr $bootfile;" \ 710 "tftp $fdtaddr $fdtfile;" \ 711 "bootm $loadaddr $ramdiskaddr $fdtaddr" 712 713 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 714 715 #endif /* __CONFIG_H */ 716