1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 /* 26 * MPC8641HPCN board configuration file 27 * 28 * Make sure you change the MAC address and other network params first, 29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* High Level Configuration Options */ 36 #define CONFIG_MPC86xx 1 /* MPC86xx */ 37 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 38 #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ 39 #define CONFIG_MP 1 /* support multiple processors */ 40 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 41 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 42 /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ 43 #define CONFIG_ADDR_MAP 1 /* Use addr map */ 44 45 #ifdef RUN_DIAG 46 #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE 47 #endif 48 49 /* 50 * virtual address to be used for temporary mappings. There 51 * should be 128k free at this VA. 52 */ 53 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 54 55 /* 56 * set this to enable Rapid IO. PCI and RIO are mutually exclusive 57 */ 58 /*#define CONFIG_RIO 1*/ 59 60 #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ 61 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 62 #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ 63 #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ 64 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 65 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 66 #endif 67 #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ 68 69 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 70 #define CONFIG_ENV_OVERWRITE 71 72 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 73 #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ 74 75 #define CONFIG_ALTIVEC 1 76 77 /* 78 * L2CR setup -- make sure this is right for your board! 79 */ 80 #define CONFIG_SYS_L2 81 #define L2_INIT 0 82 #define L2_ENABLE (L2CR_L2E) 83 84 #ifndef CONFIG_SYS_CLK_FREQ 85 #ifndef __ASSEMBLY__ 86 extern unsigned long get_board_sys_clk(unsigned long dummy); 87 #endif 88 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 89 #endif 90 91 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 92 93 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 94 #define CONFIG_SYS_MEMTEST_END 0x00400000 95 96 /* 97 * With the exception of PCI Memory and Rapid IO, most devices will simply 98 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA 99 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. 100 */ 101 #ifdef CONFIG_PHYS_64BIT 102 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL 103 #else 104 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 105 #endif 106 107 /* 108 * Base addresses -- Note these are effective addresses where the 109 * actual resources get mapped (not physical addresses) 110 */ 111 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 112 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 113 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 114 115 /* Physical addresses */ 116 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 117 #ifdef CONFIG_PHYS_64BIT 118 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 119 #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 120 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) 121 #else 122 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 123 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 124 #endif 125 126 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 127 #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 128 129 /* 130 * DDR Setup 131 */ 132 #define CONFIG_FSL_DDR2 133 #undef CONFIG_FSL_DDR_INTERACTIVE 134 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 135 #define CONFIG_DDR_SPD 136 137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 138 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 139 140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 141 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 142 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 143 #define CONFIG_VERY_BIG_RAM 144 145 #define MPC86xx_DDR_SDRAM_CLK_CNTL 146 147 #define CONFIG_NUM_DDR_CONTROLLERS 2 148 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 149 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 150 151 /* 152 * I2C addresses of SPD EEPROMs 153 */ 154 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 155 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ 156 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ 157 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ 158 159 160 /* 161 * These are used when DDR doesn't use SPD. 162 */ 163 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 164 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 165 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 166 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 167 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 168 #define CONFIG_SYS_DDR_TIMING_1 0x39357322 169 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 170 #define CONFIG_SYS_DDR_MODE_1 0x00480432 171 #define CONFIG_SYS_DDR_MODE_2 0x00000000 172 #define CONFIG_SYS_DDR_INTERVAL 0x06090100 173 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 174 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 175 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 176 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 177 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 178 #define CONFIG_SYS_DDR_CONTROL2 0x04400000 179 180 #define CONFIG_ID_EEPROM 181 #define CONFIG_SYS_I2C_EEPROM_NXID 182 #define CONFIG_ID_EEPROM 183 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 184 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 185 186 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ 187 #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ 188 | CONFIG_SYS_PHYS_ADDR_HIGH) 189 190 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 191 192 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 193 | 0x00001001) /* port size 16bit */ 194 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ 195 196 #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ 197 | 0x00001001) /* port size 16bit */ 198 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ 199 200 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ 201 | 0x00000801) /* port size 8bit */ 202 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ 203 204 /* 205 * The LBC_BASE is the base of the region that contains the PIXIS and the CF. 206 * The PIXIS and CF by themselves aren't large enough to take up the 128k 207 * required for the smallest BAT mapping, so there's a 64k hole. 208 */ 209 #define CONFIG_SYS_LBC_BASE 0xffde0000 210 #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ 211 | CONFIG_SYS_PHYS_ADDR_HIGH) 212 213 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 214 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) 215 #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) 216 #define PIXIS_SIZE 0x00008000 /* 32k */ 217 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 218 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 219 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 220 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 221 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ 222 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 223 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 224 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 225 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 226 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 227 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 228 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 229 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 230 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 231 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ 232 233 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ 234 #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) 235 #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) 236 237 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 238 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 239 240 #undef CONFIG_SYS_FLASH_CHECKSUM 241 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 242 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 243 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 244 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 245 246 #define CONFIG_FLASH_CFI_DRIVER 247 #define CONFIG_SYS_FLASH_CFI 248 #define CONFIG_SYS_FLASH_EMPTY_INFO 249 250 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 251 #define CONFIG_SYS_RAMBOOT 252 #else 253 #undef CONFIG_SYS_RAMBOOT 254 #endif 255 256 #if defined(CONFIG_SYS_RAMBOOT) 257 #undef CONFIG_SPD_EEPROM 258 #define CONFIG_SYS_SDRAM_SIZE 256 259 #endif 260 261 #undef CONFIG_CLOCKS_IN_MHZ 262 263 #define CONFIG_SYS_INIT_RAM_LOCK 1 264 #ifndef CONFIG_SYS_INIT_RAM_LOCK 265 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ 266 #else 267 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ 268 #endif 269 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 270 271 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 272 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 273 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 274 275 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 276 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 277 278 /* Serial Port */ 279 #define CONFIG_CONS_INDEX 1 280 #undef CONFIG_SERIAL_SOFTWARE_FIFO 281 #define CONFIG_SYS_NS16550 282 #define CONFIG_SYS_NS16550_SERIAL 283 #define CONFIG_SYS_NS16550_REG_SIZE 1 284 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 285 286 #define CONFIG_SYS_BAUDRATE_TABLE \ 287 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 288 289 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 290 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 291 292 /* Use the HUSH parser */ 293 #define CONFIG_SYS_HUSH_PARSER 294 #ifdef CONFIG_SYS_HUSH_PARSER 295 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 296 #endif 297 298 /* 299 * Pass open firmware flat tree to kernel 300 */ 301 #define CONFIG_OF_LIBFDT 1 302 #define CONFIG_OF_BOARD_SETUP 1 303 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 304 305 306 #define CONFIG_SYS_64BIT_VSPRINTF 1 307 #define CONFIG_SYS_64BIT_STRTOUL 1 308 309 /* 310 * I2C 311 */ 312 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 313 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 314 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 315 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 316 #define CONFIG_SYS_I2C_SLAVE 0x7F 317 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 318 #define CONFIG_SYS_I2C_OFFSET 0x3100 319 320 /* 321 * RapidIO MMU 322 */ 323 #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ 324 #ifdef CONFIG_PHYS_64BIT 325 #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL 326 #else 327 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 328 #endif 329 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 330 331 /* 332 * General PCI 333 * Addresses are mapped 1-1. 334 */ 335 336 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 337 #ifdef CONFIG_PHYS_64BIT 338 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 339 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL 340 #else 341 #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT 342 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT 343 #endif 344 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 345 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 346 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 347 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ 348 | CONFIG_SYS_PHYS_ADDR_HIGH) 349 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ 350 351 /* For RTL8139 */ 352 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 353 #define _IO_BASE 0x00000000 354 355 #ifdef CONFIG_PHYS_64BIT 356 /* 357 * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. 358 * This will increase the amount of PCI address space available for 359 * for mapping RAM. 360 */ 361 #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS 362 #else 363 #define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ 364 + CONFIG_SYS_PCI1_MEM_SIZE) 365 #endif 366 #define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ 367 + CONFIG_SYS_PCI1_MEM_SIZE) 368 #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ 369 + CONFIG_SYS_PCI1_MEM_SIZE) 370 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ 371 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 372 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ 373 + CONFIG_SYS_PCI1_IO_SIZE) 374 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ 375 + CONFIG_SYS_PCI1_IO_SIZE) 376 #define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE 377 378 #if defined(CONFIG_PCI) 379 380 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 381 382 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 383 384 #define CONFIG_NET_MULTI 385 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 386 387 #define CONFIG_RTL8139 388 389 #undef CONFIG_EEPRO100 390 #undef CONFIG_TULIP 391 392 /************************************************************ 393 * USB support 394 ************************************************************/ 395 #define CONFIG_PCI_OHCI 1 396 #define CONFIG_USB_OHCI_NEW 1 397 #define CONFIG_USB_KEYBOARD 1 398 #define CONFIG_SYS_DEVICE_DEREGISTER 399 #define CONFIG_SYS_USB_EVENT_POLL 1 400 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 401 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 402 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 403 404 /*PCIE video card used*/ 405 #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT 406 407 /*PCI video card used*/ 408 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 409 410 /* video */ 411 #define CONFIG_VIDEO 412 413 #if defined(CONFIG_VIDEO) 414 #define CONFIG_BIOSEMU 415 #define CONFIG_CFB_CONSOLE 416 #define CONFIG_VIDEO_SW_CURSOR 417 #define CONFIG_VGA_AS_SINGLE_DEVICE 418 #define CONFIG_ATI_RADEON_FB 419 #define CONFIG_VIDEO_LOGO 420 /*#define CONFIG_CONSOLE_CURSOR*/ 421 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT 422 #endif 423 424 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 425 426 #define CONFIG_DOS_PARTITION 427 #define CONFIG_SCSI_AHCI 428 429 #ifdef CONFIG_SCSI_AHCI 430 #define CONFIG_SATA_ULI5288 431 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 432 #define CONFIG_SYS_SCSI_MAX_LUN 1 433 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 434 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 435 #endif 436 437 #define CONFIG_MPC86XX_PCI2 438 439 #endif /* CONFIG_PCI */ 440 441 #if defined(CONFIG_TSEC_ENET) 442 443 #ifndef CONFIG_NET_MULTI 444 #define CONFIG_NET_MULTI 1 445 #endif 446 447 #define CONFIG_MII 1 /* MII PHY management */ 448 449 #define CONFIG_TSEC1 1 450 #define CONFIG_TSEC1_NAME "eTSEC1" 451 #define CONFIG_TSEC2 1 452 #define CONFIG_TSEC2_NAME "eTSEC2" 453 #define CONFIG_TSEC3 1 454 #define CONFIG_TSEC3_NAME "eTSEC3" 455 #define CONFIG_TSEC4 1 456 #define CONFIG_TSEC4_NAME "eTSEC4" 457 458 #define TSEC1_PHY_ADDR 0 459 #define TSEC2_PHY_ADDR 1 460 #define TSEC3_PHY_ADDR 2 461 #define TSEC4_PHY_ADDR 3 462 #define TSEC1_PHYIDX 0 463 #define TSEC2_PHYIDX 0 464 #define TSEC3_PHYIDX 0 465 #define TSEC4_PHYIDX 0 466 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 467 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 468 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 469 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 470 471 #define CONFIG_ETHPRIME "eTSEC1" 472 473 #endif /* CONFIG_TSEC_ENET */ 474 475 /* Contort an addr into the format needed for BATs */ 476 #ifdef CONFIG_PHYS_64BIT 477 #define BAT_PHYS_ADDR(x) ((unsigned long) \ 478 ((x & 0x00000000ffffffffULL) | \ 479 ((x & 0x0000000e00000000ULL) >> 24) | \ 480 ((x & 0x0000000100000000ULL) >> 30))) 481 #else 482 #define BAT_PHYS_ADDR(x) (x) 483 #endif 484 485 486 /* Put high physical address bits into the BAT format */ 487 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) 488 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) 489 490 /* 491 * BAT0 DDR 492 */ 493 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 494 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 495 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 496 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 497 498 /* 499 * BAT1 LBC (PIXIS/CF) 500 */ 501 #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 502 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 503 BATL_GUARDEDSTORAGE) 504 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ 505 | BATU_VS | BATU_VP) 506 #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ 507 | BATL_PP_RW | BATL_MEMCOHERENCE) 508 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 509 510 /* if CONFIG_PCI: 511 * BAT2 PCI1 and PCI1 MEM 512 * if CONFIG_RIO 513 * BAT2 Rapidio Memory 514 */ 515 #ifdef CONFIG_PCI 516 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ 517 | BATL_PP_RW | BATL_CACHEINHIBIT \ 518 | BATL_GUARDEDSTORAGE) 519 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \ 520 | BATU_VS | BATU_VP) 521 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ 522 | BATL_PP_RW | BATL_CACHEINHIBIT) 523 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 524 #else /* CONFIG_RIO */ 525 #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 526 | BATL_PP_RW | BATL_CACHEINHIBIT | \ 527 BATL_GUARDEDSTORAGE) 528 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ 529 | BATU_VS | BATU_VP) 530 #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ 531 | BATL_PP_RW | BATL_CACHEINHIBIT) 532 533 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ 534 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 535 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) 536 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 537 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 538 #endif 539 540 /* 541 * BAT3 CCSR Space 542 * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs 543 * instead. The assembler chokes on ULL. 544 */ 545 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 546 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 547 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 548 | BATL_PP_RW | BATL_CACHEINHIBIT \ 549 | BATL_GUARDEDSTORAGE) 550 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ 551 | BATU_VP) 552 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ 553 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 554 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ 555 | BATL_PP_RW | BATL_CACHEINHIBIT) 556 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 557 558 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 559 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 560 | BATL_PP_RW | BATL_CACHEINHIBIT \ 561 | BATL_GUARDEDSTORAGE) 562 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 563 | BATU_BL_1M | BATU_VS | BATU_VP) 564 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 565 | BATL_PP_RW | BATL_CACHEINHIBIT) 566 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 567 #endif 568 569 /* 570 * BAT4 PCI1_IO and PCI2_IO 571 */ 572 #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ 573 | BATL_PP_RW | BATL_CACHEINHIBIT \ 574 | BATL_GUARDEDSTORAGE) 575 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \ 576 | BATU_VS | BATU_VP) 577 #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ 578 | BATL_PP_RW | BATL_CACHEINHIBIT) 579 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 580 581 /* 582 * BAT5 Init RAM for stack in the CPU DCache (no backing memory) 583 */ 584 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 585 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 586 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 587 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 588 589 /* 590 * BAT6 FLASH 591 */ 592 #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 593 | BATL_PP_RW | BATL_CACHEINHIBIT \ 594 | BATL_GUARDEDSTORAGE) 595 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ 596 | BATU_VP) 597 #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 598 | BATL_PP_RW | BATL_MEMCOHERENCE) 599 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 600 601 /* Map the last 1M of flash where we're running from reset */ 602 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 603 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 604 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 605 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 606 | BATL_MEMCOHERENCE) 607 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 608 609 /* 610 * BAT7 FREE - used later for tmp mappings 611 */ 612 #define CONFIG_SYS_DBAT7L 0x00000000 613 #define CONFIG_SYS_DBAT7U 0x00000000 614 #define CONFIG_SYS_IBAT7L 0x00000000 615 #define CONFIG_SYS_IBAT7U 0x00000000 616 617 /* 618 * Environment 619 */ 620 #ifndef CONFIG_SYS_RAMBOOT 621 #define CONFIG_ENV_IS_IN_FLASH 1 622 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 623 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 624 #else 625 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 626 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 627 #endif 628 #define CONFIG_ENV_SIZE 0x2000 629 630 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 631 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 632 633 634 /* 635 * BOOTP options 636 */ 637 #define CONFIG_BOOTP_BOOTFILESIZE 638 #define CONFIG_BOOTP_BOOTPATH 639 #define CONFIG_BOOTP_GATEWAY 640 #define CONFIG_BOOTP_HOSTNAME 641 642 643 /* 644 * Command line configuration. 645 */ 646 #include <config_cmd_default.h> 647 648 #define CONFIG_CMD_PING 649 #define CONFIG_CMD_I2C 650 #define CONFIG_CMD_REGINFO 651 652 #if defined(CONFIG_SYS_RAMBOOT) 653 #undef CONFIG_CMD_SAVEENV 654 #endif 655 656 #if defined(CONFIG_PCI) 657 #define CONFIG_CMD_PCI 658 #define CONFIG_CMD_SCSI 659 #define CONFIG_CMD_EXT2 660 #define CONFIG_CMD_USB 661 #endif 662 663 664 #undef CONFIG_WATCHDOG /* watchdog disabled */ 665 666 /* 667 * Miscellaneous configurable options 668 */ 669 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 670 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 671 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 672 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 673 674 #if defined(CONFIG_CMD_KGDB) 675 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 676 #else 677 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 678 #endif 679 680 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 681 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 682 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 683 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 684 685 /* 686 * For booting Linux, the board info and command line data 687 * have to be in the first 8 MB of memory, since this is 688 * the maximum mapped by the Linux kernel during initialization. 689 */ 690 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 691 692 /* 693 * Internal Definitions 694 * 695 * Boot Flags 696 */ 697 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 698 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 699 700 #if defined(CONFIG_CMD_KGDB) 701 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 702 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 703 #endif 704 705 /* 706 * Environment Configuration 707 */ 708 709 /* The mac addresses for all ethernet interface */ 710 #if defined(CONFIG_TSEC_ENET) 711 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 712 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD 713 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD 714 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD 715 #endif 716 717 #define CONFIG_HAS_ETH0 1 718 #define CONFIG_HAS_ETH1 1 719 #define CONFIG_HAS_ETH2 1 720 #define CONFIG_HAS_ETH3 1 721 722 #define CONFIG_IPADDR 192.168.1.100 723 724 #define CONFIG_HOSTNAME unknown 725 #define CONFIG_ROOTPATH /opt/nfsroot 726 #define CONFIG_BOOTFILE uImage 727 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 728 729 #define CONFIG_SERVERIP 192.168.1.1 730 #define CONFIG_GATEWAYIP 192.168.1.1 731 #define CONFIG_NETMASK 255.255.255.0 732 733 /* default location for tftp and bootm */ 734 #define CONFIG_LOADADDR 1000000 735 736 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 737 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 738 739 #define CONFIG_BAUDRATE 115200 740 741 #define CONFIG_EXTRA_ENV_SETTINGS \ 742 "netdev=eth0\0" \ 743 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 744 "tftpflash=tftpboot $loadaddr $uboot; " \ 745 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 746 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 747 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 748 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 749 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 750 "consoledev=ttyS0\0" \ 751 "ramdiskaddr=2000000\0" \ 752 "ramdiskfile=your.ramdisk.u-boot\0" \ 753 "fdtaddr=c00000\0" \ 754 "fdtfile=mpc8641_hpcn.dtb\0" \ 755 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ 756 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ 757 "maxcpus=2" 758 759 760 #define CONFIG_NFSBOOTCOMMAND \ 761 "setenv bootargs root=/dev/nfs rw " \ 762 "nfsroot=$serverip:$rootpath " \ 763 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 764 "console=$consoledev,$baudrate $othbootargs;" \ 765 "tftp $loadaddr $bootfile;" \ 766 "tftp $fdtaddr $fdtfile;" \ 767 "bootm $loadaddr - $fdtaddr" 768 769 #define CONFIG_RAMBOOTCOMMAND \ 770 "setenv bootargs root=/dev/ram rw " \ 771 "console=$consoledev,$baudrate $othbootargs;" \ 772 "tftp $ramdiskaddr $ramdiskfile;" \ 773 "tftp $loadaddr $bootfile;" \ 774 "tftp $fdtaddr $fdtfile;" \ 775 "bootm $loadaddr $ramdiskaddr $fdtaddr" 776 777 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 778 779 #endif /* __CONFIG_H */ 780