1 /*
2  * Copyright 2006, 2010-2011 Freescale Semiconductor.
3  *
4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 /*
10  * MPC8641HPCN board configuration file
11  *
12  * Make sure you change the MAC address and other network params first,
13  * search for CONFIG_SERVERIP, etc. in this file.
14  */
15 
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18 
19 /* High Level Configuration Options */
20 #define CONFIG_MP		1	/* support multiple processors */
21 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
22 #define CONFIG_ADDR_MAP		1	/* Use addr map */
23 
24 /*
25  * default CCSRBAR is at 0xff700000
26  * assume U-Boot is less than 0.5MB
27  */
28 #define	CONFIG_SYS_TEXT_BASE	0xeff00000
29 
30 #ifdef RUN_DIAG
31 #define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
32 #endif
33 
34 /*
35  * virtual address to be used for temporary mappings.  There
36  * should be 128k free at this VA.
37  */
38 #define CONFIG_SYS_SCRATCH_VA	0xe0000000
39 
40 #define CONFIG_SYS_SRIO
41 #define CONFIG_SRIO1			/* SRIO port 1 */
42 
43 #define CONFIG_PCIE1		1	/* PCIE controller 1 (ULI bridge) */
44 #define CONFIG_PCIE2		1	/* PCIE controller 2 (slot) */
45 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
46 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
47 
48 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
49 #define CONFIG_ENV_OVERWRITE
50 
51 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
52 #define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
53 #define CONFIG_SYS_NUM_ADDR_MAP 8	/* Number of addr map slots = 8 dbats */
54 
55 #define CONFIG_ALTIVEC		1
56 
57 /*
58  * L2CR setup -- make sure this is right for your board!
59  */
60 #define CONFIG_SYS_L2
61 #define L2_INIT		0
62 #define L2_ENABLE	(L2CR_L2E)
63 
64 #ifndef CONFIG_SYS_CLK_FREQ
65 #ifndef __ASSEMBLY__
66 extern unsigned long get_board_sys_clk(unsigned long dummy);
67 #endif
68 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
69 #endif
70 
71 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
72 #define CONFIG_SYS_MEMTEST_END		0x00400000
73 
74 /*
75  * With the exception of PCI Memory and Rapid IO, most devices will simply
76  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
77  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
78  */
79 #ifdef CONFIG_PHYS_64BIT
80 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
81 #else
82 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
83 #endif
84 
85 /*
86  * Base addresses -- Note these are effective addresses where the
87  * actual resources get mapped (not physical addresses)
88  */
89 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
90 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
91 
92 /* Physical addresses */
93 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
94 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
95 #define CONFIG_SYS_CCSRBAR_PHYS \
96 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
97 			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
98 
99 #define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
100 
101 /*
102  * DDR Setup
103  */
104 #undef CONFIG_FSL_DDR_INTERACTIVE
105 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
106 #define CONFIG_DDR_SPD
107 
108 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
109 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
110 
111 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
112 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
113 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
114 #define CONFIG_VERY_BIG_RAM
115 
116 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
117 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
118 
119 /*
120  * I2C addresses of SPD EEPROMs
121  */
122 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
123 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
124 #define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
125 #define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
126 
127 /*
128  * These are used when DDR doesn't use SPD.
129  */
130 #define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
131 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
132 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
133 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
134 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
135 #define CONFIG_SYS_DDR_TIMING_1	0x39357322
136 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
137 #define CONFIG_SYS_DDR_MODE_1		0x00480432
138 #define CONFIG_SYS_DDR_MODE_2		0x00000000
139 #define CONFIG_SYS_DDR_INTERVAL	0x06090100
140 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
141 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
142 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
143 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
144 #define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
145 #define CONFIG_SYS_DDR_CONTROL2	0x04400000
146 
147 #define CONFIG_ID_EEPROM
148 #define CONFIG_SYS_I2C_EEPROM_NXID
149 #define CONFIG_ID_EEPROM
150 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
151 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
152 
153 #define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
154 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
155 #define CONFIG_SYS_FLASH_BASE_PHYS \
156 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
157 			    CONFIG_SYS_PHYS_ADDR_HIGH)
158 
159 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
160 
161 #define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
162 				 | 0x00001001)	/* port size 16bit */
163 #define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
164 
165 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
166 				 | 0x00001001)	/* port size 16bit */
167 #define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
168 
169 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
170 				 | 0x00000801) /* port size 8bit */
171 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
172 
173 /*
174  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
175  * The PIXIS and CF by themselves aren't large enough to take up the 128k
176  * required for the smallest BAT mapping, so there's a 64k hole.
177  */
178 #define CONFIG_SYS_LBC_BASE		0xffde0000
179 #define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
180 
181 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
182 #define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
183 #define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
184 #define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
185 						    CONFIG_SYS_PHYS_ADDR_HIGH)
186 #define PIXIS_SIZE		0x00008000	/* 32k */
187 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
188 #define PIXIS_VER		0x1	/* Board version at offset 1 */
189 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
190 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
191 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
192 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
193 #define PIXIS_VCTL		0x10	/* VELA Control Register */
194 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
195 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
196 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
197 #define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
198 #define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
199 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
200 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
201 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
202 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
203 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
204 
205 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
206 #define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
207 #define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
208 
209 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
210 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
211 
212 #undef	CONFIG_SYS_FLASH_CHECKSUM
213 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
214 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
215 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
216 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
217 
218 #define CONFIG_FLASH_CFI_DRIVER
219 #define CONFIG_SYS_FLASH_CFI
220 #define CONFIG_SYS_FLASH_EMPTY_INFO
221 
222 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
223 #define CONFIG_SYS_RAMBOOT
224 #else
225 #undef	CONFIG_SYS_RAMBOOT
226 #endif
227 
228 #if defined(CONFIG_SYS_RAMBOOT)
229 #undef CONFIG_SPD_EEPROM
230 #define CONFIG_SYS_SDRAM_SIZE	256
231 #endif
232 
233 #undef CONFIG_CLOCKS_IN_MHZ
234 
235 #define CONFIG_SYS_INIT_RAM_LOCK	1
236 #ifndef CONFIG_SYS_INIT_RAM_LOCK
237 #define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
238 #else
239 #define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
240 #endif
241 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
242 
243 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
244 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
245 
246 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
247 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
248 
249 /* Serial Port */
250 #define CONFIG_CONS_INDEX     1
251 #define CONFIG_SYS_NS16550_SERIAL
252 #define CONFIG_SYS_NS16550_REG_SIZE	1
253 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
254 
255 #define CONFIG_SYS_BAUDRATE_TABLE  \
256 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
257 
258 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
259 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
260 
261 /*
262  * I2C
263  */
264 #define CONFIG_SYS_I2C
265 #define CONFIG_SYS_I2C_FSL
266 #define CONFIG_SYS_FSL_I2C_SPEED	400000
267 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
268 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
269 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
270 
271 /*
272  * RapidIO MMU
273  */
274 #define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
275 #ifdef CONFIG_PHYS_64BIT
276 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
277 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
278 #else
279 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
280 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
281 #endif
282 #define CONFIG_SYS_SRIO1_MEM_PHYS \
283 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
284 			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
285 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
286 
287 /*
288  * General PCI
289  * Addresses are mapped 1-1.
290  */
291 
292 #define CONFIG_SYS_PCIE1_NAME		"ULI"
293 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
294 #ifdef CONFIG_PHYS_64BIT
295 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
296 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
297 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
298 #else
299 #define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
300 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
301 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
302 #endif
303 #define CONFIG_SYS_PCIE1_MEM_PHYS \
304 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
305 			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
306 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
307 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
308 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
309 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
310 #define CONFIG_SYS_PCIE1_IO_PHYS \
311 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
312 			    CONFIG_SYS_PHYS_ADDR_HIGH)
313 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
314 
315 #ifdef CONFIG_PHYS_64BIT
316 /*
317  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
318  * This will increase the amount of PCI address space available for
319  * for mapping RAM.
320  */
321 #define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
322 #else
323 #define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
324 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
325 #endif
326 #define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
327 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
328 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
329 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
330 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
331 #define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
332 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
333 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
334 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
335 #define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
336 					 + CONFIG_SYS_PCIE1_IO_SIZE)
337 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
338 					 + CONFIG_SYS_PCIE1_IO_SIZE)
339 #define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
340 					 + CONFIG_SYS_PCIE1_IO_SIZE)
341 #define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
342 
343 #if defined(CONFIG_PCI)
344 
345 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
346 
347 #undef CONFIG_EEPRO100
348 #undef CONFIG_TULIP
349 
350 /************************************************************
351  * USB support
352  ************************************************************/
353 #define CONFIG_PCI_OHCI			1
354 #define CONFIG_USB_OHCI_NEW		1
355 #define CONFIG_SYS_USB_EVENT_POLL		1
356 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
357 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
358 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
359 
360 /*PCIE video card used*/
361 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
362 
363 /*PCI video card used*/
364 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
365 
366 /* video */
367 
368 #if defined(CONFIG_VIDEO)
369 #define CONFIG_BIOSEMU
370 #define CONFIG_ATI_RADEON_FB
371 #define CONFIG_VIDEO_LOGO
372 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
373 #endif
374 
375 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
376 
377 #define CONFIG_DOS_PARTITION
378 #define CONFIG_SCSI_AHCI
379 
380 #ifdef CONFIG_SCSI_AHCI
381 #define CONFIG_LIBATA
382 #define CONFIG_SATA_ULI5288
383 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
384 #define CONFIG_SYS_SCSI_MAX_LUN	1
385 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
386 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
387 #endif
388 
389 #endif	/* CONFIG_PCI */
390 
391 #if defined(CONFIG_TSEC_ENET)
392 
393 #define CONFIG_MII		1	/* MII PHY management */
394 
395 #define CONFIG_TSEC1		1
396 #define CONFIG_TSEC1_NAME	"eTSEC1"
397 #define CONFIG_TSEC2		1
398 #define CONFIG_TSEC2_NAME	"eTSEC2"
399 #define CONFIG_TSEC3		1
400 #define CONFIG_TSEC3_NAME	"eTSEC3"
401 #define CONFIG_TSEC4		1
402 #define CONFIG_TSEC4_NAME	"eTSEC4"
403 
404 #define TSEC1_PHY_ADDR		0
405 #define TSEC2_PHY_ADDR		1
406 #define TSEC3_PHY_ADDR		2
407 #define TSEC4_PHY_ADDR		3
408 #define TSEC1_PHYIDX		0
409 #define TSEC2_PHYIDX		0
410 #define TSEC3_PHYIDX		0
411 #define TSEC4_PHYIDX		0
412 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
413 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
414 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
415 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
416 
417 #define CONFIG_ETHPRIME		"eTSEC1"
418 
419 #endif	/* CONFIG_TSEC_ENET */
420 
421 #ifdef CONFIG_PHYS_64BIT
422 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
423 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
424 
425 /* Put physical address into the BAT format */
426 #define BAT_PHYS_ADDR(low, high) \
427 	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
428 /* Convert high/low pairs to actual 64-bit value */
429 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
430 #else
431 /* 32-bit systems just ignore the "high" bits */
432 #define BAT_PHYS_ADDR(low, high)        (low)
433 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
434 #endif
435 
436 /*
437  * BAT0		DDR
438  */
439 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
440 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
441 
442 /*
443  * BAT1		LBC (PIXIS/CF)
444  */
445 #define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
446 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
447 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
448 				 BATL_GUARDEDSTORAGE)
449 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
450 				 | BATU_VS | BATU_VP)
451 #define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
452 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
453 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
454 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
455 
456 /* if CONFIG_PCI:
457  * BAT2		PCIE1 and PCIE1 MEM
458  * if CONFIG_RIO
459  * BAT2		Rapidio Memory
460  */
461 #ifdef CONFIG_PCI
462 #define CONFIG_PCI_INDIRECT_BRIDGE
463 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
464 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
465 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
466 				 | BATL_GUARDEDSTORAGE)
467 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
468 				 | BATU_VS | BATU_VP)
469 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
470 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
471 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
472 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
473 #else /* CONFIG_RIO */
474 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
475 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
476 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
477 				 BATL_GUARDEDSTORAGE)
478 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
479 				 | BATU_VS | BATU_VP)
480 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
481 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
482 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
483 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
484 #endif
485 
486 /*
487  * BAT3		CCSR Space
488  */
489 #define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
490 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
491 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
492 				 | BATL_GUARDEDSTORAGE)
493 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
494 				 | BATU_VP)
495 #define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
496 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
497 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
498 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
499 
500 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
501 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
502 				       | BATL_PP_RW | BATL_CACHEINHIBIT \
503 				       | BATL_GUARDEDSTORAGE)
504 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
505 				       | BATU_BL_1M | BATU_VS | BATU_VP)
506 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
507 				       | BATL_PP_RW | BATL_CACHEINHIBIT)
508 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
509 #endif
510 
511 /*
512  * BAT4		PCIE1_IO and PCIE2_IO
513  */
514 #define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
515 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
516 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
517 				 | BATL_GUARDEDSTORAGE)
518 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
519 				 | BATU_VS | BATU_VP)
520 #define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
521 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
522 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
523 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
524 
525 /*
526  * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
527  */
528 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
529 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
530 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
531 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
532 
533 /*
534  * BAT6		FLASH
535  */
536 #define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
537 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
538 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
539 				 | BATL_GUARDEDSTORAGE)
540 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
541 				 | BATU_VP)
542 #define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
543 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
544 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
545 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
546 
547 /* Map the last 1M of flash where we're running from reset */
548 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
549 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
550 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
551 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
552 				 | BATL_MEMCOHERENCE)
553 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
554 
555 /*
556  * BAT7		FREE - used later for tmp mappings
557  */
558 #define CONFIG_SYS_DBAT7L 0x00000000
559 #define CONFIG_SYS_DBAT7U 0x00000000
560 #define CONFIG_SYS_IBAT7L 0x00000000
561 #define CONFIG_SYS_IBAT7U 0x00000000
562 
563 /*
564  * Environment
565  */
566 #ifndef CONFIG_SYS_RAMBOOT
567     #define CONFIG_ENV_IS_IN_FLASH	1
568     #define CONFIG_ENV_ADDR		\
569 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
570     #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
571 #else
572     #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
573     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
574 #endif
575 #define CONFIG_ENV_SIZE		0x2000
576 
577 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
578 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
579 
580 /*
581  * BOOTP options
582  */
583 #define CONFIG_BOOTP_BOOTFILESIZE
584 #define CONFIG_BOOTP_BOOTPATH
585 #define CONFIG_BOOTP_GATEWAY
586 #define CONFIG_BOOTP_HOSTNAME
587 
588 /*
589  * Command line configuration.
590  */
591 #define CONFIG_CMD_REGINFO
592 
593 #if defined(CONFIG_PCI)
594     #define CONFIG_CMD_PCI
595     #define CONFIG_SCSI
596 #endif
597 
598 #undef CONFIG_WATCHDOG			/* watchdog disabled */
599 
600 /*
601  * Miscellaneous configurable options
602  */
603 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
604 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
605 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
606 
607 #if defined(CONFIG_CMD_KGDB)
608     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
609 #else
610     #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
611 #endif
612 
613 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
614 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
615 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
616 
617 /*
618  * For booting Linux, the board info and command line data
619  * have to be in the first 8 MB of memory, since this is
620  * the maximum mapped by the Linux kernel during initialization.
621  */
622 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
623 #define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
624 
625 #if defined(CONFIG_CMD_KGDB)
626     #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
627 #endif
628 
629 /*
630  * Environment Configuration
631  */
632 
633 #define CONFIG_HAS_ETH0		1
634 #define CONFIG_HAS_ETH1		1
635 #define CONFIG_HAS_ETH2		1
636 #define CONFIG_HAS_ETH3		1
637 
638 #define CONFIG_IPADDR		192.168.1.100
639 
640 #define CONFIG_HOSTNAME		unknown
641 #define CONFIG_ROOTPATH		"/opt/nfsroot"
642 #define CONFIG_BOOTFILE		"uImage"
643 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
644 
645 #define CONFIG_SERVERIP		192.168.1.1
646 #define CONFIG_GATEWAYIP	192.168.1.1
647 #define CONFIG_NETMASK		255.255.255.0
648 
649 /* default location for tftp and bootm */
650 #define CONFIG_LOADADDR		0x10000000
651 
652 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
653 
654 #define CONFIG_BAUDRATE	115200
655 
656 #define	CONFIG_EXTRA_ENV_SETTINGS					\
657 	"netdev=eth0\0"							\
658 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
659 	"tftpflash=tftpboot $loadaddr $uboot; "				\
660 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
661 			" +$filesize; "	\
662 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
663 			" +$filesize; "	\
664 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
665 			" $filesize; "	\
666 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
667 			" +$filesize; "	\
668 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
669 			" $filesize\0"	\
670 	"consoledev=ttyS0\0"						\
671 	"ramdiskaddr=0x18000000\0"						\
672 	"ramdiskfile=your.ramdisk.u-boot\0"				\
673 	"fdtaddr=0x17c00000\0"						\
674 	"fdtfile=mpc8641_hpcn.dtb\0"					\
675 	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
676 	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
677 	"maxcpus=2"
678 
679 #define CONFIG_NFSBOOTCOMMAND						\
680 	"setenv bootargs root=/dev/nfs rw "				\
681 	      "nfsroot=$serverip:$rootpath "				\
682 	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
683 	      "console=$consoledev,$baudrate $othbootargs;"		\
684 	"tftp $loadaddr $bootfile;"					\
685 	"tftp $fdtaddr $fdtfile;"					\
686 	"bootm $loadaddr - $fdtaddr"
687 
688 #define CONFIG_RAMBOOTCOMMAND						\
689 	"setenv bootargs root=/dev/ram rw "				\
690 	      "console=$consoledev,$baudrate $othbootargs;"		\
691 	"tftp $ramdiskaddr $ramdiskfile;"				\
692 	"tftp $loadaddr $bootfile;"					\
693 	"tftp $fdtaddr $fdtfile;"					\
694 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
695 
696 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
697 
698 #endif	/* __CONFIG_H */
699