1 /*
2  * Copyright 2006, 2010-2011 Freescale Semiconductor.
3  *
4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 /*
10  * MPC8641HPCN board configuration file
11  *
12  * Make sure you change the MAC address and other network params first,
13  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
14  */
15 
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18 
19 /* High Level Configuration Options */
20 #define CONFIG_MPC86xx		1	/* MPC86xx */
21 #define CONFIG_MPC8641		1	/* MPC8641 specific */
22 #define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
23 #define CONFIG_MP		1	/* support multiple processors */
24 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
25 /*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
26 #define CONFIG_ADDR_MAP		1	/* Use addr map */
27 
28 /*
29  * default CCSRBAR is at 0xff700000
30  * assume U-Boot is less than 0.5MB
31  */
32 #define	CONFIG_SYS_TEXT_BASE	0xeff00000
33 
34 #ifdef RUN_DIAG
35 #define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
36 #endif
37 
38 /*
39  * virtual address to be used for temporary mappings.  There
40  * should be 128k free at this VA.
41  */
42 #define CONFIG_SYS_SCRATCH_VA	0xe0000000
43 
44 #define CONFIG_SYS_SRIO
45 #define CONFIG_SRIO1			/* SRIO port 1 */
46 
47 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
48 #define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
49 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
50 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
51 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
52 #define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
53 
54 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
55 #define CONFIG_ENV_OVERWRITE
56 
57 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
58 #define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
59 #define CONFIG_SYS_NUM_ADDR_MAP 8	/* Number of addr map slots = 8 dbats */
60 
61 #define CONFIG_ALTIVEC		1
62 
63 /*
64  * L2CR setup -- make sure this is right for your board!
65  */
66 #define CONFIG_SYS_L2
67 #define L2_INIT		0
68 #define L2_ENABLE	(L2CR_L2E)
69 
70 #ifndef CONFIG_SYS_CLK_FREQ
71 #ifndef __ASSEMBLY__
72 extern unsigned long get_board_sys_clk(unsigned long dummy);
73 #endif
74 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
75 #endif
76 
77 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
78 #define CONFIG_SYS_MEMTEST_END		0x00400000
79 
80 /*
81  * With the exception of PCI Memory and Rapid IO, most devices will simply
82  * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
83  * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
84  */
85 #ifdef CONFIG_PHYS_64BIT
86 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
87 #else
88 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
89 #endif
90 
91 /*
92  * Base addresses -- Note these are effective addresses where the
93  * actual resources get mapped (not physical addresses)
94  */
95 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
96 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
97 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
98 
99 /* Physical addresses */
100 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
101 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
102 #define CONFIG_SYS_CCSRBAR_PHYS \
103 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
104 			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
105 
106 #define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
107 
108 /*
109  * DDR Setup
110  */
111 #define CONFIG_FSL_DDR2
112 #undef CONFIG_FSL_DDR_INTERACTIVE
113 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
114 #define CONFIG_DDR_SPD
115 
116 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
117 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
118 
119 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
120 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
121 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
122 #define CONFIG_VERY_BIG_RAM
123 
124 #define CONFIG_NUM_DDR_CONTROLLERS	2
125 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
126 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
127 
128 /*
129  * I2C addresses of SPD EEPROMs
130  */
131 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
132 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
133 #define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
134 #define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
135 
136 
137 /*
138  * These are used when DDR doesn't use SPD.
139  */
140 #define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
141 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
142 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
143 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
144 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
145 #define CONFIG_SYS_DDR_TIMING_1	0x39357322
146 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
147 #define CONFIG_SYS_DDR_MODE_1		0x00480432
148 #define CONFIG_SYS_DDR_MODE_2		0x00000000
149 #define CONFIG_SYS_DDR_INTERVAL	0x06090100
150 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
151 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
152 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
153 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
154 #define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
155 #define CONFIG_SYS_DDR_CONTROL2	0x04400000
156 
157 #define CONFIG_ID_EEPROM
158 #define CONFIG_SYS_I2C_EEPROM_NXID
159 #define CONFIG_ID_EEPROM
160 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
161 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
162 
163 #define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
164 #define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
165 #define CONFIG_SYS_FLASH_BASE_PHYS \
166 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
167 			    CONFIG_SYS_PHYS_ADDR_HIGH)
168 
169 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
170 
171 #define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
172 				 | 0x00001001)	/* port size 16bit */
173 #define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
174 
175 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
176 				 | 0x00001001)	/* port size 16bit */
177 #define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
178 
179 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
180 				 | 0x00000801) /* port size 8bit */
181 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
182 
183 /*
184  * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
185  * The PIXIS and CF by themselves aren't large enough to take up the 128k
186  * required for the smallest BAT mapping, so there's a 64k hole.
187  */
188 #define CONFIG_SYS_LBC_BASE		0xffde0000
189 #define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
190 
191 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
192 #define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
193 #define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
194 #define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
195 						    CONFIG_SYS_PHYS_ADDR_HIGH)
196 #define PIXIS_SIZE		0x00008000	/* 32k */
197 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
198 #define PIXIS_VER		0x1	/* Board version at offset 1 */
199 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
200 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
201 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
202 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
203 #define PIXIS_VCTL		0x10	/* VELA Control Register */
204 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
205 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
206 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
207 #define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
208 #define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
209 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
210 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
211 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
212 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
213 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
214 
215 /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
216 #define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
217 #define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
218 
219 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
220 #define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
221 
222 #undef	CONFIG_SYS_FLASH_CHECKSUM
223 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
224 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
225 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
226 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
227 
228 #define CONFIG_FLASH_CFI_DRIVER
229 #define CONFIG_SYS_FLASH_CFI
230 #define CONFIG_SYS_FLASH_EMPTY_INFO
231 
232 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
233 #define CONFIG_SYS_RAMBOOT
234 #else
235 #undef	CONFIG_SYS_RAMBOOT
236 #endif
237 
238 #if defined(CONFIG_SYS_RAMBOOT)
239 #undef CONFIG_SPD_EEPROM
240 #define CONFIG_SYS_SDRAM_SIZE	256
241 #endif
242 
243 #undef CONFIG_CLOCKS_IN_MHZ
244 
245 #define CONFIG_SYS_INIT_RAM_LOCK	1
246 #ifndef CONFIG_SYS_INIT_RAM_LOCK
247 #define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
248 #else
249 #define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
250 #endif
251 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
252 
253 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
254 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
255 
256 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
257 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
258 
259 /* Serial Port */
260 #define CONFIG_CONS_INDEX     1
261 #define CONFIG_SYS_NS16550
262 #define CONFIG_SYS_NS16550_SERIAL
263 #define CONFIG_SYS_NS16550_REG_SIZE	1
264 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
265 
266 #define CONFIG_SYS_BAUDRATE_TABLE  \
267 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
268 
269 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
270 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
271 
272 /* Use the HUSH parser */
273 #define CONFIG_SYS_HUSH_PARSER
274 
275 /*
276  * Pass open firmware flat tree to kernel
277  */
278 #define CONFIG_OF_LIBFDT		1
279 #define CONFIG_OF_BOARD_SETUP		1
280 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
281 
282 /*
283  * I2C
284  */
285 #define CONFIG_SYS_I2C
286 #define CONFIG_SYS_I2C_FSL
287 #define CONFIG_SYS_FSL_I2C_SPEED	400000
288 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
289 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
290 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
291 
292 /*
293  * RapidIO MMU
294  */
295 #define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
296 #ifdef CONFIG_PHYS_64BIT
297 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
298 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
299 #else
300 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
301 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
302 #endif
303 #define CONFIG_SYS_SRIO1_MEM_PHYS \
304 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
305 			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
306 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
307 
308 /*
309  * General PCI
310  * Addresses are mapped 1-1.
311  */
312 
313 #define CONFIG_SYS_PCIE1_NAME		"ULI"
314 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
315 #ifdef CONFIG_PHYS_64BIT
316 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
317 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
318 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
319 #else
320 #define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
321 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
322 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
323 #endif
324 #define CONFIG_SYS_PCIE1_MEM_PHYS \
325 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
326 			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
327 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
328 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
329 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
330 #define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
331 #define CONFIG_SYS_PCIE1_IO_PHYS \
332 	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
333 			    CONFIG_SYS_PHYS_ADDR_HIGH)
334 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
335 
336 #ifdef CONFIG_PHYS_64BIT
337 /*
338  * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
339  * This will increase the amount of PCI address space available for
340  * for mapping RAM.
341  */
342 #define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
343 #else
344 #define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
345 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
346 #endif
347 #define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
348 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
349 #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
350 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
351 #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
352 #define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
353 					 + CONFIG_SYS_PCIE1_MEM_SIZE)
354 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
355 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
356 #define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
357 					 + CONFIG_SYS_PCIE1_IO_SIZE)
358 #define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
359 					 + CONFIG_SYS_PCIE1_IO_SIZE)
360 #define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
361 					 + CONFIG_SYS_PCIE1_IO_SIZE)
362 #define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
363 
364 #if defined(CONFIG_PCI)
365 
366 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
367 
368 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
369 
370 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
371 
372 #define CONFIG_RTL8139
373 
374 #undef CONFIG_EEPRO100
375 #undef CONFIG_TULIP
376 
377 /************************************************************
378  * USB support
379  ************************************************************/
380 #define CONFIG_PCI_OHCI			1
381 #define CONFIG_USB_OHCI_NEW		1
382 #define CONFIG_USB_KEYBOARD		1
383 #define CONFIG_SYS_STDIO_DEREGISTER
384 #define CONFIG_SYS_USB_EVENT_POLL		1
385 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
386 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
387 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
388 
389 /*PCIE video card used*/
390 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
391 
392 /*PCI video card used*/
393 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
394 
395 /* video */
396 #define CONFIG_VIDEO
397 
398 #if defined(CONFIG_VIDEO)
399 #define CONFIG_BIOSEMU
400 #define CONFIG_CFB_CONSOLE
401 #define CONFIG_VIDEO_SW_CURSOR
402 #define CONFIG_VGA_AS_SINGLE_DEVICE
403 #define CONFIG_ATI_RADEON_FB
404 #define CONFIG_VIDEO_LOGO
405 /*#define CONFIG_CONSOLE_CURSOR*/
406 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
407 #endif
408 
409 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
410 
411 #define CONFIG_DOS_PARTITION
412 #define CONFIG_SCSI_AHCI
413 
414 #ifdef CONFIG_SCSI_AHCI
415 #define CONFIG_LIBATA
416 #define CONFIG_SATA_ULI5288
417 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
418 #define CONFIG_SYS_SCSI_MAX_LUN	1
419 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
420 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
421 #endif
422 
423 #endif	/* CONFIG_PCI */
424 
425 #if defined(CONFIG_TSEC_ENET)
426 
427 #define CONFIG_MII		1	/* MII PHY management */
428 
429 #define CONFIG_TSEC1		1
430 #define CONFIG_TSEC1_NAME	"eTSEC1"
431 #define CONFIG_TSEC2		1
432 #define CONFIG_TSEC2_NAME	"eTSEC2"
433 #define CONFIG_TSEC3		1
434 #define CONFIG_TSEC3_NAME	"eTSEC3"
435 #define CONFIG_TSEC4		1
436 #define CONFIG_TSEC4_NAME	"eTSEC4"
437 
438 #define TSEC1_PHY_ADDR		0
439 #define TSEC2_PHY_ADDR		1
440 #define TSEC3_PHY_ADDR		2
441 #define TSEC4_PHY_ADDR		3
442 #define TSEC1_PHYIDX		0
443 #define TSEC2_PHYIDX		0
444 #define TSEC3_PHYIDX		0
445 #define TSEC4_PHYIDX		0
446 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
447 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
448 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
449 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
450 
451 #define CONFIG_ETHPRIME		"eTSEC1"
452 
453 #endif	/* CONFIG_TSEC_ENET */
454 
455 
456 #ifdef CONFIG_PHYS_64BIT
457 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
458 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
459 
460 /* Put physical address into the BAT format */
461 #define BAT_PHYS_ADDR(low, high) \
462 	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
463 /* Convert high/low pairs to actual 64-bit value */
464 #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
465 #else
466 /* 32-bit systems just ignore the "high" bits */
467 #define BAT_PHYS_ADDR(low, high)        (low)
468 #define PAIRED_PHYS_TO_PHYS(low, high)  (low)
469 #endif
470 
471 /*
472  * BAT0		DDR
473  */
474 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
475 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
476 
477 /*
478  * BAT1		LBC (PIXIS/CF)
479  */
480 #define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
481 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
482 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
483 				 BATL_GUARDEDSTORAGE)
484 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
485 				 | BATU_VS | BATU_VP)
486 #define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
487 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
488 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
489 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
490 
491 /* if CONFIG_PCI:
492  * BAT2		PCIE1 and PCIE1 MEM
493  * if CONFIG_RIO
494  * BAT2		Rapidio Memory
495  */
496 #ifdef CONFIG_PCI
497 #define CONFIG_PCI_INDIRECT_BRIDGE
498 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
499 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
500 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
501 				 | BATL_GUARDEDSTORAGE)
502 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
503 				 | BATU_VS | BATU_VP)
504 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
505 					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
506 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
507 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
508 #else /* CONFIG_RIO */
509 #define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
510 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
511 				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
512 				 BATL_GUARDEDSTORAGE)
513 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
514 				 | BATU_VS | BATU_VP)
515 #define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
516 					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
517 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
518 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
519 #endif
520 
521 /*
522  * BAT3		CCSR Space
523  */
524 #define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
525 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
526 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
527 				 | BATL_GUARDEDSTORAGE)
528 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
529 				 | BATU_VP)
530 #define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
531 					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
532 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
533 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
534 
535 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
536 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
537 				       | BATL_PP_RW | BATL_CACHEINHIBIT \
538 				       | BATL_GUARDEDSTORAGE)
539 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
540 				       | BATU_BL_1M | BATU_VS | BATU_VP)
541 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
542 				       | BATL_PP_RW | BATL_CACHEINHIBIT)
543 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
544 #endif
545 
546 /*
547  * BAT4		PCIE1_IO and PCIE2_IO
548  */
549 #define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
550 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
551 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
552 				 | BATL_GUARDEDSTORAGE)
553 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
554 				 | BATU_VS | BATU_VP)
555 #define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
556 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
557 				 | BATL_PP_RW | BATL_CACHEINHIBIT)
558 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
559 
560 /*
561  * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
562  */
563 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
564 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
565 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
566 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
567 
568 /*
569  * BAT6		FLASH
570  */
571 #define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
572 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
573 				 | BATL_PP_RW | BATL_CACHEINHIBIT \
574 				 | BATL_GUARDEDSTORAGE)
575 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
576 				 | BATU_VP)
577 #define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
578 					       CONFIG_SYS_PHYS_ADDR_HIGH) \
579 				 | BATL_PP_RW | BATL_MEMCOHERENCE)
580 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
581 
582 /* Map the last 1M of flash where we're running from reset */
583 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
584 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
585 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
586 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
587 				 | BATL_MEMCOHERENCE)
588 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
589 
590 /*
591  * BAT7		FREE - used later for tmp mappings
592  */
593 #define CONFIG_SYS_DBAT7L 0x00000000
594 #define CONFIG_SYS_DBAT7U 0x00000000
595 #define CONFIG_SYS_IBAT7L 0x00000000
596 #define CONFIG_SYS_IBAT7U 0x00000000
597 
598 /*
599  * Environment
600  */
601 #ifndef CONFIG_SYS_RAMBOOT
602     #define CONFIG_ENV_IS_IN_FLASH	1
603     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
604     #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
605 #else
606     #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
607     #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
608 #endif
609 #define CONFIG_ENV_SIZE		0x2000
610 
611 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
612 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
613 
614 
615 /*
616  * BOOTP options
617  */
618 #define CONFIG_BOOTP_BOOTFILESIZE
619 #define CONFIG_BOOTP_BOOTPATH
620 #define CONFIG_BOOTP_GATEWAY
621 #define CONFIG_BOOTP_HOSTNAME
622 
623 
624 /*
625  * Command line configuration.
626  */
627 #include <config_cmd_default.h>
628 
629 #define CONFIG_CMD_PING
630 #define CONFIG_CMD_I2C
631 #define CONFIG_CMD_REGINFO
632 
633 #if defined(CONFIG_SYS_RAMBOOT)
634     #undef CONFIG_CMD_SAVEENV
635 #endif
636 
637 #if defined(CONFIG_PCI)
638     #define CONFIG_CMD_PCI
639     #define CONFIG_CMD_SCSI
640     #define CONFIG_CMD_EXT2
641     #define CONFIG_CMD_USB
642 #endif
643 
644 
645 #undef CONFIG_WATCHDOG			/* watchdog disabled */
646 
647 /*
648  * Miscellaneous configurable options
649  */
650 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
651 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
652 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
653 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
654 
655 #if defined(CONFIG_CMD_KGDB)
656     #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
657 #else
658     #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
659 #endif
660 
661 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
662 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
663 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
664 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
665 
666 /*
667  * For booting Linux, the board info and command line data
668  * have to be in the first 8 MB of memory, since this is
669  * the maximum mapped by the Linux kernel during initialization.
670  */
671 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
672 
673 #if defined(CONFIG_CMD_KGDB)
674     #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
675     #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
676 #endif
677 
678 /*
679  * Environment Configuration
680  */
681 
682 /* The mac addresses for all ethernet interface */
683 #if defined(CONFIG_TSEC_ENET)
684 #define CONFIG_ETHADDR	 00:E0:0C:00:00:01
685 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
686 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
687 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
688 #endif
689 
690 #define CONFIG_HAS_ETH0		1
691 #define CONFIG_HAS_ETH1		1
692 #define CONFIG_HAS_ETH2		1
693 #define CONFIG_HAS_ETH3		1
694 
695 #define CONFIG_IPADDR		192.168.1.100
696 
697 #define CONFIG_HOSTNAME		unknown
698 #define CONFIG_ROOTPATH		"/opt/nfsroot"
699 #define CONFIG_BOOTFILE		"uImage"
700 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
701 
702 #define CONFIG_SERVERIP		192.168.1.1
703 #define CONFIG_GATEWAYIP	192.168.1.1
704 #define CONFIG_NETMASK		255.255.255.0
705 
706 /* default location for tftp and bootm */
707 #define CONFIG_LOADADDR		1000000
708 
709 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
710 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
711 
712 #define CONFIG_BAUDRATE	115200
713 
714 #define	CONFIG_EXTRA_ENV_SETTINGS					\
715 	"netdev=eth0\0"							\
716 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
717 	"tftpflash=tftpboot $loadaddr $uboot; "				\
718 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
719 			" +$filesize; "	\
720 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
721 			" +$filesize; "	\
722 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
723 			" $filesize; "	\
724 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
725 			" +$filesize; "	\
726 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
727 			" $filesize\0"	\
728 	"consoledev=ttyS0\0"						\
729 	"ramdiskaddr=2000000\0"						\
730 	"ramdiskfile=your.ramdisk.u-boot\0"				\
731 	"fdtaddr=c00000\0"						\
732 	"fdtfile=mpc8641_hpcn.dtb\0"					\
733 	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
734 	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
735 	"maxcpus=2"
736 
737 
738 #define CONFIG_NFSBOOTCOMMAND						\
739 	"setenv bootargs root=/dev/nfs rw "				\
740 	      "nfsroot=$serverip:$rootpath "				\
741 	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
742 	      "console=$consoledev,$baudrate $othbootargs;"		\
743 	"tftp $loadaddr $bootfile;"					\
744 	"tftp $fdtaddr $fdtfile;"					\
745 	"bootm $loadaddr - $fdtaddr"
746 
747 #define CONFIG_RAMBOOTCOMMAND						\
748 	"setenv bootargs root=/dev/ram rw "				\
749 	      "console=$consoledev,$baudrate $othbootargs;"		\
750 	"tftp $ramdiskaddr $ramdiskfile;"				\
751 	"tftp $loadaddr $bootfile;"					\
752 	"tftp $fdtaddr $fdtfile;"					\
753 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
754 
755 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
756 
757 #endif	/* __CONFIG_H */
758