1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_MPC86xx 1 /* MPC86xx */ 18 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 19 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 20 #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 23 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 24 25 /* video */ 26 #undef CONFIG_VIDEO 27 28 #if defined(CONFIG_VIDEO) 29 #define CONFIG_CFB_CONSOLE 30 #define CONFIG_VGA_AS_SINGLE_DEVICE 31 #endif 32 33 #ifdef RUN_DIAG 34 #define CONFIG_SYS_DIAG_ADDR 0xff800000 35 #endif 36 37 /* 38 * virtual address to be used for temporary mappings. There 39 * should be 128k free at this VA. 40 */ 41 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 42 43 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 44 #define CONFIG_PCI1 1 /* PCI controler 1 */ 45 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 46 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 48 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 50 51 #define CONFIG_ENV_OVERWRITE 52 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 53 54 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 55 #define CONFIG_ALTIVEC 1 56 57 /* 58 * L2CR setup -- make sure this is right for your board! 59 */ 60 #define CONFIG_SYS_L2 61 #define L2_INIT 0 62 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 63 64 #ifndef CONFIG_SYS_CLK_FREQ 65 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 66 #endif 67 68 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 69 #define CONFIG_MISC_INIT_R 1 70 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 /* 75 * Base addresses -- Note these are effective addresses where the 76 * actual resources get mapped (not physical addresses) 77 */ 78 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 79 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 80 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 81 82 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 83 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 84 85 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 86 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 87 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 88 89 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) 90 91 /* DDR Setup */ 92 #define CONFIG_FSL_DDR2 93 #undef CONFIG_FSL_DDR_INTERACTIVE 94 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 95 #define CONFIG_DDR_SPD 96 97 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 98 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 99 100 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 102 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 103 #define CONFIG_VERY_BIG_RAM 104 105 #define MPC86xx_DDR_SDRAM_CLK_CNTL 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 112 113 /* These are used when DDR doesn't use SPD. */ 114 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 115 116 #if 0 /* TODO */ 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 122 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 123 #define CONFIG_SYS_DDR_MODE_1 0x00480432 124 #define CONFIG_SYS_DDR_MODE_2 0x00000000 125 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x000f0000 136 137 #endif 138 139 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_ID_EEPROM 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 146 147 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 148 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 149 150 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 151 152 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 153 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 154 155 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 156 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 157 #if 0 /* TODO */ 158 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 159 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 160 #endif 161 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 162 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 163 164 165 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 166 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 167 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 168 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 169 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 170 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 171 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 172 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 173 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 174 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 175 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 176 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 177 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 178 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 179 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 180 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 181 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 182 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ 183 184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 186 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 191 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 197 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 198 #define CONFIG_SYS_RAMBOOT 199 #else 200 #undef CONFIG_SYS_RAMBOOT 201 #endif 202 203 #if defined(CONFIG_SYS_RAMBOOT) 204 #undef CONFIG_SPD_EEPROM 205 #define CONFIG_SYS_SDRAM_SIZE 256 206 #endif 207 208 #undef CONFIG_CLOCKS_IN_MHZ 209 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #ifndef CONFIG_SYS_INIT_RAM_LOCK 212 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 213 #else 214 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 215 #endif 216 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 217 218 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 219 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 220 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 221 222 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 223 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 224 225 /* Serial Port */ 226 #define CONFIG_CONS_INDEX 1 227 #undef CONFIG_SERIAL_SOFTWARE_FIFO 228 #define CONFIG_SYS_NS16550 229 #define CONFIG_SYS_NS16550_SERIAL 230 #define CONFIG_SYS_NS16550_REG_SIZE 1 231 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 232 233 #define CONFIG_SYS_BAUDRATE_TABLE \ 234 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 235 236 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 237 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 238 239 /* Use the HUSH parser */ 240 #define CONFIG_SYS_HUSH_PARSER 241 #ifdef CONFIG_SYS_HUSH_PARSER 242 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 243 #endif 244 245 /* 246 * Pass open firmware flat tree to kernel 247 */ 248 #define CONFIG_OF_LIBFDT 1 249 #define CONFIG_OF_BOARD_SETUP 1 250 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 251 252 253 /* maximum size of the flat tree (8K) */ 254 #define OF_FLAT_TREE_MAX_SIZE 8192 255 256 #define CONFIG_SYS_64BIT_VSPRINTF 1 257 #define CONFIG_SYS_64BIT_STRTOUL 1 258 259 /* 260 * I2C 261 */ 262 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 263 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 264 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 265 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 266 #define CONFIG_SYS_I2C_SLAVE 0x7F 267 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 268 #define CONFIG_SYS_I2C_OFFSET 0x3000 269 270 /* 271 * General PCI 272 * Addresses are mapped 1-1. 273 */ 274 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 275 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 276 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 277 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 278 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 279 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 280 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 281 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 282 283 /* For RTL8139 */ 284 #define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) 285 #define _IO_BASE 0x00000000 286 287 /* controller 1, Base address 0xa000 */ 288 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 289 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 290 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 291 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 292 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 293 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 294 295 /* controller 2, Base Address 0x9000 */ 296 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 297 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 298 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 299 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 300 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 301 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 302 303 304 #if defined(CONFIG_PCI) 305 306 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 307 308 #define CONFIG_NET_MULTI 309 #define CONFIG_CMD_NET 310 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 311 #define CONFIG_CMD_REGINFO 312 313 #define CONFIG_ULI526X 314 #ifdef CONFIG_ULI526X 315 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 316 #endif 317 318 /************************************************************ 319 * USB support 320 ************************************************************/ 321 #define CONFIG_PCI_OHCI 1 322 #define CONFIG_USB_OHCI_NEW 1 323 #define CONFIG_USB_KEYBOARD 1 324 #define CONFIG_SYS_DEVICE_DEREGISTER 325 #define CONFIG_SYS_USB_EVENT_POLL 1 326 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 327 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 328 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 329 330 #if !defined(CONFIG_PCI_PNP) 331 #define PCI_ENET0_IOADDR 0xe0000000 332 #define PCI_ENET0_MEMADDR 0xe0000000 333 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 334 #endif 335 336 #define CONFIG_DOS_PARTITION 337 #define CONFIG_SCSI_AHCI 338 339 #ifdef CONFIG_SCSI_AHCI 340 #define CONFIG_SATA_ULI5288 341 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 342 #define CONFIG_SYS_SCSI_MAX_LUN 1 343 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 344 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 345 #endif 346 347 #endif /* CONFIG_PCI */ 348 349 /* 350 * BAT0 2G Cacheable, non-guarded 351 * 0x0000_0000 2G DDR 352 */ 353 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 354 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 355 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 356 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 357 358 /* 359 * BAT1 1G Cache-inhibited, guarded 360 * 0x8000_0000 256M PCI-1 Memory 361 * 0xa000_0000 256M PCI-Express 1 Memory 362 * 0x9000_0000 256M PCI-Express 2 Memory 363 */ 364 365 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 366 | BATL_GUARDEDSTORAGE) 367 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 368 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 369 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 370 371 /* 372 * BAT2 16M Cache-inhibited, guarded 373 * 0xe100_0000 1M PCI-1 I/O 374 */ 375 376 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 377 | BATL_GUARDEDSTORAGE) 378 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 379 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 380 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 381 382 /* 383 * BAT3 4M Cache-inhibited, guarded 384 * 0xe000_0000 4M CCSR 385 */ 386 387 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 388 | BATL_GUARDEDSTORAGE) 389 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 390 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 391 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 392 393 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 394 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 395 | BATL_PP_RW | BATL_CACHEINHIBIT \ 396 | BATL_GUARDEDSTORAGE) 397 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 398 | BATU_BL_1M | BATU_VS | BATU_VP) 399 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 400 | BATL_PP_RW | BATL_CACHEINHIBIT) 401 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 402 #endif 403 404 /* 405 * BAT4 32M Cache-inhibited, guarded 406 * 0xe200_0000 1M PCI-Express 2 I/O 407 * 0xe300_0000 1M PCI-Express 1 I/O 408 */ 409 410 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 411 | BATL_GUARDEDSTORAGE) 412 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 413 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 414 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 415 416 417 /* 418 * BAT5 128K Cacheable, non-guarded 419 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 420 */ 421 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 422 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 423 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 424 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 425 426 /* 427 * BAT6 256M Cache-inhibited, guarded 428 * 0xf000_0000 256M FLASH 429 */ 430 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 431 | BATL_GUARDEDSTORAGE) 432 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 433 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 434 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 435 436 /* Map the last 1M of flash where we're running from reset */ 437 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 438 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 439 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 440 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 441 | BATL_MEMCOHERENCE) 442 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 443 444 /* 445 * BAT7 4M Cache-inhibited, guarded 446 * 0xe800_0000 4M PIXIS 447 */ 448 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 449 | BATL_GUARDEDSTORAGE) 450 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 451 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 452 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 453 454 455 /* 456 * Environment 457 */ 458 #ifndef CONFIG_SYS_RAMBOOT 459 #define CONFIG_ENV_IS_IN_FLASH 1 460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 461 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 462 #define CONFIG_ENV_SIZE 0x2000 463 #else 464 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 465 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 466 #define CONFIG_ENV_SIZE 0x2000 467 #endif 468 469 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 470 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 471 472 473 /* 474 * BOOTP options 475 */ 476 #define CONFIG_BOOTP_BOOTFILESIZE 477 #define CONFIG_BOOTP_BOOTPATH 478 #define CONFIG_BOOTP_GATEWAY 479 #define CONFIG_BOOTP_HOSTNAME 480 481 482 /* 483 * Command line configuration. 484 */ 485 #include <config_cmd_default.h> 486 487 #define CONFIG_CMD_PING 488 #define CONFIG_CMD_I2C 489 #define CONFIG_CMD_MII 490 491 #if defined(CONFIG_SYS_RAMBOOT) 492 #undef CONFIG_CMD_SAVEENV 493 #endif 494 495 #if defined(CONFIG_PCI) 496 #define CONFIG_CMD_PCI 497 #define CONFIG_CMD_SCSI 498 #define CONFIG_CMD_EXT2 499 #define CONFIG_CMD_USB 500 #endif 501 502 503 #define CONFIG_WATCHDOG /* watchdog enabled */ 504 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 505 506 /*DIU Configuration*/ 507 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 508 509 /* 510 * Miscellaneous configurable options 511 */ 512 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 513 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 514 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 515 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 516 517 #if defined(CONFIG_CMD_KGDB) 518 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 519 #else 520 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 521 #endif 522 523 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 524 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 525 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 526 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 527 528 /* 529 * For booting Linux, the board info and command line data 530 * have to be in the first 8 MB of memory, since this is 531 * the maximum mapped by the Linux kernel during initialization. 532 */ 533 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 534 535 /* 536 * Internal Definitions 537 * 538 * Boot Flags 539 */ 540 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 541 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 542 543 #if defined(CONFIG_CMD_KGDB) 544 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 545 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 546 #endif 547 548 /* 549 * Environment Configuration 550 */ 551 #define CONFIG_IPADDR 192.168.1.100 552 553 #define CONFIG_HOSTNAME unknown 554 #define CONFIG_ROOTPATH /opt/nfsroot 555 #define CONFIG_BOOTFILE uImage 556 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 557 558 #define CONFIG_SERVERIP 192.168.1.1 559 #define CONFIG_GATEWAYIP 192.168.1.1 560 #define CONFIG_NETMASK 255.255.255.0 561 562 /* default location for tftp and bootm */ 563 #define CONFIG_LOADADDR 1000000 564 565 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 566 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 567 568 #define CONFIG_BAUDRATE 115200 569 570 #if defined(CONFIG_PCI1) 571 #define PCI_ENV \ 572 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 573 "echo e;md ${a}e00 9\0" \ 574 "pci1regs=setenv a e0008; run pcireg\0" \ 575 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 576 "pci d.w $b.0 56 1\0" \ 577 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 578 "pci w.w $b.0 56 ffff\0" \ 579 "pci1err=setenv a e0008; run pcierr\0" \ 580 "pci1errc=setenv a e0008; run pcierrc\0" 581 #else 582 #define PCI_ENV "" 583 #endif 584 585 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 586 #define PCIE_ENV \ 587 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 588 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 589 "pcie1regs=setenv a e000a; run pciereg\0" \ 590 "pcie2regs=setenv a e0009; run pciereg\0" \ 591 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 592 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 593 "pci d $b.0 130 1\0" \ 594 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 595 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 596 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 597 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 598 "pcie1err=setenv a e000a; run pcieerr\0" \ 599 "pcie2err=setenv a e0009; run pcieerr\0" \ 600 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 601 "pcie2errc=setenv a e0009; run pcieerrc\0" 602 #else 603 #define PCIE_ENV "" 604 #endif 605 606 #define DMA_ENV \ 607 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 608 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 609 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 610 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 611 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 612 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 613 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 614 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 615 616 #ifdef ENV_DEBUG 617 #define CONFIG_EXTRA_ENV_SETTINGS \ 618 "netdev=eth0\0" \ 619 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 620 "tftpflash=tftpboot $loadaddr $uboot; " \ 621 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 622 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 623 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 624 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 625 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 626 "consoledev=ttyS0\0" \ 627 "ramdiskaddr=2000000\0" \ 628 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 629 "fdtaddr=c00000\0" \ 630 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 631 "bdev=sda3\0" \ 632 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 633 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 634 "maxcpus=1" \ 635 "eoi=mw e00400b0 0\0" \ 636 "iack=md e00400a0 1\0" \ 637 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 638 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 639 "md ${a}f00 5\0" \ 640 "ddr1regs=setenv a e0002; run ddrreg\0" \ 641 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 642 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 643 "md ${a}e60 1; md ${a}ef0 1d\0" \ 644 "guregs=setenv a e00e0; run gureg\0" \ 645 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 646 "mcmregs=setenv a e0001; run mcmreg\0" \ 647 "diuregs=md e002c000 1d\0" \ 648 "dium=mw e002c01c\0" \ 649 "diuerr=md e002c014 1\0" \ 650 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 651 "monitor=0-DVI\0" \ 652 "pmregs=md e00e1000 2b\0" \ 653 "lawregs=md e0000c08 4b\0" \ 654 "lbcregs=md e0005000 36\0" \ 655 "dma0regs=md e0021100 12\0" \ 656 "dma1regs=md e0021180 12\0" \ 657 "dma2regs=md e0021200 12\0" \ 658 "dma3regs=md e0021280 12\0" \ 659 PCI_ENV \ 660 PCIE_ENV \ 661 DMA_ENV 662 #else 663 #define CONFIG_EXTRA_ENV_SETTINGS \ 664 "netdev=eth0\0" \ 665 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 666 "consoledev=ttyS0\0" \ 667 "ramdiskaddr=2000000\0" \ 668 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 669 "fdtaddr=c00000\0" \ 670 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 671 "bdev=sda3\0" \ 672 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 673 "monitor=0-DVI\0" 674 #endif 675 676 #define CONFIG_NFSBOOTCOMMAND \ 677 "setenv bootargs root=/dev/nfs rw " \ 678 "nfsroot=$serverip:$rootpath " \ 679 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 680 "console=$consoledev,$baudrate $othbootargs;" \ 681 "tftp $loadaddr $bootfile;" \ 682 "tftp $fdtaddr $fdtfile;" \ 683 "bootm $loadaddr - $fdtaddr" 684 685 #define CONFIG_RAMBOOTCOMMAND \ 686 "setenv bootargs root=/dev/ram rw " \ 687 "console=$consoledev,$baudrate $othbootargs;" \ 688 "tftp $ramdiskaddr $ramdiskfile;" \ 689 "tftp $loadaddr $bootfile;" \ 690 "tftp $fdtaddr $fdtfile;" \ 691 "bootm $loadaddr $ramdiskaddr $fdtaddr" 692 693 #define CONFIG_BOOTCOMMAND \ 694 "setenv bootargs root=/dev/$bdev rw " \ 695 "console=$consoledev,$baudrate $othbootargs;" \ 696 "tftp $loadaddr $bootfile;" \ 697 "tftp $fdtaddr $fdtfile;" \ 698 "bootm $loadaddr - $fdtaddr" 699 700 #endif /* __CONFIG_H */ 701