1 /*
2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8 
9 /*
10  * MPC8610HPCD board configuration file
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 /* High Level Configuration Options */
17 #define CONFIG_MPC86xx		1	/* MPC86xx */
18 #define CONFIG_MPC8610		1	/* MPC8610 specific */
19 #define CONFIG_MPC8610HPCD	1	/* MPC8610HPCD board specific */
20 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
21 
22 #define	CONFIG_SYS_TEXT_BASE	0xfff00000
23 
24 
25 /* video */
26 #define CONFIG_FSL_DIU_FB
27 
28 #ifdef CONFIG_FSL_DIU_FB
29 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x2c000)
30 #define CONFIG_VIDEO
31 #define CONFIG_CMD_BMP
32 #define CONFIG_CFB_CONSOLE
33 #define CONFIG_VIDEO_SW_CURSOR
34 #define CONFIG_VGA_AS_SINGLE_DEVICE
35 #define CONFIG_VIDEO_LOGO
36 #define CONFIG_VIDEO_BMP_LOGO
37 #endif
38 
39 #ifdef RUN_DIAG
40 #define CONFIG_SYS_DIAG_ADDR		0xff800000
41 #endif
42 
43 /*
44  * virtual address to be used for temporary mappings.  There
45  * should be 128k free at this VA.
46  */
47 #define CONFIG_SYS_SCRATCH_VA	0xc0000000
48 
49 #define CONFIG_PCI		1	/* Enable PCI/PCIE*/
50 #define CONFIG_PCI1		1	/* PCI controler 1 */
51 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
52 #define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
53 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
54 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
55 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
56 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
57 
58 #define CONFIG_ENV_OVERWRITE
59 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
60 
61 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
62 #define CONFIG_HIGH_BATS	1	/* High BATs supported & enabled */
63 #define CONFIG_ALTIVEC		1
64 
65 /*
66  * L2CR setup -- make sure this is right for your board!
67  */
68 #define CONFIG_SYS_L2
69 #define L2_INIT		0
70 #define L2_ENABLE	(L2CR_L2E |0x00100000 )
71 
72 #ifndef CONFIG_SYS_CLK_FREQ
73 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
74 #endif
75 
76 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
77 #define CONFIG_MISC_INIT_R		1
78 
79 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
80 #define CONFIG_SYS_MEMTEST_END		0x00400000
81 
82 /*
83  * Base addresses -- Note these are effective addresses where the
84  * actual resources get mapped (not physical addresses)
85  */
86 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
87 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
88 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
89 
90 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
91 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
92 #define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
93 
94 /* DDR Setup */
95 #define CONFIG_FSL_DDR2
96 #undef CONFIG_FSL_DDR_INTERACTIVE
97 #define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
98 #define CONFIG_DDR_SPD
99 
100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
101 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
102 
103 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
104 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
105 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
106 #define CONFIG_VERY_BIG_RAM
107 
108 #define CONFIG_NUM_DDR_CONTROLLERS	1
109 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
110 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
111 
112 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
113 
114 /* These are used when DDR doesn't use SPD.  */
115 #define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
116 
117 #if 0 /* TODO */
118 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
119 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
120 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
121 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
122 #define CONFIG_SYS_DDR_TIMING_1	0x3935d322
123 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
124 #define CONFIG_SYS_DDR_MODE_1		0x00480432
125 #define CONFIG_SYS_DDR_MODE_2		0x00000000
126 #define CONFIG_SYS_DDR_INTERVAL	0x06180100
127 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
128 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
129 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
130 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
131 #define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
132 #define CONFIG_SYS_DDR_CONTROL2	0x04400010
133 
134 #define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
135 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
136 #define CONFIG_SYS_DDR_SBE		0x000f0000
137 
138 #endif
139 
140 
141 #define CONFIG_ID_EEPROM
142 #define CONFIG_SYS_I2C_EEPROM_NXID
143 #define CONFIG_ID_EEPROM
144 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
145 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
146 
147 
148 #define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
149 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
150 
151 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
152 
153 #define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
154 #define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
155 
156 #define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
157 #define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
158 #if 0 /* TODO */
159 #define CONFIG_SYS_BR2_PRELIM		0xf0000000
160 #define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
161 #endif
162 #define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
163 #define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
164 
165 
166 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
167 #define PIXIS_BASE	0xe8000000	/* PIXIS registers */
168 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
169 #define PIXIS_VER		0x1	/* Board version at offset 1 */
170 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
171 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
172 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
173 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
174 #define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
175 #define PIXIS_VCTL		0x10	/* VELA Control Register */
176 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
177 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
178 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
179 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
180 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
181 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
182 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
183 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
184 
185 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
186 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
187 
188 #undef	CONFIG_SYS_FLASH_CHECKSUM
189 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
190 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
191 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
192 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
193 
194 #define CONFIG_FLASH_CFI_DRIVER
195 #define CONFIG_SYS_FLASH_CFI
196 #define CONFIG_SYS_FLASH_EMPTY_INFO
197 
198 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
199 #define CONFIG_SYS_RAMBOOT
200 #else
201 #undef	CONFIG_SYS_RAMBOOT
202 #endif
203 
204 #if defined(CONFIG_SYS_RAMBOOT)
205 #undef CONFIG_SPD_EEPROM
206 #define CONFIG_SYS_SDRAM_SIZE	256
207 #endif
208 
209 #undef CONFIG_CLOCKS_IN_MHZ
210 
211 #define CONFIG_SYS_INIT_RAM_LOCK	1
212 #ifndef CONFIG_SYS_INIT_RAM_LOCK
213 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
214 #else
215 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
216 #endif
217 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
218 
219 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
221 
222 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
223 #define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
224 
225 /* Serial Port */
226 #define CONFIG_CONS_INDEX	1
227 #define CONFIG_SYS_NS16550
228 #define CONFIG_SYS_NS16550_SERIAL
229 #define CONFIG_SYS_NS16550_REG_SIZE	1
230 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
231 
232 #define CONFIG_SYS_BAUDRATE_TABLE \
233 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
234 
235 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
236 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
237 
238 /* Use the HUSH parser */
239 #define CONFIG_SYS_HUSH_PARSER
240 
241 /*
242  * Pass open firmware flat tree to kernel
243  */
244 #define CONFIG_OF_LIBFDT		1
245 #define CONFIG_OF_BOARD_SETUP		1
246 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
247 
248 
249 /* maximum size of the flat tree (8K) */
250 #define OF_FLAT_TREE_MAX_SIZE	8192
251 
252 /*
253  * I2C
254  */
255 #define CONFIG_SYS_I2C
256 #define CONFIG_SYS_I2C_FSL
257 #define CONFIG_SYS_FSL_I2C_SPEED	400000
258 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
259 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
260 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
261 
262 /*
263  * General PCI
264  * Addresses are mapped 1-1.
265  */
266 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
267 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
268 #define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
269 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
270 #define CONFIG_SYS_PCI1_IO_BUS	0x0000000
271 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
272 #define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
273 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
274 
275 /* controller 1, Base address 0xa000 */
276 #define CONFIG_SYS_PCIE1_NAME		"ULI"
277 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
278 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
279 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
280 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
281 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
282 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
283 
284 /* controller 2, Base Address 0x9000 */
285 #define CONFIG_SYS_PCIE2_NAME		"Slot 1"
286 #define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
287 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
288 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
289 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
290 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
291 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
292 
293 
294 #if defined(CONFIG_PCI)
295 
296 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
297 
298 #define CONFIG_CMD_NET
299 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
300 #define CONFIG_CMD_REGINFO
301 
302 #define CONFIG_ULI526X
303 #ifdef CONFIG_ULI526X
304 #define CONFIG_ETHADDR   00:E0:0C:00:00:01
305 #endif
306 
307 /************************************************************
308  * USB support
309  ************************************************************/
310 #define CONFIG_PCI_OHCI		1
311 #define CONFIG_USB_OHCI_NEW		1
312 #define CONFIG_USB_KEYBOARD	1
313 #define CONFIG_SYS_STDIO_DEREGISTER
314 #define CONFIG_SYS_USB_EVENT_POLL	1
315 #define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
316 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
317 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
318 
319 #if !defined(CONFIG_PCI_PNP)
320 #define PCI_ENET0_IOADDR	0xe0000000
321 #define PCI_ENET0_MEMADDR	0xe0000000
322 #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
323 #endif
324 
325 #define CONFIG_DOS_PARTITION
326 #define CONFIG_SCSI_AHCI
327 
328 #ifdef CONFIG_SCSI_AHCI
329 #define CONFIG_LIBATA
330 #define CONFIG_SATA_ULI5288
331 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
332 #define CONFIG_SYS_SCSI_MAX_LUN	1
333 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
334 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
335 #endif
336 
337 #endif	/* CONFIG_PCI */
338 
339 /*
340  * BAT0		2G	Cacheable, non-guarded
341  * 0x0000_0000	2G	DDR
342  */
343 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
344 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
345 
346 /*
347  * BAT1		1G	Cache-inhibited, guarded
348  * 0x8000_0000	256M	PCI-1 Memory
349  * 0xa000_0000	256M	PCI-Express 1 Memory
350  * 0x9000_0000	256M	PCI-Express 2 Memory
351  */
352 
353 #define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
354 			| BATL_GUARDEDSTORAGE)
355 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
356 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
357 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
358 
359 /*
360  * BAT2		16M	Cache-inhibited, guarded
361  * 0xe100_0000	1M	PCI-1 I/O
362  */
363 
364 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
365 			| BATL_GUARDEDSTORAGE)
366 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
367 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
368 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
369 
370 /*
371  * BAT3		4M	Cache-inhibited, guarded
372  * 0xe000_0000	4M	CCSR
373  */
374 
375 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
376 			| BATL_GUARDEDSTORAGE)
377 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
378 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
379 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
380 
381 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
382 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
383 				       | BATL_PP_RW | BATL_CACHEINHIBIT \
384 				       | BATL_GUARDEDSTORAGE)
385 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
386 				       | BATU_BL_1M | BATU_VS | BATU_VP)
387 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
388 				       | BATL_PP_RW | BATL_CACHEINHIBIT)
389 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
390 #endif
391 
392 /*
393  * BAT4		32M	Cache-inhibited, guarded
394  * 0xe200_0000	1M	PCI-Express 2 I/O
395  * 0xe300_0000	1M	PCI-Express 1 I/O
396  */
397 
398 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
399 			| BATL_GUARDEDSTORAGE)
400 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
401 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
402 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
403 
404 
405 /*
406  * BAT5		128K	Cacheable, non-guarded
407  * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
408  */
409 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
410 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
411 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
412 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
413 
414 /*
415  * BAT6		256M	Cache-inhibited, guarded
416  * 0xf000_0000	256M	FLASH
417  */
418 #define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
419 			| BATL_GUARDEDSTORAGE)
420 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
421 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
422 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
423 
424 /* Map the last 1M of flash where we're running from reset */
425 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
426 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
427 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
428 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
429 				 | BATL_MEMCOHERENCE)
430 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
431 
432 /*
433  * BAT7		4M	Cache-inhibited, guarded
434  * 0xe800_0000	4M	PIXIS
435  */
436 #define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
437 			| BATL_GUARDEDSTORAGE)
438 #define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
439 #define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
440 #define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
441 
442 
443 /*
444  * Environment
445  */
446 #ifndef CONFIG_SYS_RAMBOOT
447 #define CONFIG_ENV_IS_IN_FLASH	1
448 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
449 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 126k (one sector) for env */
450 #define CONFIG_ENV_SIZE		0x2000
451 #else
452 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
453 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
454 #define CONFIG_ENV_SIZE		0x2000
455 #endif
456 
457 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
458 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
459 
460 
461 /*
462  * BOOTP options
463  */
464 #define CONFIG_BOOTP_BOOTFILESIZE
465 #define CONFIG_BOOTP_BOOTPATH
466 #define CONFIG_BOOTP_GATEWAY
467 #define CONFIG_BOOTP_HOSTNAME
468 
469 
470 /*
471  * Command line configuration.
472  */
473 #include <config_cmd_default.h>
474 
475 #define CONFIG_CMD_PING
476 #define CONFIG_CMD_I2C
477 #define CONFIG_CMD_MII
478 
479 #if defined(CONFIG_SYS_RAMBOOT)
480 #undef CONFIG_CMD_SAVEENV
481 #endif
482 
483 #if defined(CONFIG_PCI)
484 #define CONFIG_CMD_PCI
485 #define CONFIG_CMD_SCSI
486 #define CONFIG_CMD_EXT2
487 #define CONFIG_CMD_USB
488 #endif
489 
490 
491 #define CONFIG_WATCHDOG			/* watchdog enabled */
492 #define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
493 
494 /*
495  * Miscellaneous configurable options
496  */
497 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
498 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
499 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
500 
501 #if defined(CONFIG_CMD_KGDB)
502 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
503 #else
504 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
505 #endif
506 
507 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
508 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
509 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
510 
511 /*
512  * For booting Linux, the board info and command line data
513  * have to be in the first 8 MB of memory, since this is
514  * the maximum mapped by the Linux kernel during initialization.
515  */
516 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
517 
518 #if defined(CONFIG_CMD_KGDB)
519 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
520 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
521 #endif
522 
523 /*
524  * Environment Configuration
525  */
526 #define CONFIG_IPADDR		192.168.1.100
527 
528 #define CONFIG_HOSTNAME		unknown
529 #define CONFIG_ROOTPATH		"/opt/nfsroot"
530 #define CONFIG_BOOTFILE		"uImage"
531 #define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
532 
533 #define CONFIG_SERVERIP		192.168.1.1
534 #define CONFIG_GATEWAYIP	192.168.1.1
535 #define CONFIG_NETMASK		255.255.255.0
536 
537 /* default location for tftp and bootm */
538 #define CONFIG_LOADADDR		1000000
539 
540 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
541 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
542 
543 #define CONFIG_BAUDRATE	115200
544 
545 #if defined(CONFIG_PCI1)
546 #define PCI_ENV \
547  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
548 	"echo e;md ${a}e00 9\0" \
549  "pci1regs=setenv a e0008; run pcireg\0" \
550  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
551 	"pci d.w $b.0 56 1\0" \
552  "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
553 	"pci w.w $b.0 56 ffff\0"	\
554  "pci1err=setenv a e0008; run pcierr\0"	\
555  "pci1errc=setenv a e0008; run pcierrc\0"
556 #else
557 #define	PCI_ENV ""
558 #endif
559 
560 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
561 #define PCIE_ENV \
562  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
563 	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
564  "pcie1regs=setenv a e000a; run pciereg\0"	\
565  "pcie2regs=setenv a e0009; run pciereg\0"	\
566  "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
567 	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
568 	"pci d $b.0 130 1\0" \
569  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
570 	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
571 	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
572  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
573  "pcie1err=setenv a e000a; run pcieerr\0"	\
574  "pcie2err=setenv a e0009; run pcieerr\0"	\
575  "pcie1errc=setenv a e000a; run pcieerrc\0"	\
576  "pcie2errc=setenv a e0009; run pcieerrc\0"
577 #else
578 #define	PCIE_ENV ""
579 #endif
580 
581 #define DMA_ENV \
582  "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
583 	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
584  "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
585 	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
586  "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
587 	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
588  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
589 	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
590 
591 #ifdef ENV_DEBUG
592 #define	CONFIG_EXTRA_ENV_SETTINGS				\
593 "netdev=eth0\0"							\
594 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
595 "tftpflash=tftpboot $loadaddr $uboot; "				\
596 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
597 		" +$filesize; "	\
598 	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
599 		" +$filesize; "	\
600 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
601 		" $filesize; "	\
602 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
603 		" +$filesize; "	\
604 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
605 		" $filesize\0"	\
606 "consoledev=ttyS0\0"						\
607 "ramdiskaddr=2000000\0"					\
608 "ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
609 "fdtaddr=c00000\0"						\
610 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
611 "bdev=sda3\0"					\
612 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
613 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
614 "maxcpus=1"	\
615 "eoi=mw e00400b0 0\0"						\
616 "iack=md e00400a0 1\0"						\
617 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
618 	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
619 	"md ${a}f00 5\0" \
620 "ddr1regs=setenv a e0002; run ddrreg\0" \
621 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
622 	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
623 	"md ${a}e60 1; md ${a}ef0 1d\0" \
624 "guregs=setenv a e00e0; run gureg\0" \
625 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
626 "mcmregs=setenv a e0001; run mcmreg\0" \
627 "diuregs=md e002c000 1d\0" \
628 "dium=mw e002c01c\0" \
629 "diuerr=md e002c014 1\0" \
630 "pmregs=md e00e1000 2b\0" \
631 "lawregs=md e0000c08 4b\0" \
632 "lbcregs=md e0005000 36\0" \
633 "dma0regs=md e0021100 12\0" \
634 "dma1regs=md e0021180 12\0" \
635 "dma2regs=md e0021200 12\0" \
636 "dma3regs=md e0021280 12\0" \
637  PCI_ENV \
638  PCIE_ENV \
639  DMA_ENV
640 #else
641 #define CONFIG_EXTRA_ENV_SETTINGS				\
642 	"netdev=eth0\0"						\
643 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
644 	"consoledev=ttyS0\0"					\
645 	"ramdiskaddr=2000000\0"					\
646 	"ramdiskfile=8610hpcd/ramdisk.uboot\0"			\
647 	"fdtaddr=c00000\0"					\
648 	"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"			\
649 	"bdev=sda3\0"
650 #endif
651 
652 #define CONFIG_NFSBOOTCOMMAND					\
653  "setenv bootargs root=/dev/nfs rw "				\
654 	"nfsroot=$serverip:$rootpath "				\
655 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
656 	"console=$consoledev,$baudrate $othbootargs;"		\
657  "tftp $loadaddr $bootfile;"					\
658  "tftp $fdtaddr $fdtfile;"					\
659  "bootm $loadaddr - $fdtaddr"
660 
661 #define CONFIG_RAMBOOTCOMMAND \
662  "setenv bootargs root=/dev/ram rw "				\
663 	"console=$consoledev,$baudrate $othbootargs;"		\
664  "tftp $ramdiskaddr $ramdiskfile;"				\
665  "tftp $loadaddr $bootfile;"					\
666  "tftp $fdtaddr $fdtfile;"					\
667  "bootm $loadaddr $ramdiskaddr $fdtaddr"
668 
669 #define CONFIG_BOOTCOMMAND		\
670  "setenv bootargs root=/dev/$bdev rw "	\
671 	"console=$consoledev,$baudrate $othbootargs;"	\
672  "tftp $loadaddr $bootfile;"		\
673  "tftp $fdtaddr $fdtfile;"		\
674  "bootm $loadaddr - $fdtaddr"
675 
676 #endif	/* __CONFIG_H */
677