1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 /* 8 * MPC8610HPCD board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 16 17 #define CONFIG_SYS_TEXT_BASE 0xfff00000 18 19 /* video */ 20 #define CONFIG_FSL_DIU_FB 21 22 #ifdef CONFIG_FSL_DIU_FB 23 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 24 #define CONFIG_CMD_BMP 25 #define CONFIG_VIDEO_LOGO 26 #define CONFIG_VIDEO_BMP_LOGO 27 #endif 28 29 #ifdef RUN_DIAG 30 #define CONFIG_SYS_DIAG_ADDR 0xff800000 31 #endif 32 33 /* 34 * virtual address to be used for temporary mappings. There 35 * should be 128k free at this VA. 36 */ 37 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 38 39 #define CONFIG_PCI1 1 /* PCI controller 1 */ 40 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 41 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 44 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 45 46 #define CONFIG_ENV_OVERWRITE 47 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 48 49 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 50 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 51 #define CONFIG_ALTIVEC 1 52 53 /* 54 * L2CR setup -- make sure this is right for your board! 55 */ 56 #define CONFIG_SYS_L2 57 #define L2_INIT 0 58 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 59 60 #ifndef CONFIG_SYS_CLK_FREQ 61 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 62 #endif 63 64 #define CONFIG_MISC_INIT_R 1 65 66 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 67 #define CONFIG_SYS_MEMTEST_END 0x00400000 68 69 /* 70 * Base addresses -- Note these are effective addresses where the 71 * actual resources get mapped (not physical addresses) 72 */ 73 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 74 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 75 76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 77 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 78 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 79 80 /* DDR Setup */ 81 #undef CONFIG_FSL_DDR_INTERACTIVE 82 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 83 #define CONFIG_DDR_SPD 84 85 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 86 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 87 88 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 90 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 91 #define CONFIG_VERY_BIG_RAM 92 93 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 94 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 95 96 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 97 98 /* These are used when DDR doesn't use SPD. */ 99 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 100 101 #if 0 /* TODO */ 102 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 103 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 104 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 105 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 106 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 107 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 108 #define CONFIG_SYS_DDR_MODE_1 0x00480432 109 #define CONFIG_SYS_DDR_MODE_2 0x00000000 110 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 111 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 112 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 113 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 114 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 115 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 116 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 117 118 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 119 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 120 #define CONFIG_SYS_DDR_SBE 0x000f0000 121 122 #endif 123 124 #define CONFIG_ID_EEPROM 125 #define CONFIG_SYS_I2C_EEPROM_NXID 126 #define CONFIG_ID_EEPROM 127 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 128 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 129 130 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 131 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 132 133 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 134 135 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 136 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 137 138 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 139 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 140 #if 0 /* TODO */ 141 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 142 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 143 #endif 144 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 145 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 146 147 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 148 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 149 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 150 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 151 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 152 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 153 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 154 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 155 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 156 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 157 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 158 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 159 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 160 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 161 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 162 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 163 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 164 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 165 166 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 167 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 168 169 #undef CONFIG_SYS_FLASH_CHECKSUM 170 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 171 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 172 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 173 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 174 175 #define CONFIG_FLASH_CFI_DRIVER 176 #define CONFIG_SYS_FLASH_CFI 177 #define CONFIG_SYS_FLASH_EMPTY_INFO 178 179 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 180 #define CONFIG_SYS_RAMBOOT 181 #else 182 #undef CONFIG_SYS_RAMBOOT 183 #endif 184 185 #if defined(CONFIG_SYS_RAMBOOT) 186 #undef CONFIG_SPD_EEPROM 187 #define CONFIG_SYS_SDRAM_SIZE 256 188 #endif 189 190 #undef CONFIG_CLOCKS_IN_MHZ 191 192 #define CONFIG_SYS_INIT_RAM_LOCK 1 193 #ifndef CONFIG_SYS_INIT_RAM_LOCK 194 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 195 #else 196 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 197 #endif 198 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 199 200 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 201 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 202 203 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 204 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 205 206 /* Serial Port */ 207 #define CONFIG_CONS_INDEX 1 208 #define CONFIG_SYS_NS16550_SERIAL 209 #define CONFIG_SYS_NS16550_REG_SIZE 1 210 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 211 212 #define CONFIG_SYS_BAUDRATE_TABLE \ 213 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 214 215 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 216 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 217 218 /* maximum size of the flat tree (8K) */ 219 #define OF_FLAT_TREE_MAX_SIZE 8192 220 221 /* 222 * I2C 223 */ 224 #define CONFIG_SYS_I2C 225 #define CONFIG_SYS_I2C_FSL 226 #define CONFIG_SYS_FSL_I2C_SPEED 400000 227 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 228 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 229 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 230 231 /* 232 * General PCI 233 * Addresses are mapped 1-1. 234 */ 235 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 236 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 237 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 238 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 239 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 240 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 241 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 242 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 243 244 /* controller 1, Base address 0xa000 */ 245 #define CONFIG_SYS_PCIE1_NAME "ULI" 246 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 247 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 248 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 249 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 250 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 251 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 252 253 /* controller 2, Base Address 0x9000 */ 254 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 255 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 256 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 257 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 258 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 259 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 260 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 261 262 #if defined(CONFIG_PCI) 263 264 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 265 266 #define CONFIG_CMD_REGINFO 267 268 #define CONFIG_ULI526X 269 #ifdef CONFIG_ULI526X 270 #endif 271 272 /************************************************************ 273 * USB support 274 ************************************************************/ 275 #define CONFIG_PCI_OHCI 1 276 #define CONFIG_USB_OHCI_NEW 1 277 #define CONFIG_SYS_USB_EVENT_POLL 1 278 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 279 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 280 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 281 282 #if !defined(CONFIG_PCI_PNP) 283 #define PCI_ENET0_IOADDR 0xe0000000 284 #define PCI_ENET0_MEMADDR 0xe0000000 285 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 286 #endif 287 288 #define CONFIG_DOS_PARTITION 289 #define CONFIG_SCSI_AHCI 290 291 #ifdef CONFIG_SCSI_AHCI 292 #define CONFIG_LIBATA 293 #define CONFIG_SATA_ULI5288 294 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 295 #define CONFIG_SYS_SCSI_MAX_LUN 1 296 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 297 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 298 #endif 299 300 #endif /* CONFIG_PCI */ 301 302 /* 303 * BAT0 2G Cacheable, non-guarded 304 * 0x0000_0000 2G DDR 305 */ 306 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 307 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 308 309 /* 310 * BAT1 1G Cache-inhibited, guarded 311 * 0x8000_0000 256M PCI-1 Memory 312 * 0xa000_0000 256M PCI-Express 1 Memory 313 * 0x9000_0000 256M PCI-Express 2 Memory 314 */ 315 316 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 317 | BATL_GUARDEDSTORAGE) 318 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 319 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 320 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 321 322 /* 323 * BAT2 16M Cache-inhibited, guarded 324 * 0xe100_0000 1M PCI-1 I/O 325 */ 326 327 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 328 | BATL_GUARDEDSTORAGE) 329 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 330 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 331 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 332 333 /* 334 * BAT3 4M Cache-inhibited, guarded 335 * 0xe000_0000 4M CCSR 336 */ 337 338 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 339 | BATL_GUARDEDSTORAGE) 340 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 341 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 342 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 343 344 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 345 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 346 | BATL_PP_RW | BATL_CACHEINHIBIT \ 347 | BATL_GUARDEDSTORAGE) 348 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 349 | BATU_BL_1M | BATU_VS | BATU_VP) 350 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 351 | BATL_PP_RW | BATL_CACHEINHIBIT) 352 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 353 #endif 354 355 /* 356 * BAT4 32M Cache-inhibited, guarded 357 * 0xe200_0000 1M PCI-Express 2 I/O 358 * 0xe300_0000 1M PCI-Express 1 I/O 359 */ 360 361 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 362 | BATL_GUARDEDSTORAGE) 363 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 364 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 365 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 366 367 /* 368 * BAT5 128K Cacheable, non-guarded 369 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 370 */ 371 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 372 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 373 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 374 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 375 376 /* 377 * BAT6 256M Cache-inhibited, guarded 378 * 0xf000_0000 256M FLASH 379 */ 380 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 381 | BATL_GUARDEDSTORAGE) 382 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 383 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 384 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 385 386 /* Map the last 1M of flash where we're running from reset */ 387 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 388 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 389 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 390 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 391 | BATL_MEMCOHERENCE) 392 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 393 394 /* 395 * BAT7 4M Cache-inhibited, guarded 396 * 0xe800_0000 4M PIXIS 397 */ 398 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 399 | BATL_GUARDEDSTORAGE) 400 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 401 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 402 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 403 404 /* 405 * Environment 406 */ 407 #ifndef CONFIG_SYS_RAMBOOT 408 #define CONFIG_ENV_IS_IN_FLASH 1 409 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 410 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 411 #define CONFIG_ENV_SIZE 0x2000 412 #else 413 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 414 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 415 #define CONFIG_ENV_SIZE 0x2000 416 #endif 417 418 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 419 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 420 421 /* 422 * BOOTP options 423 */ 424 #define CONFIG_BOOTP_BOOTFILESIZE 425 #define CONFIG_BOOTP_BOOTPATH 426 #define CONFIG_BOOTP_GATEWAY 427 #define CONFIG_BOOTP_HOSTNAME 428 429 /* 430 * Command line configuration. 431 */ 432 433 #if defined(CONFIG_PCI) 434 #define CONFIG_CMD_PCI 435 #define CONFIG_SCSI 436 #endif 437 438 #define CONFIG_WATCHDOG /* watchdog enabled */ 439 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 440 441 /* 442 * Miscellaneous configurable options 443 */ 444 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 445 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 446 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 447 448 #if defined(CONFIG_CMD_KGDB) 449 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 450 #else 451 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 452 #endif 453 454 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 455 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 456 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 457 458 /* 459 * For booting Linux, the board info and command line data 460 * have to be in the first 8 MB of memory, since this is 461 * the maximum mapped by the Linux kernel during initialization. 462 */ 463 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 464 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 465 466 #if defined(CONFIG_CMD_KGDB) 467 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 468 #endif 469 470 /* 471 * Environment Configuration 472 */ 473 #define CONFIG_IPADDR 192.168.1.100 474 475 #define CONFIG_HOSTNAME unknown 476 #define CONFIG_ROOTPATH "/opt/nfsroot" 477 #define CONFIG_BOOTFILE "uImage" 478 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 479 480 #define CONFIG_SERVERIP 192.168.1.1 481 #define CONFIG_GATEWAYIP 192.168.1.1 482 #define CONFIG_NETMASK 255.255.255.0 483 484 /* default location for tftp and bootm */ 485 #define CONFIG_LOADADDR 0x10000000 486 487 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 488 489 #define CONFIG_BAUDRATE 115200 490 491 #if defined(CONFIG_PCI1) 492 #define PCI_ENV \ 493 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 494 "echo e;md ${a}e00 9\0" \ 495 "pci1regs=setenv a e0008; run pcireg\0" \ 496 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 497 "pci d.w $b.0 56 1\0" \ 498 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 499 "pci w.w $b.0 56 ffff\0" \ 500 "pci1err=setenv a e0008; run pcierr\0" \ 501 "pci1errc=setenv a e0008; run pcierrc\0" 502 #else 503 #define PCI_ENV "" 504 #endif 505 506 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 507 #define PCIE_ENV \ 508 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 509 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 510 "pcie1regs=setenv a e000a; run pciereg\0" \ 511 "pcie2regs=setenv a e0009; run pciereg\0" \ 512 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 513 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 514 "pci d $b.0 130 1\0" \ 515 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 516 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 517 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 518 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 519 "pcie1err=setenv a e000a; run pcieerr\0" \ 520 "pcie2err=setenv a e0009; run pcieerr\0" \ 521 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 522 "pcie2errc=setenv a e0009; run pcieerrc\0" 523 #else 524 #define PCIE_ENV "" 525 #endif 526 527 #define DMA_ENV \ 528 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 529 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 530 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 531 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 532 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 533 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 534 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 535 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 536 537 #ifdef ENV_DEBUG 538 #define CONFIG_EXTRA_ENV_SETTINGS \ 539 "netdev=eth0\0" \ 540 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 541 "tftpflash=tftpboot $loadaddr $uboot; " \ 542 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 543 " +$filesize; " \ 544 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 545 " +$filesize; " \ 546 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 547 " $filesize; " \ 548 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 549 " +$filesize; " \ 550 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 551 " $filesize\0" \ 552 "consoledev=ttyS0\0" \ 553 "ramdiskaddr=0x18000000\0" \ 554 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 555 "fdtaddr=0x17c00000\0" \ 556 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 557 "bdev=sda3\0" \ 558 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 559 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 560 "maxcpus=1" \ 561 "eoi=mw e00400b0 0\0" \ 562 "iack=md e00400a0 1\0" \ 563 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 564 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 565 "md ${a}f00 5\0" \ 566 "ddr1regs=setenv a e0002; run ddrreg\0" \ 567 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 568 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 569 "md ${a}e60 1; md ${a}ef0 1d\0" \ 570 "guregs=setenv a e00e0; run gureg\0" \ 571 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 572 "mcmregs=setenv a e0001; run mcmreg\0" \ 573 "diuregs=md e002c000 1d\0" \ 574 "dium=mw e002c01c\0" \ 575 "diuerr=md e002c014 1\0" \ 576 "pmregs=md e00e1000 2b\0" \ 577 "lawregs=md e0000c08 4b\0" \ 578 "lbcregs=md e0005000 36\0" \ 579 "dma0regs=md e0021100 12\0" \ 580 "dma1regs=md e0021180 12\0" \ 581 "dma2regs=md e0021200 12\0" \ 582 "dma3regs=md e0021280 12\0" \ 583 PCI_ENV \ 584 PCIE_ENV \ 585 DMA_ENV 586 #else 587 #define CONFIG_EXTRA_ENV_SETTINGS \ 588 "netdev=eth0\0" \ 589 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 590 "consoledev=ttyS0\0" \ 591 "ramdiskaddr=0x18000000\0" \ 592 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 593 "fdtaddr=0x17c00000\0" \ 594 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 595 "bdev=sda3\0" 596 #endif 597 598 #define CONFIG_NFSBOOTCOMMAND \ 599 "setenv bootargs root=/dev/nfs rw " \ 600 "nfsroot=$serverip:$rootpath " \ 601 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 602 "console=$consoledev,$baudrate $othbootargs;" \ 603 "tftp $loadaddr $bootfile;" \ 604 "tftp $fdtaddr $fdtfile;" \ 605 "bootm $loadaddr - $fdtaddr" 606 607 #define CONFIG_RAMBOOTCOMMAND \ 608 "setenv bootargs root=/dev/ram rw " \ 609 "console=$consoledev,$baudrate $othbootargs;" \ 610 "tftp $ramdiskaddr $ramdiskfile;" \ 611 "tftp $loadaddr $bootfile;" \ 612 "tftp $fdtaddr $fdtfile;" \ 613 "bootm $loadaddr $ramdiskaddr $fdtaddr" 614 615 #define CONFIG_BOOTCOMMAND \ 616 "setenv bootargs root=/dev/$bdev rw " \ 617 "console=$consoledev,$baudrate $othbootargs;" \ 618 "tftp $loadaddr $bootfile;" \ 619 "tftp $fdtaddr $fdtfile;" \ 620 "bootm $loadaddr - $fdtaddr" 621 622 #endif /* __CONFIG_H */ 623