1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_MPC86xx 1 /* MPC86xx */ 18 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 19 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 21 22 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 23 24 /* video */ 25 #undef CONFIG_VIDEO 26 27 #ifdef CONFIG_VIDEO 28 #define CONFIG_CMD_BMP 29 #define CONFIG_CFB_CONSOLE 30 #define CONFIG_VGA_AS_SINGLE_DEVICE 31 #define CONFIG_VIDEO_LOGO 32 #define CONFIG_VIDEO_BMP_LOGO 33 #endif 34 35 #ifdef RUN_DIAG 36 #define CONFIG_SYS_DIAG_ADDR 0xff800000 37 #endif 38 39 /* 40 * virtual address to be used for temporary mappings. There 41 * should be 128k free at this VA. 42 */ 43 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 44 45 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 46 #define CONFIG_PCI1 1 /* PCI controler 1 */ 47 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 48 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 49 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 50 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 53 #define CONFIG_ENV_OVERWRITE 54 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 55 56 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 57 #define CONFIG_ALTIVEC 1 58 59 /* 60 * L2CR setup -- make sure this is right for your board! 61 */ 62 #define CONFIG_SYS_L2 63 #define L2_INIT 0 64 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 65 66 #ifndef CONFIG_SYS_CLK_FREQ 67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 68 #endif 69 70 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 71 #define CONFIG_MISC_INIT_R 1 72 73 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 74 #define CONFIG_SYS_MEMTEST_END 0x00400000 75 76 /* 77 * Base addresses -- Note these are effective addresses where the 78 * actual resources get mapped (not physical addresses) 79 */ 80 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 81 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 82 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 83 84 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 85 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 86 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 87 88 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) 89 90 /* DDR Setup */ 91 #define CONFIG_FSL_DDR2 92 #undef CONFIG_FSL_DDR_INTERACTIVE 93 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 94 #define CONFIG_DDR_SPD 95 96 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 97 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 98 99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 101 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 102 #define CONFIG_VERY_BIG_RAM 103 104 #define CONFIG_NUM_DDR_CONTROLLERS 1 105 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 106 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 107 108 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 109 110 /* These are used when DDR doesn't use SPD. */ 111 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 112 113 #if 0 /* TODO */ 114 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 115 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 116 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 117 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 118 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 119 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 120 #define CONFIG_SYS_DDR_MODE_1 0x00480432 121 #define CONFIG_SYS_DDR_MODE_2 0x00000000 122 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 123 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 124 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 125 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 126 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 127 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 128 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 129 130 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 131 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 132 #define CONFIG_SYS_DDR_SBE 0x000f0000 133 134 #endif 135 136 137 #define CONFIG_ID_EEPROM 138 #define CONFIG_SYS_I2C_EEPROM_NXID 139 #define CONFIG_ID_EEPROM 140 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 141 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 142 143 144 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 145 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 146 147 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 148 149 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 150 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 151 152 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 153 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 154 #if 0 /* TODO */ 155 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 156 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 157 #endif 158 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 159 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 160 161 162 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 163 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 164 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 165 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 166 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 167 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 168 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 169 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 170 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 171 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 172 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 173 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 174 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 175 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 176 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 177 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 178 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 179 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 180 181 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 182 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 183 184 #undef CONFIG_SYS_FLASH_CHECKSUM 185 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 186 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 187 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 188 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 189 190 #define CONFIG_FLASH_CFI_DRIVER 191 #define CONFIG_SYS_FLASH_CFI 192 #define CONFIG_SYS_FLASH_EMPTY_INFO 193 194 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 195 #define CONFIG_SYS_RAMBOOT 196 #else 197 #undef CONFIG_SYS_RAMBOOT 198 #endif 199 200 #if defined(CONFIG_SYS_RAMBOOT) 201 #undef CONFIG_SPD_EEPROM 202 #define CONFIG_SYS_SDRAM_SIZE 256 203 #endif 204 205 #undef CONFIG_CLOCKS_IN_MHZ 206 207 #define CONFIG_SYS_INIT_RAM_LOCK 1 208 #ifndef CONFIG_SYS_INIT_RAM_LOCK 209 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 210 #else 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 212 #endif 213 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 214 215 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 216 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 217 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 218 219 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 220 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 221 222 /* Serial Port */ 223 #define CONFIG_CONS_INDEX 1 224 #define CONFIG_SYS_NS16550 225 #define CONFIG_SYS_NS16550_SERIAL 226 #define CONFIG_SYS_NS16550_REG_SIZE 1 227 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 228 229 #define CONFIG_SYS_BAUDRATE_TABLE \ 230 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 231 232 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 233 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 234 235 /* Use the HUSH parser */ 236 #define CONFIG_SYS_HUSH_PARSER 237 #ifdef CONFIG_SYS_HUSH_PARSER 238 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 239 #endif 240 241 /* 242 * Pass open firmware flat tree to kernel 243 */ 244 #define CONFIG_OF_LIBFDT 1 245 #define CONFIG_OF_BOARD_SETUP 1 246 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 247 248 249 /* maximum size of the flat tree (8K) */ 250 #define OF_FLAT_TREE_MAX_SIZE 8192 251 252 /* 253 * I2C 254 */ 255 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 256 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 257 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 258 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 259 #define CONFIG_SYS_I2C_SLAVE 0x7F 260 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 261 #define CONFIG_SYS_I2C_OFFSET 0x3000 262 263 /* 264 * General PCI 265 * Addresses are mapped 1-1. 266 */ 267 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 268 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 269 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 270 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 271 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 272 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 273 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 274 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 275 276 /* controller 1, Base address 0xa000 */ 277 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 278 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 279 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 280 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 281 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 282 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 283 284 /* controller 2, Base Address 0x9000 */ 285 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 286 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 287 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 288 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 289 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 290 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 291 292 293 #if defined(CONFIG_PCI) 294 295 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 296 297 #define CONFIG_NET_MULTI 298 #define CONFIG_CMD_NET 299 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 300 #define CONFIG_CMD_REGINFO 301 302 #define CONFIG_ULI526X 303 #ifdef CONFIG_ULI526X 304 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 305 #endif 306 307 /************************************************************ 308 * USB support 309 ************************************************************/ 310 #define CONFIG_PCI_OHCI 1 311 #define CONFIG_USB_OHCI_NEW 1 312 #define CONFIG_USB_KEYBOARD 1 313 #define CONFIG_SYS_STDIO_DEREGISTER 314 #define CONFIG_SYS_USB_EVENT_POLL 1 315 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 316 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 317 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 318 319 #if !defined(CONFIG_PCI_PNP) 320 #define PCI_ENET0_IOADDR 0xe0000000 321 #define PCI_ENET0_MEMADDR 0xe0000000 322 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 323 #endif 324 325 #define CONFIG_DOS_PARTITION 326 #define CONFIG_SCSI_AHCI 327 328 #ifdef CONFIG_SCSI_AHCI 329 #define CONFIG_SATA_ULI5288 330 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 331 #define CONFIG_SYS_SCSI_MAX_LUN 1 332 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 333 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 334 #endif 335 336 #endif /* CONFIG_PCI */ 337 338 /* 339 * BAT0 2G Cacheable, non-guarded 340 * 0x0000_0000 2G DDR 341 */ 342 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 343 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 344 345 /* 346 * BAT1 1G Cache-inhibited, guarded 347 * 0x8000_0000 256M PCI-1 Memory 348 * 0xa000_0000 256M PCI-Express 1 Memory 349 * 0x9000_0000 256M PCI-Express 2 Memory 350 */ 351 352 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 353 | BATL_GUARDEDSTORAGE) 354 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 355 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 356 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 357 358 /* 359 * BAT2 16M Cache-inhibited, guarded 360 * 0xe100_0000 1M PCI-1 I/O 361 */ 362 363 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 364 | BATL_GUARDEDSTORAGE) 365 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 366 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 367 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 368 369 /* 370 * BAT3 4M Cache-inhibited, guarded 371 * 0xe000_0000 4M CCSR 372 */ 373 374 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 375 | BATL_GUARDEDSTORAGE) 376 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 377 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 378 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 379 380 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 381 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 382 | BATL_PP_RW | BATL_CACHEINHIBIT \ 383 | BATL_GUARDEDSTORAGE) 384 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 385 | BATU_BL_1M | BATU_VS | BATU_VP) 386 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 387 | BATL_PP_RW | BATL_CACHEINHIBIT) 388 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 389 #endif 390 391 /* 392 * BAT4 32M Cache-inhibited, guarded 393 * 0xe200_0000 1M PCI-Express 2 I/O 394 * 0xe300_0000 1M PCI-Express 1 I/O 395 */ 396 397 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 398 | BATL_GUARDEDSTORAGE) 399 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 400 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 401 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 402 403 404 /* 405 * BAT5 128K Cacheable, non-guarded 406 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 407 */ 408 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 409 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 410 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 411 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 412 413 /* 414 * BAT6 256M Cache-inhibited, guarded 415 * 0xf000_0000 256M FLASH 416 */ 417 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 418 | BATL_GUARDEDSTORAGE) 419 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 420 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 421 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 422 423 /* Map the last 1M of flash where we're running from reset */ 424 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 425 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 426 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 427 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 428 | BATL_MEMCOHERENCE) 429 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 430 431 /* 432 * BAT7 4M Cache-inhibited, guarded 433 * 0xe800_0000 4M PIXIS 434 */ 435 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 436 | BATL_GUARDEDSTORAGE) 437 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 438 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 439 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 440 441 442 /* 443 * Environment 444 */ 445 #ifndef CONFIG_SYS_RAMBOOT 446 #define CONFIG_ENV_IS_IN_FLASH 1 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 448 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 449 #define CONFIG_ENV_SIZE 0x2000 450 #else 451 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 452 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 453 #define CONFIG_ENV_SIZE 0x2000 454 #endif 455 456 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 457 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 458 459 460 /* 461 * BOOTP options 462 */ 463 #define CONFIG_BOOTP_BOOTFILESIZE 464 #define CONFIG_BOOTP_BOOTPATH 465 #define CONFIG_BOOTP_GATEWAY 466 #define CONFIG_BOOTP_HOSTNAME 467 468 469 /* 470 * Command line configuration. 471 */ 472 #include <config_cmd_default.h> 473 474 #define CONFIG_CMD_PING 475 #define CONFIG_CMD_I2C 476 #define CONFIG_CMD_MII 477 478 #if defined(CONFIG_SYS_RAMBOOT) 479 #undef CONFIG_CMD_SAVEENV 480 #endif 481 482 #if defined(CONFIG_PCI) 483 #define CONFIG_CMD_PCI 484 #define CONFIG_CMD_SCSI 485 #define CONFIG_CMD_EXT2 486 #define CONFIG_CMD_USB 487 #endif 488 489 490 #define CONFIG_WATCHDOG /* watchdog enabled */ 491 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 492 493 /*DIU Configuration*/ 494 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 495 496 /* 497 * Miscellaneous configurable options 498 */ 499 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 500 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 501 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 502 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 503 504 #if defined(CONFIG_CMD_KGDB) 505 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 506 #else 507 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 508 #endif 509 510 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 511 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 512 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 513 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 514 515 /* 516 * For booting Linux, the board info and command line data 517 * have to be in the first 8 MB of memory, since this is 518 * the maximum mapped by the Linux kernel during initialization. 519 */ 520 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 521 522 /* 523 * Internal Definitions 524 * 525 * Boot Flags 526 */ 527 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 528 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 529 530 #if defined(CONFIG_CMD_KGDB) 531 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 532 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 533 #endif 534 535 /* 536 * Environment Configuration 537 */ 538 #define CONFIG_IPADDR 192.168.1.100 539 540 #define CONFIG_HOSTNAME unknown 541 #define CONFIG_ROOTPATH /opt/nfsroot 542 #define CONFIG_BOOTFILE uImage 543 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 544 545 #define CONFIG_SERVERIP 192.168.1.1 546 #define CONFIG_GATEWAYIP 192.168.1.1 547 #define CONFIG_NETMASK 255.255.255.0 548 549 /* default location for tftp and bootm */ 550 #define CONFIG_LOADADDR 1000000 551 552 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 553 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 554 555 #define CONFIG_BAUDRATE 115200 556 557 #if defined(CONFIG_PCI1) 558 #define PCI_ENV \ 559 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 560 "echo e;md ${a}e00 9\0" \ 561 "pci1regs=setenv a e0008; run pcireg\0" \ 562 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 563 "pci d.w $b.0 56 1\0" \ 564 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 565 "pci w.w $b.0 56 ffff\0" \ 566 "pci1err=setenv a e0008; run pcierr\0" \ 567 "pci1errc=setenv a e0008; run pcierrc\0" 568 #else 569 #define PCI_ENV "" 570 #endif 571 572 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 573 #define PCIE_ENV \ 574 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 575 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 576 "pcie1regs=setenv a e000a; run pciereg\0" \ 577 "pcie2regs=setenv a e0009; run pciereg\0" \ 578 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 579 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 580 "pci d $b.0 130 1\0" \ 581 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 582 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 583 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 584 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 585 "pcie1err=setenv a e000a; run pcieerr\0" \ 586 "pcie2err=setenv a e0009; run pcieerr\0" \ 587 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 588 "pcie2errc=setenv a e0009; run pcieerrc\0" 589 #else 590 #define PCIE_ENV "" 591 #endif 592 593 #define DMA_ENV \ 594 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 595 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 596 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 597 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 598 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 599 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 600 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 601 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 602 603 #ifdef ENV_DEBUG 604 #define CONFIG_EXTRA_ENV_SETTINGS \ 605 "netdev=eth0\0" \ 606 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 607 "tftpflash=tftpboot $loadaddr $uboot; " \ 608 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 609 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 610 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 611 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 612 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 613 "consoledev=ttyS0\0" \ 614 "ramdiskaddr=2000000\0" \ 615 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 616 "fdtaddr=c00000\0" \ 617 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 618 "bdev=sda3\0" \ 619 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 620 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 621 "maxcpus=1" \ 622 "eoi=mw e00400b0 0\0" \ 623 "iack=md e00400a0 1\0" \ 624 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 625 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 626 "md ${a}f00 5\0" \ 627 "ddr1regs=setenv a e0002; run ddrreg\0" \ 628 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 629 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 630 "md ${a}e60 1; md ${a}ef0 1d\0" \ 631 "guregs=setenv a e00e0; run gureg\0" \ 632 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 633 "mcmregs=setenv a e0001; run mcmreg\0" \ 634 "diuregs=md e002c000 1d\0" \ 635 "dium=mw e002c01c\0" \ 636 "diuerr=md e002c014 1\0" \ 637 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 638 "monitor=0-DVI\0" \ 639 "pmregs=md e00e1000 2b\0" \ 640 "lawregs=md e0000c08 4b\0" \ 641 "lbcregs=md e0005000 36\0" \ 642 "dma0regs=md e0021100 12\0" \ 643 "dma1regs=md e0021180 12\0" \ 644 "dma2regs=md e0021200 12\0" \ 645 "dma3regs=md e0021280 12\0" \ 646 PCI_ENV \ 647 PCIE_ENV \ 648 DMA_ENV 649 #else 650 #define CONFIG_EXTRA_ENV_SETTINGS \ 651 "netdev=eth0\0" \ 652 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 653 "consoledev=ttyS0\0" \ 654 "ramdiskaddr=2000000\0" \ 655 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 656 "fdtaddr=c00000\0" \ 657 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 658 "bdev=sda3\0" \ 659 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 660 "monitor=0-DVI\0" 661 #endif 662 663 #define CONFIG_NFSBOOTCOMMAND \ 664 "setenv bootargs root=/dev/nfs rw " \ 665 "nfsroot=$serverip:$rootpath " \ 666 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 667 "console=$consoledev,$baudrate $othbootargs;" \ 668 "tftp $loadaddr $bootfile;" \ 669 "tftp $fdtaddr $fdtfile;" \ 670 "bootm $loadaddr - $fdtaddr" 671 672 #define CONFIG_RAMBOOTCOMMAND \ 673 "setenv bootargs root=/dev/ram rw " \ 674 "console=$consoledev,$baudrate $othbootargs;" \ 675 "tftp $ramdiskaddr $ramdiskfile;" \ 676 "tftp $loadaddr $bootfile;" \ 677 "tftp $fdtaddr $fdtfile;" \ 678 "bootm $loadaddr $ramdiskaddr $fdtaddr" 679 680 #define CONFIG_BOOTCOMMAND \ 681 "setenv bootargs root=/dev/$bdev rw " \ 682 "console=$consoledev,$baudrate $othbootargs;" \ 683 "tftp $loadaddr $bootfile;" \ 684 "tftp $fdtaddr $fdtfile;" \ 685 "bootm $loadaddr - $fdtaddr" 686 687 #endif /* __CONFIG_H */ 688