1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 /* 8 * MPC8610HPCD board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 16 17 #define CONFIG_SYS_TEXT_BASE 0xfff00000 18 19 /* video */ 20 #define CONFIG_FSL_DIU_FB 21 22 #ifdef CONFIG_FSL_DIU_FB 23 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 24 #define CONFIG_VIDEO_LOGO 25 #define CONFIG_VIDEO_BMP_LOGO 26 #endif 27 28 #ifdef RUN_DIAG 29 #define CONFIG_SYS_DIAG_ADDR 0xff800000 30 #endif 31 32 /* 33 * virtual address to be used for temporary mappings. There 34 * should be 128k free at this VA. 35 */ 36 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 37 38 #define CONFIG_PCI1 1 /* PCI controller 1 */ 39 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 40 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 41 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 42 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 43 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 44 45 #define CONFIG_ENV_OVERWRITE 46 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 47 48 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 49 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 50 #define CONFIG_ALTIVEC 1 51 52 /* 53 * L2CR setup -- make sure this is right for your board! 54 */ 55 #define CONFIG_SYS_L2 56 #define L2_INIT 0 57 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 58 59 #ifndef CONFIG_SYS_CLK_FREQ 60 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 61 #endif 62 63 #define CONFIG_MISC_INIT_R 1 64 65 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 66 #define CONFIG_SYS_MEMTEST_END 0x00400000 67 68 /* 69 * Base addresses -- Note these are effective addresses where the 70 * actual resources get mapped (not physical addresses) 71 */ 72 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 73 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 74 75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 76 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 77 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 78 79 /* DDR Setup */ 80 #undef CONFIG_FSL_DDR_INTERACTIVE 81 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 82 #define CONFIG_DDR_SPD 83 84 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 86 87 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 88 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 89 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 90 #define CONFIG_VERY_BIG_RAM 91 92 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 93 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 94 95 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 96 97 /* These are used when DDR doesn't use SPD. */ 98 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 99 100 #if 0 /* TODO */ 101 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 102 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 103 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 104 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 105 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 106 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 107 #define CONFIG_SYS_DDR_MODE_1 0x00480432 108 #define CONFIG_SYS_DDR_MODE_2 0x00000000 109 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 110 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 111 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 112 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 113 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 114 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 115 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 116 117 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 118 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 119 #define CONFIG_SYS_DDR_SBE 0x000f0000 120 121 #endif 122 123 #define CONFIG_ID_EEPROM 124 #define CONFIG_SYS_I2C_EEPROM_NXID 125 #define CONFIG_ID_EEPROM 126 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 127 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 128 129 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 130 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 131 132 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 133 134 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 135 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 136 137 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 138 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 139 #if 0 /* TODO */ 140 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 141 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 142 #endif 143 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 144 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 145 146 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 147 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 148 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 149 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 150 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 151 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 152 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 153 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 154 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 155 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 156 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 157 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 158 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 159 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 160 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 161 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 162 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 163 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 164 165 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 166 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 167 168 #undef CONFIG_SYS_FLASH_CHECKSUM 169 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 170 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 172 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 173 174 #define CONFIG_FLASH_CFI_DRIVER 175 #define CONFIG_SYS_FLASH_CFI 176 #define CONFIG_SYS_FLASH_EMPTY_INFO 177 178 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 179 #define CONFIG_SYS_RAMBOOT 180 #else 181 #undef CONFIG_SYS_RAMBOOT 182 #endif 183 184 #if defined(CONFIG_SYS_RAMBOOT) 185 #undef CONFIG_SPD_EEPROM 186 #define CONFIG_SYS_SDRAM_SIZE 256 187 #endif 188 189 #undef CONFIG_CLOCKS_IN_MHZ 190 191 #define CONFIG_SYS_INIT_RAM_LOCK 1 192 #ifndef CONFIG_SYS_INIT_RAM_LOCK 193 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 194 #else 195 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 196 #endif 197 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 198 199 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 200 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 201 202 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 203 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 204 205 /* Serial Port */ 206 #define CONFIG_CONS_INDEX 1 207 #define CONFIG_SYS_NS16550_SERIAL 208 #define CONFIG_SYS_NS16550_REG_SIZE 1 209 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 210 211 #define CONFIG_SYS_BAUDRATE_TABLE \ 212 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 213 214 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 215 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 216 217 /* maximum size of the flat tree (8K) */ 218 #define OF_FLAT_TREE_MAX_SIZE 8192 219 220 /* 221 * I2C 222 */ 223 #define CONFIG_SYS_I2C 224 #define CONFIG_SYS_I2C_FSL 225 #define CONFIG_SYS_FSL_I2C_SPEED 400000 226 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 228 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 229 230 /* 231 * General PCI 232 * Addresses are mapped 1-1. 233 */ 234 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 235 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 236 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 237 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 238 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 239 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 240 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 241 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 242 243 /* controller 1, Base address 0xa000 */ 244 #define CONFIG_SYS_PCIE1_NAME "ULI" 245 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 246 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 247 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 248 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 249 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 250 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 251 252 /* controller 2, Base Address 0x9000 */ 253 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 254 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 255 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 256 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 257 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 258 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 259 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 260 261 #if defined(CONFIG_PCI) 262 263 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 264 265 #define CONFIG_ULI526X 266 #ifdef CONFIG_ULI526X 267 #endif 268 269 /************************************************************ 270 * USB support 271 ************************************************************/ 272 #define CONFIG_PCI_OHCI 1 273 #define CONFIG_USB_OHCI_NEW 1 274 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 275 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 276 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 277 278 #if !defined(CONFIG_PCI_PNP) 279 #define PCI_ENET0_IOADDR 0xe0000000 280 #define PCI_ENET0_MEMADDR 0xe0000000 281 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 282 #endif 283 284 #define CONFIG_SCSI_AHCI 285 286 #ifdef CONFIG_SCSI_AHCI 287 #define CONFIG_LIBATA 288 #define CONFIG_SATA_ULI5288 289 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 290 #define CONFIG_SYS_SCSI_MAX_LUN 1 291 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 292 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 293 #endif 294 295 #endif /* CONFIG_PCI */ 296 297 /* 298 * BAT0 2G Cacheable, non-guarded 299 * 0x0000_0000 2G DDR 300 */ 301 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 302 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 303 304 /* 305 * BAT1 1G Cache-inhibited, guarded 306 * 0x8000_0000 256M PCI-1 Memory 307 * 0xa000_0000 256M PCI-Express 1 Memory 308 * 0x9000_0000 256M PCI-Express 2 Memory 309 */ 310 311 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 312 | BATL_GUARDEDSTORAGE) 313 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 314 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 315 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 316 317 /* 318 * BAT2 16M Cache-inhibited, guarded 319 * 0xe100_0000 1M PCI-1 I/O 320 */ 321 322 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 323 | BATL_GUARDEDSTORAGE) 324 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 325 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 326 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 327 328 /* 329 * BAT3 4M Cache-inhibited, guarded 330 * 0xe000_0000 4M CCSR 331 */ 332 333 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 334 | BATL_GUARDEDSTORAGE) 335 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 336 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 337 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 338 339 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 340 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 341 | BATL_PP_RW | BATL_CACHEINHIBIT \ 342 | BATL_GUARDEDSTORAGE) 343 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 344 | BATU_BL_1M | BATU_VS | BATU_VP) 345 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 346 | BATL_PP_RW | BATL_CACHEINHIBIT) 347 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 348 #endif 349 350 /* 351 * BAT4 32M Cache-inhibited, guarded 352 * 0xe200_0000 1M PCI-Express 2 I/O 353 * 0xe300_0000 1M PCI-Express 1 I/O 354 */ 355 356 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 357 | BATL_GUARDEDSTORAGE) 358 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 359 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 360 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 361 362 /* 363 * BAT5 128K Cacheable, non-guarded 364 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 365 */ 366 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 367 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 368 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 369 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 370 371 /* 372 * BAT6 256M Cache-inhibited, guarded 373 * 0xf000_0000 256M FLASH 374 */ 375 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 376 | BATL_GUARDEDSTORAGE) 377 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 378 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 379 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 380 381 /* Map the last 1M of flash where we're running from reset */ 382 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 383 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 384 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 385 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 386 | BATL_MEMCOHERENCE) 387 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 388 389 /* 390 * BAT7 4M Cache-inhibited, guarded 391 * 0xe800_0000 4M PIXIS 392 */ 393 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 394 | BATL_GUARDEDSTORAGE) 395 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 396 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 397 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 398 399 /* 400 * Environment 401 */ 402 #ifndef CONFIG_SYS_RAMBOOT 403 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 404 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 405 #define CONFIG_ENV_SIZE 0x2000 406 #else 407 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 408 #define CONFIG_ENV_SIZE 0x2000 409 #endif 410 411 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 412 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 413 414 /* 415 * BOOTP options 416 */ 417 #define CONFIG_BOOTP_BOOTFILESIZE 418 #define CONFIG_BOOTP_BOOTPATH 419 #define CONFIG_BOOTP_GATEWAY 420 #define CONFIG_BOOTP_HOSTNAME 421 422 /* 423 * Command line configuration. 424 */ 425 426 #define CONFIG_WATCHDOG /* watchdog enabled */ 427 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 428 429 /* 430 * Miscellaneous configurable options 431 */ 432 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 433 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 434 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 435 436 /* 437 * For booting Linux, the board info and command line data 438 * have to be in the first 8 MB of memory, since this is 439 * the maximum mapped by the Linux kernel during initialization. 440 */ 441 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 442 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 443 444 #if defined(CONFIG_CMD_KGDB) 445 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 446 #endif 447 448 /* 449 * Environment Configuration 450 */ 451 #define CONFIG_IPADDR 192.168.1.100 452 453 #define CONFIG_HOSTNAME unknown 454 #define CONFIG_ROOTPATH "/opt/nfsroot" 455 #define CONFIG_BOOTFILE "uImage" 456 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 457 458 #define CONFIG_SERVERIP 192.168.1.1 459 #define CONFIG_GATEWAYIP 192.168.1.1 460 #define CONFIG_NETMASK 255.255.255.0 461 462 /* default location for tftp and bootm */ 463 #define CONFIG_LOADADDR 0x10000000 464 465 #if defined(CONFIG_PCI1) 466 #define PCI_ENV \ 467 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 468 "echo e;md ${a}e00 9\0" \ 469 "pci1regs=setenv a e0008; run pcireg\0" \ 470 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 471 "pci d.w $b.0 56 1\0" \ 472 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 473 "pci w.w $b.0 56 ffff\0" \ 474 "pci1err=setenv a e0008; run pcierr\0" \ 475 "pci1errc=setenv a e0008; run pcierrc\0" 476 #else 477 #define PCI_ENV "" 478 #endif 479 480 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 481 #define PCIE_ENV \ 482 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 483 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 484 "pcie1regs=setenv a e000a; run pciereg\0" \ 485 "pcie2regs=setenv a e0009; run pciereg\0" \ 486 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 487 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 488 "pci d $b.0 130 1\0" \ 489 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 490 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 491 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 492 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 493 "pcie1err=setenv a e000a; run pcieerr\0" \ 494 "pcie2err=setenv a e0009; run pcieerr\0" \ 495 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 496 "pcie2errc=setenv a e0009; run pcieerrc\0" 497 #else 498 #define PCIE_ENV "" 499 #endif 500 501 #define DMA_ENV \ 502 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 503 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 504 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 505 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 506 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 507 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 508 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 509 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 510 511 #ifdef ENV_DEBUG 512 #define CONFIG_EXTRA_ENV_SETTINGS \ 513 "netdev=eth0\0" \ 514 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 515 "tftpflash=tftpboot $loadaddr $uboot; " \ 516 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 517 " +$filesize; " \ 518 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 519 " +$filesize; " \ 520 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 521 " $filesize; " \ 522 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 523 " +$filesize; " \ 524 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 525 " $filesize\0" \ 526 "consoledev=ttyS0\0" \ 527 "ramdiskaddr=0x18000000\0" \ 528 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 529 "fdtaddr=0x17c00000\0" \ 530 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 531 "bdev=sda3\0" \ 532 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 533 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 534 "maxcpus=1" \ 535 "eoi=mw e00400b0 0\0" \ 536 "iack=md e00400a0 1\0" \ 537 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 538 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 539 "md ${a}f00 5\0" \ 540 "ddr1regs=setenv a e0002; run ddrreg\0" \ 541 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 542 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 543 "md ${a}e60 1; md ${a}ef0 1d\0" \ 544 "guregs=setenv a e00e0; run gureg\0" \ 545 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 546 "mcmregs=setenv a e0001; run mcmreg\0" \ 547 "diuregs=md e002c000 1d\0" \ 548 "dium=mw e002c01c\0" \ 549 "diuerr=md e002c014 1\0" \ 550 "pmregs=md e00e1000 2b\0" \ 551 "lawregs=md e0000c08 4b\0" \ 552 "lbcregs=md e0005000 36\0" \ 553 "dma0regs=md e0021100 12\0" \ 554 "dma1regs=md e0021180 12\0" \ 555 "dma2regs=md e0021200 12\0" \ 556 "dma3regs=md e0021280 12\0" \ 557 PCI_ENV \ 558 PCIE_ENV \ 559 DMA_ENV 560 #else 561 #define CONFIG_EXTRA_ENV_SETTINGS \ 562 "netdev=eth0\0" \ 563 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 564 "consoledev=ttyS0\0" \ 565 "ramdiskaddr=0x18000000\0" \ 566 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 567 "fdtaddr=0x17c00000\0" \ 568 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 569 "bdev=sda3\0" 570 #endif 571 572 #define CONFIG_NFSBOOTCOMMAND \ 573 "setenv bootargs root=/dev/nfs rw " \ 574 "nfsroot=$serverip:$rootpath " \ 575 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 576 "console=$consoledev,$baudrate $othbootargs;" \ 577 "tftp $loadaddr $bootfile;" \ 578 "tftp $fdtaddr $fdtfile;" \ 579 "bootm $loadaddr - $fdtaddr" 580 581 #define CONFIG_RAMBOOTCOMMAND \ 582 "setenv bootargs root=/dev/ram rw " \ 583 "console=$consoledev,$baudrate $othbootargs;" \ 584 "tftp $ramdiskaddr $ramdiskfile;" \ 585 "tftp $loadaddr $bootfile;" \ 586 "tftp $fdtaddr $fdtfile;" \ 587 "bootm $loadaddr $ramdiskaddr $fdtaddr" 588 589 #define CONFIG_BOOTCOMMAND \ 590 "setenv bootargs root=/dev/$bdev rw " \ 591 "console=$consoledev,$baudrate $othbootargs;" \ 592 "tftp $loadaddr $bootfile;" \ 593 "tftp $fdtaddr $fdtfile;" \ 594 "bootm $loadaddr - $fdtaddr" 595 596 #endif /* __CONFIG_H */ 597