1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2007-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * MPC8610HPCD board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 15 16 /* video */ 17 #define CONFIG_FSL_DIU_FB 18 19 #ifdef CONFIG_FSL_DIU_FB 20 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 21 #define CONFIG_VIDEO_LOGO 22 #define CONFIG_VIDEO_BMP_LOGO 23 #endif 24 25 #ifdef RUN_DIAG 26 #define CONFIG_SYS_DIAG_ADDR 0xff800000 27 #endif 28 29 /* 30 * virtual address to be used for temporary mappings. There 31 * should be 128k free at this VA. 32 */ 33 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 34 35 #define CONFIG_PCI1 1 /* PCI controller 1 */ 36 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 37 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 38 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 39 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 41 42 #define CONFIG_ENV_OVERWRITE 43 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 44 45 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 46 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 47 #define CONFIG_ALTIVEC 1 48 49 /* 50 * L2CR setup -- make sure this is right for your board! 51 */ 52 #define CONFIG_SYS_L2 53 #define L2_INIT 0 54 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 58 #endif 59 60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 61 #define CONFIG_SYS_MEMTEST_END 0x00400000 62 63 /* 64 * Base addresses -- Note these are effective addresses where the 65 * actual resources get mapped (not physical addresses) 66 */ 67 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 68 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 69 70 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 71 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 72 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 73 74 /* DDR Setup */ 75 #undef CONFIG_FSL_DDR_INTERACTIVE 76 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 77 #define CONFIG_DDR_SPD 78 79 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 80 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 81 82 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 83 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 84 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 85 #define CONFIG_VERY_BIG_RAM 86 87 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 88 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 89 90 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 91 92 /* These are used when DDR doesn't use SPD. */ 93 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 94 95 #if 0 /* TODO */ 96 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 97 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 98 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 99 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 100 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 101 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 102 #define CONFIG_SYS_DDR_MODE_1 0x00480432 103 #define CONFIG_SYS_DDR_MODE_2 0x00000000 104 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 105 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 106 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 107 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 108 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 109 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 110 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 111 112 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 113 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 114 #define CONFIG_SYS_DDR_SBE 0x000f0000 115 116 #endif 117 118 #define CONFIG_ID_EEPROM 119 #define CONFIG_SYS_I2C_EEPROM_NXID 120 #define CONFIG_ID_EEPROM 121 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 122 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 123 124 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 125 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 126 127 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 128 129 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 130 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 131 132 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 133 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 134 #if 0 /* TODO */ 135 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 136 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 137 #endif 138 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 139 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 140 141 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 142 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 143 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 144 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 145 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 146 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 147 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 148 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 149 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 150 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 151 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 152 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 153 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 154 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 155 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 156 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 157 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 158 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 159 160 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 161 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 162 163 #undef CONFIG_SYS_FLASH_CHECKSUM 164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 167 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 168 169 #define CONFIG_FLASH_CFI_DRIVER 170 #define CONFIG_SYS_FLASH_CFI 171 #define CONFIG_SYS_FLASH_EMPTY_INFO 172 173 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 174 #define CONFIG_SYS_RAMBOOT 175 #else 176 #undef CONFIG_SYS_RAMBOOT 177 #endif 178 179 #if defined(CONFIG_SYS_RAMBOOT) 180 #undef CONFIG_SPD_EEPROM 181 #define CONFIG_SYS_SDRAM_SIZE 256 182 #endif 183 184 #undef CONFIG_CLOCKS_IN_MHZ 185 186 #define CONFIG_SYS_INIT_RAM_LOCK 1 187 #ifndef CONFIG_SYS_INIT_RAM_LOCK 188 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 189 #else 190 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 191 #endif 192 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 193 194 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 195 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 196 197 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 198 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 199 200 /* Serial Port */ 201 #define CONFIG_SYS_NS16550_SERIAL 202 #define CONFIG_SYS_NS16550_REG_SIZE 1 203 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 204 205 #define CONFIG_SYS_BAUDRATE_TABLE \ 206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 207 208 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 209 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 210 211 /* maximum size of the flat tree (8K) */ 212 #define OF_FLAT_TREE_MAX_SIZE 8192 213 214 /* 215 * I2C 216 */ 217 #define CONFIG_SYS_I2C 218 #define CONFIG_SYS_I2C_FSL 219 #define CONFIG_SYS_FSL_I2C_SPEED 400000 220 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 221 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 222 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 223 224 /* 225 * General PCI 226 * Addresses are mapped 1-1. 227 */ 228 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 229 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 230 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 231 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 232 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 233 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 234 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 235 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 236 237 /* controller 1, Base address 0xa000 */ 238 #define CONFIG_SYS_PCIE1_NAME "ULI" 239 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 240 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 241 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 242 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 243 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 244 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 245 246 /* controller 2, Base Address 0x9000 */ 247 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 248 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 249 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 250 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 251 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 252 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 253 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 254 255 #if defined(CONFIG_PCI) 256 257 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 258 259 #define CONFIG_ULI526X 260 261 /************************************************************ 262 * USB support 263 ************************************************************/ 264 #define CONFIG_PCI_OHCI 1 265 #define CONFIG_USB_OHCI_NEW 1 266 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 267 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 268 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 269 270 #if !defined(CONFIG_PCI_PNP) 271 #define PCI_ENET0_IOADDR 0xe0000000 272 #define PCI_ENET0_MEMADDR 0xe0000000 273 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 274 #endif 275 276 #ifdef CONFIG_SCSI_AHCI 277 #define CONFIG_SATA_ULI5288 278 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 279 #define CONFIG_SYS_SCSI_MAX_LUN 1 280 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 281 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 282 #endif 283 284 #endif /* CONFIG_PCI */ 285 286 /* 287 * BAT0 2G Cacheable, non-guarded 288 * 0x0000_0000 2G DDR 289 */ 290 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 291 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 292 293 /* 294 * BAT1 1G Cache-inhibited, guarded 295 * 0x8000_0000 256M PCI-1 Memory 296 * 0xa000_0000 256M PCI-Express 1 Memory 297 * 0x9000_0000 256M PCI-Express 2 Memory 298 */ 299 300 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 301 | BATL_GUARDEDSTORAGE) 302 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 303 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 304 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 305 306 /* 307 * BAT2 16M Cache-inhibited, guarded 308 * 0xe100_0000 1M PCI-1 I/O 309 */ 310 311 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 312 | BATL_GUARDEDSTORAGE) 313 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 314 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 315 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 316 317 /* 318 * BAT3 4M Cache-inhibited, guarded 319 * 0xe000_0000 4M CCSR 320 */ 321 322 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 323 | BATL_GUARDEDSTORAGE) 324 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 325 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 326 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 327 328 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 329 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 330 | BATL_PP_RW | BATL_CACHEINHIBIT \ 331 | BATL_GUARDEDSTORAGE) 332 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 333 | BATU_BL_1M | BATU_VS | BATU_VP) 334 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 335 | BATL_PP_RW | BATL_CACHEINHIBIT) 336 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 337 #endif 338 339 /* 340 * BAT4 32M Cache-inhibited, guarded 341 * 0xe200_0000 1M PCI-Express 2 I/O 342 * 0xe300_0000 1M PCI-Express 1 I/O 343 */ 344 345 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 346 | BATL_GUARDEDSTORAGE) 347 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 348 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 349 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 350 351 /* 352 * BAT5 128K Cacheable, non-guarded 353 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 354 */ 355 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 356 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 357 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 358 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 359 360 /* 361 * BAT6 256M Cache-inhibited, guarded 362 * 0xf000_0000 256M FLASH 363 */ 364 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 365 | BATL_GUARDEDSTORAGE) 366 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 367 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 368 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 369 370 /* Map the last 1M of flash where we're running from reset */ 371 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 372 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 373 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 374 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 375 | BATL_MEMCOHERENCE) 376 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 377 378 /* 379 * BAT7 4M Cache-inhibited, guarded 380 * 0xe800_0000 4M PIXIS 381 */ 382 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 383 | BATL_GUARDEDSTORAGE) 384 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 385 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 386 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 387 388 /* 389 * Environment 390 */ 391 #ifndef CONFIG_SYS_RAMBOOT 392 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 393 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 394 #define CONFIG_ENV_SIZE 0x2000 395 #else 396 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 397 #define CONFIG_ENV_SIZE 0x2000 398 #endif 399 400 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 401 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 402 403 /* 404 * BOOTP options 405 */ 406 #define CONFIG_BOOTP_BOOTFILESIZE 407 408 /* 409 * Command line configuration. 410 */ 411 412 #define CONFIG_WATCHDOG /* watchdog enabled */ 413 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 414 415 /* 416 * Miscellaneous configurable options 417 */ 418 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 419 420 /* 421 * For booting Linux, the board info and command line data 422 * have to be in the first 8 MB of memory, since this is 423 * the maximum mapped by the Linux kernel during initialization. 424 */ 425 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 426 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 427 428 #if defined(CONFIG_CMD_KGDB) 429 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 430 #endif 431 432 /* 433 * Environment Configuration 434 */ 435 #define CONFIG_IPADDR 192.168.1.100 436 437 #define CONFIG_HOSTNAME "unknown" 438 #define CONFIG_ROOTPATH "/opt/nfsroot" 439 #define CONFIG_BOOTFILE "uImage" 440 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 441 442 #define CONFIG_SERVERIP 192.168.1.1 443 #define CONFIG_GATEWAYIP 192.168.1.1 444 #define CONFIG_NETMASK 255.255.255.0 445 446 /* default location for tftp and bootm */ 447 #define CONFIG_LOADADDR 0x10000000 448 449 #if defined(CONFIG_PCI1) 450 #define PCI_ENV \ 451 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 452 "echo e;md ${a}e00 9\0" \ 453 "pci1regs=setenv a e0008; run pcireg\0" \ 454 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 455 "pci d.w $b.0 56 1\0" \ 456 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 457 "pci w.w $b.0 56 ffff\0" \ 458 "pci1err=setenv a e0008; run pcierr\0" \ 459 "pci1errc=setenv a e0008; run pcierrc\0" 460 #else 461 #define PCI_ENV "" 462 #endif 463 464 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 465 #define PCIE_ENV \ 466 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 467 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 468 "pcie1regs=setenv a e000a; run pciereg\0" \ 469 "pcie2regs=setenv a e0009; run pciereg\0" \ 470 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 471 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 472 "pci d $b.0 130 1\0" \ 473 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 474 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 475 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 476 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 477 "pcie1err=setenv a e000a; run pcieerr\0" \ 478 "pcie2err=setenv a e0009; run pcieerr\0" \ 479 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 480 "pcie2errc=setenv a e0009; run pcieerrc\0" 481 #else 482 #define PCIE_ENV "" 483 #endif 484 485 #define DMA_ENV \ 486 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 487 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 488 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 489 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 490 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 491 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 492 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 493 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 494 495 #ifdef ENV_DEBUG 496 #define CONFIG_EXTRA_ENV_SETTINGS \ 497 "netdev=eth0\0" \ 498 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 499 "tftpflash=tftpboot $loadaddr $uboot; " \ 500 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 501 " +$filesize; " \ 502 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 503 " +$filesize; " \ 504 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 505 " $filesize; " \ 506 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 507 " +$filesize; " \ 508 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 509 " $filesize\0" \ 510 "consoledev=ttyS0\0" \ 511 "ramdiskaddr=0x18000000\0" \ 512 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 513 "fdtaddr=0x17c00000\0" \ 514 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 515 "bdev=sda3\0" \ 516 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 517 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 518 "maxcpus=1" \ 519 "eoi=mw e00400b0 0\0" \ 520 "iack=md e00400a0 1\0" \ 521 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 522 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 523 "md ${a}f00 5\0" \ 524 "ddr1regs=setenv a e0002; run ddrreg\0" \ 525 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 526 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 527 "md ${a}e60 1; md ${a}ef0 1d\0" \ 528 "guregs=setenv a e00e0; run gureg\0" \ 529 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 530 "mcmregs=setenv a e0001; run mcmreg\0" \ 531 "diuregs=md e002c000 1d\0" \ 532 "dium=mw e002c01c\0" \ 533 "diuerr=md e002c014 1\0" \ 534 "pmregs=md e00e1000 2b\0" \ 535 "lawregs=md e0000c08 4b\0" \ 536 "lbcregs=md e0005000 36\0" \ 537 "dma0regs=md e0021100 12\0" \ 538 "dma1regs=md e0021180 12\0" \ 539 "dma2regs=md e0021200 12\0" \ 540 "dma3regs=md e0021280 12\0" \ 541 PCI_ENV \ 542 PCIE_ENV \ 543 DMA_ENV 544 #else 545 #define CONFIG_EXTRA_ENV_SETTINGS \ 546 "netdev=eth0\0" \ 547 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 548 "consoledev=ttyS0\0" \ 549 "ramdiskaddr=0x18000000\0" \ 550 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 551 "fdtaddr=0x17c00000\0" \ 552 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 553 "bdev=sda3\0" 554 #endif 555 556 #define CONFIG_NFSBOOTCOMMAND \ 557 "setenv bootargs root=/dev/nfs rw " \ 558 "nfsroot=$serverip:$rootpath " \ 559 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 560 "console=$consoledev,$baudrate $othbootargs;" \ 561 "tftp $loadaddr $bootfile;" \ 562 "tftp $fdtaddr $fdtfile;" \ 563 "bootm $loadaddr - $fdtaddr" 564 565 #define CONFIG_RAMBOOTCOMMAND \ 566 "setenv bootargs root=/dev/ram rw " \ 567 "console=$consoledev,$baudrate $othbootargs;" \ 568 "tftp $ramdiskaddr $ramdiskfile;" \ 569 "tftp $loadaddr $bootfile;" \ 570 "tftp $fdtaddr $fdtfile;" \ 571 "bootm $loadaddr $ramdiskaddr $fdtaddr" 572 573 #define CONFIG_BOOTCOMMAND \ 574 "setenv bootargs root=/dev/$bdev rw " \ 575 "console=$consoledev,$baudrate $othbootargs;" \ 576 "tftp $loadaddr $bootfile;" \ 577 "tftp $fdtaddr $fdtfile;" \ 578 "bootm $loadaddr - $fdtaddr" 579 580 #endif /* __CONFIG_H */ 581