1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_MPC86xx 1 /* MPC86xx */ 18 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 19 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 20 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 21 22 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 23 24 /* video */ 25 #undef CONFIG_VIDEO 26 27 #if defined(CONFIG_VIDEO) 28 #define CONFIG_CFB_CONSOLE 29 #define CONFIG_VGA_AS_SINGLE_DEVICE 30 #endif 31 32 #ifdef RUN_DIAG 33 #define CONFIG_SYS_DIAG_ADDR 0xff800000 34 #endif 35 36 /* 37 * virtual address to be used for temporary mappings. There 38 * should be 128k free at this VA. 39 */ 40 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 41 42 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 43 #define CONFIG_PCI1 1 /* PCI controler 1 */ 44 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 45 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 46 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 47 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 48 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 49 50 #define CONFIG_ENV_OVERWRITE 51 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 52 53 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 54 #define CONFIG_ALTIVEC 1 55 56 /* 57 * L2CR setup -- make sure this is right for your board! 58 */ 59 #define CONFIG_SYS_L2 60 #define L2_INIT 0 61 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 62 63 #ifndef CONFIG_SYS_CLK_FREQ 64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 65 #endif 66 67 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 68 #define CONFIG_MISC_INIT_R 1 69 70 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 71 #define CONFIG_SYS_MEMTEST_END 0x00400000 72 73 /* 74 * Base addresses -- Note these are effective addresses where the 75 * actual resources get mapped (not physical addresses) 76 */ 77 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 78 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 79 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 80 81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 82 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 83 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 84 85 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 86 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 87 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 88 89 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) 90 91 /* DDR Setup */ 92 #define CONFIG_FSL_DDR2 93 #undef CONFIG_FSL_DDR_INTERACTIVE 94 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 95 #define CONFIG_DDR_SPD 96 97 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 98 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 99 100 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 102 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 103 #define CONFIG_VERY_BIG_RAM 104 105 #define MPC86xx_DDR_SDRAM_CLK_CNTL 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 112 113 /* These are used when DDR doesn't use SPD. */ 114 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 115 116 #if 0 /* TODO */ 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 122 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 123 #define CONFIG_SYS_DDR_MODE_1 0x00480432 124 #define CONFIG_SYS_DDR_MODE_2 0x00000000 125 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x000f0000 136 137 #endif 138 139 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_ID_EEPROM 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 146 147 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 148 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 149 150 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 151 152 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 153 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 154 155 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 156 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 157 #if 0 /* TODO */ 158 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 159 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 160 #endif 161 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 162 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 163 164 165 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 166 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 167 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 168 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 169 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 170 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 171 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 172 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 173 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 174 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 175 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 176 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 177 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 178 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 179 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 180 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 181 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 182 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ 183 184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 186 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 191 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 197 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 198 #define CONFIG_SYS_RAMBOOT 199 #else 200 #undef CONFIG_SYS_RAMBOOT 201 #endif 202 203 #if defined(CONFIG_SYS_RAMBOOT) 204 #undef CONFIG_SPD_EEPROM 205 #define CONFIG_SYS_SDRAM_SIZE 256 206 #endif 207 208 #undef CONFIG_CLOCKS_IN_MHZ 209 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #ifndef CONFIG_SYS_INIT_RAM_LOCK 212 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 213 #else 214 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 215 #endif 216 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 217 218 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 219 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 220 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 221 222 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 223 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 224 225 /* Serial Port */ 226 #define CONFIG_CONS_INDEX 1 227 #undef CONFIG_SERIAL_SOFTWARE_FIFO 228 #define CONFIG_SYS_NS16550 229 #define CONFIG_SYS_NS16550_SERIAL 230 #define CONFIG_SYS_NS16550_REG_SIZE 1 231 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 232 233 #define CONFIG_SYS_BAUDRATE_TABLE \ 234 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 235 236 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 237 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 238 239 /* Use the HUSH parser */ 240 #define CONFIG_SYS_HUSH_PARSER 241 #ifdef CONFIG_SYS_HUSH_PARSER 242 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 243 #endif 244 245 /* 246 * Pass open firmware flat tree to kernel 247 */ 248 #define CONFIG_OF_LIBFDT 1 249 #define CONFIG_OF_BOARD_SETUP 1 250 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 251 252 253 /* maximum size of the flat tree (8K) */ 254 #define OF_FLAT_TREE_MAX_SIZE 8192 255 256 #define CONFIG_SYS_64BIT_VSPRINTF 1 257 #define CONFIG_SYS_64BIT_STRTOUL 1 258 259 /* 260 * I2C 261 */ 262 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 263 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 264 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 265 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 266 #define CONFIG_SYS_I2C_SLAVE 0x7F 267 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 268 #define CONFIG_SYS_I2C_OFFSET 0x3000 269 270 /* 271 * General PCI 272 * Addresses are mapped 1-1. 273 */ 274 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 275 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 276 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 277 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 278 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 279 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 280 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 281 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 282 283 /* controller 1, Base address 0xa000 */ 284 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 285 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 286 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 287 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 288 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 289 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 290 291 /* controller 2, Base Address 0x9000 */ 292 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 293 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 294 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 295 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 296 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 297 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 298 299 300 #if defined(CONFIG_PCI) 301 302 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 303 304 #define CONFIG_NET_MULTI 305 #define CONFIG_CMD_NET 306 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 307 #define CONFIG_CMD_REGINFO 308 309 #define CONFIG_ULI526X 310 #ifdef CONFIG_ULI526X 311 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 312 #endif 313 314 /************************************************************ 315 * USB support 316 ************************************************************/ 317 #define CONFIG_PCI_OHCI 1 318 #define CONFIG_USB_OHCI_NEW 1 319 #define CONFIG_USB_KEYBOARD 1 320 #define CONFIG_SYS_STDIO_DEREGISTER 321 #define CONFIG_SYS_USB_EVENT_POLL 1 322 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 323 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 324 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 325 326 #if !defined(CONFIG_PCI_PNP) 327 #define PCI_ENET0_IOADDR 0xe0000000 328 #define PCI_ENET0_MEMADDR 0xe0000000 329 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 330 #endif 331 332 #define CONFIG_DOS_PARTITION 333 #define CONFIG_SCSI_AHCI 334 335 #ifdef CONFIG_SCSI_AHCI 336 #define CONFIG_SATA_ULI5288 337 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 338 #define CONFIG_SYS_SCSI_MAX_LUN 1 339 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 340 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 341 #endif 342 343 #endif /* CONFIG_PCI */ 344 345 /* 346 * BAT0 2G Cacheable, non-guarded 347 * 0x0000_0000 2G DDR 348 */ 349 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 350 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 351 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 352 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 353 354 /* 355 * BAT1 1G Cache-inhibited, guarded 356 * 0x8000_0000 256M PCI-1 Memory 357 * 0xa000_0000 256M PCI-Express 1 Memory 358 * 0x9000_0000 256M PCI-Express 2 Memory 359 */ 360 361 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 362 | BATL_GUARDEDSTORAGE) 363 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 364 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 365 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 366 367 /* 368 * BAT2 16M Cache-inhibited, guarded 369 * 0xe100_0000 1M PCI-1 I/O 370 */ 371 372 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 373 | BATL_GUARDEDSTORAGE) 374 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 375 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 376 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 377 378 /* 379 * BAT3 4M Cache-inhibited, guarded 380 * 0xe000_0000 4M CCSR 381 */ 382 383 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 384 | BATL_GUARDEDSTORAGE) 385 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 386 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 387 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 388 389 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 390 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 391 | BATL_PP_RW | BATL_CACHEINHIBIT \ 392 | BATL_GUARDEDSTORAGE) 393 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 394 | BATU_BL_1M | BATU_VS | BATU_VP) 395 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 396 | BATL_PP_RW | BATL_CACHEINHIBIT) 397 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 398 #endif 399 400 /* 401 * BAT4 32M Cache-inhibited, guarded 402 * 0xe200_0000 1M PCI-Express 2 I/O 403 * 0xe300_0000 1M PCI-Express 1 I/O 404 */ 405 406 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 407 | BATL_GUARDEDSTORAGE) 408 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 409 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 410 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 411 412 413 /* 414 * BAT5 128K Cacheable, non-guarded 415 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 416 */ 417 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 418 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 419 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 420 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 421 422 /* 423 * BAT6 256M Cache-inhibited, guarded 424 * 0xf000_0000 256M FLASH 425 */ 426 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 427 | BATL_GUARDEDSTORAGE) 428 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 429 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 430 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 431 432 /* Map the last 1M of flash where we're running from reset */ 433 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 434 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 435 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 436 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 437 | BATL_MEMCOHERENCE) 438 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 439 440 /* 441 * BAT7 4M Cache-inhibited, guarded 442 * 0xe800_0000 4M PIXIS 443 */ 444 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 445 | BATL_GUARDEDSTORAGE) 446 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 447 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 448 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 449 450 451 /* 452 * Environment 453 */ 454 #ifndef CONFIG_SYS_RAMBOOT 455 #define CONFIG_ENV_IS_IN_FLASH 1 456 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 457 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 458 #define CONFIG_ENV_SIZE 0x2000 459 #else 460 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 461 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 462 #define CONFIG_ENV_SIZE 0x2000 463 #endif 464 465 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 466 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 467 468 469 /* 470 * BOOTP options 471 */ 472 #define CONFIG_BOOTP_BOOTFILESIZE 473 #define CONFIG_BOOTP_BOOTPATH 474 #define CONFIG_BOOTP_GATEWAY 475 #define CONFIG_BOOTP_HOSTNAME 476 477 478 /* 479 * Command line configuration. 480 */ 481 #include <config_cmd_default.h> 482 483 #define CONFIG_CMD_PING 484 #define CONFIG_CMD_I2C 485 #define CONFIG_CMD_MII 486 487 #if defined(CONFIG_SYS_RAMBOOT) 488 #undef CONFIG_CMD_SAVEENV 489 #endif 490 491 #if defined(CONFIG_PCI) 492 #define CONFIG_CMD_PCI 493 #define CONFIG_CMD_SCSI 494 #define CONFIG_CMD_EXT2 495 #define CONFIG_CMD_USB 496 #endif 497 498 499 #define CONFIG_WATCHDOG /* watchdog enabled */ 500 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 501 502 /*DIU Configuration*/ 503 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 504 505 /* 506 * Miscellaneous configurable options 507 */ 508 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 509 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 510 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 511 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 512 513 #if defined(CONFIG_CMD_KGDB) 514 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 515 #else 516 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 517 #endif 518 519 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 520 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 521 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 522 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 523 524 /* 525 * For booting Linux, the board info and command line data 526 * have to be in the first 8 MB of memory, since this is 527 * the maximum mapped by the Linux kernel during initialization. 528 */ 529 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 530 531 /* 532 * Internal Definitions 533 * 534 * Boot Flags 535 */ 536 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 537 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 538 539 #if defined(CONFIG_CMD_KGDB) 540 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 541 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 542 #endif 543 544 /* 545 * Environment Configuration 546 */ 547 #define CONFIG_IPADDR 192.168.1.100 548 549 #define CONFIG_HOSTNAME unknown 550 #define CONFIG_ROOTPATH /opt/nfsroot 551 #define CONFIG_BOOTFILE uImage 552 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 553 554 #define CONFIG_SERVERIP 192.168.1.1 555 #define CONFIG_GATEWAYIP 192.168.1.1 556 #define CONFIG_NETMASK 255.255.255.0 557 558 /* default location for tftp and bootm */ 559 #define CONFIG_LOADADDR 1000000 560 561 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 562 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 563 564 #define CONFIG_BAUDRATE 115200 565 566 #if defined(CONFIG_PCI1) 567 #define PCI_ENV \ 568 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 569 "echo e;md ${a}e00 9\0" \ 570 "pci1regs=setenv a e0008; run pcireg\0" \ 571 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 572 "pci d.w $b.0 56 1\0" \ 573 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 574 "pci w.w $b.0 56 ffff\0" \ 575 "pci1err=setenv a e0008; run pcierr\0" \ 576 "pci1errc=setenv a e0008; run pcierrc\0" 577 #else 578 #define PCI_ENV "" 579 #endif 580 581 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 582 #define PCIE_ENV \ 583 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 584 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 585 "pcie1regs=setenv a e000a; run pciereg\0" \ 586 "pcie2regs=setenv a e0009; run pciereg\0" \ 587 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 588 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 589 "pci d $b.0 130 1\0" \ 590 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 591 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 592 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 593 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 594 "pcie1err=setenv a e000a; run pcieerr\0" \ 595 "pcie2err=setenv a e0009; run pcieerr\0" \ 596 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 597 "pcie2errc=setenv a e0009; run pcieerrc\0" 598 #else 599 #define PCIE_ENV "" 600 #endif 601 602 #define DMA_ENV \ 603 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 604 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 605 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 606 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 607 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 608 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 609 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 610 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 611 612 #ifdef ENV_DEBUG 613 #define CONFIG_EXTRA_ENV_SETTINGS \ 614 "netdev=eth0\0" \ 615 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 616 "tftpflash=tftpboot $loadaddr $uboot; " \ 617 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 618 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 619 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 620 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 621 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 622 "consoledev=ttyS0\0" \ 623 "ramdiskaddr=2000000\0" \ 624 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 625 "fdtaddr=c00000\0" \ 626 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 627 "bdev=sda3\0" \ 628 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 629 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 630 "maxcpus=1" \ 631 "eoi=mw e00400b0 0\0" \ 632 "iack=md e00400a0 1\0" \ 633 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 634 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 635 "md ${a}f00 5\0" \ 636 "ddr1regs=setenv a e0002; run ddrreg\0" \ 637 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 638 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 639 "md ${a}e60 1; md ${a}ef0 1d\0" \ 640 "guregs=setenv a e00e0; run gureg\0" \ 641 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 642 "mcmregs=setenv a e0001; run mcmreg\0" \ 643 "diuregs=md e002c000 1d\0" \ 644 "dium=mw e002c01c\0" \ 645 "diuerr=md e002c014 1\0" \ 646 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 647 "monitor=0-DVI\0" \ 648 "pmregs=md e00e1000 2b\0" \ 649 "lawregs=md e0000c08 4b\0" \ 650 "lbcregs=md e0005000 36\0" \ 651 "dma0regs=md e0021100 12\0" \ 652 "dma1regs=md e0021180 12\0" \ 653 "dma2regs=md e0021200 12\0" \ 654 "dma3regs=md e0021280 12\0" \ 655 PCI_ENV \ 656 PCIE_ENV \ 657 DMA_ENV 658 #else 659 #define CONFIG_EXTRA_ENV_SETTINGS \ 660 "netdev=eth0\0" \ 661 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 662 "consoledev=ttyS0\0" \ 663 "ramdiskaddr=2000000\0" \ 664 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 665 "fdtaddr=c00000\0" \ 666 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 667 "bdev=sda3\0" \ 668 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 669 "monitor=0-DVI\0" 670 #endif 671 672 #define CONFIG_NFSBOOTCOMMAND \ 673 "setenv bootargs root=/dev/nfs rw " \ 674 "nfsroot=$serverip:$rootpath " \ 675 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 676 "console=$consoledev,$baudrate $othbootargs;" \ 677 "tftp $loadaddr $bootfile;" \ 678 "tftp $fdtaddr $fdtfile;" \ 679 "bootm $loadaddr - $fdtaddr" 680 681 #define CONFIG_RAMBOOTCOMMAND \ 682 "setenv bootargs root=/dev/ram rw " \ 683 "console=$consoledev,$baudrate $othbootargs;" \ 684 "tftp $ramdiskaddr $ramdiskfile;" \ 685 "tftp $loadaddr $bootfile;" \ 686 "tftp $fdtaddr $fdtfile;" \ 687 "bootm $loadaddr $ramdiskaddr $fdtaddr" 688 689 #define CONFIG_BOOTCOMMAND \ 690 "setenv bootargs root=/dev/$bdev rw " \ 691 "console=$consoledev,$baudrate $othbootargs;" \ 692 "tftp $loadaddr $bootfile;" \ 693 "tftp $fdtaddr $fdtfile;" \ 694 "bootm $loadaddr - $fdtaddr" 695 696 #endif /* __CONFIG_H */ 697