1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 /* 8 * MPC8610HPCD board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 16 17 #define CONFIG_SYS_TEXT_BASE 0xfff00000 18 19 /* video */ 20 #define CONFIG_FSL_DIU_FB 21 22 #ifdef CONFIG_FSL_DIU_FB 23 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 24 #define CONFIG_CMD_BMP 25 #define CONFIG_VIDEO_LOGO 26 #define CONFIG_VIDEO_BMP_LOGO 27 #endif 28 29 #ifdef RUN_DIAG 30 #define CONFIG_SYS_DIAG_ADDR 0xff800000 31 #endif 32 33 /* 34 * virtual address to be used for temporary mappings. There 35 * should be 128k free at this VA. 36 */ 37 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 38 39 #define CONFIG_PCI1 1 /* PCI controller 1 */ 40 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 41 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 44 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 49 50 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 51 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 52 #define CONFIG_ALTIVEC 1 53 54 /* 55 * L2CR setup -- make sure this is right for your board! 56 */ 57 #define CONFIG_SYS_L2 58 #define L2_INIT 0 59 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 60 61 #ifndef CONFIG_SYS_CLK_FREQ 62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 63 #endif 64 65 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 66 #define CONFIG_MISC_INIT_R 1 67 68 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 69 #define CONFIG_SYS_MEMTEST_END 0x00400000 70 71 /* 72 * Base addresses -- Note these are effective addresses where the 73 * actual resources get mapped (not physical addresses) 74 */ 75 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 76 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 77 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 78 79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 80 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 81 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 82 83 /* DDR Setup */ 84 #define CONFIG_SYS_FSL_DDR2 85 #undef CONFIG_FSL_DDR_INTERACTIVE 86 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 87 #define CONFIG_DDR_SPD 88 89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 91 92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 94 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 95 #define CONFIG_VERY_BIG_RAM 96 97 #define CONFIG_NUM_DDR_CONTROLLERS 1 98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 99 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 100 101 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 102 103 /* These are used when DDR doesn't use SPD. */ 104 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 105 106 #if 0 /* TODO */ 107 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 108 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 109 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 110 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 111 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 112 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 113 #define CONFIG_SYS_DDR_MODE_1 0x00480432 114 #define CONFIG_SYS_DDR_MODE_2 0x00000000 115 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 116 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 117 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 118 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 119 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 120 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 121 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 122 123 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 124 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 125 #define CONFIG_SYS_DDR_SBE 0x000f0000 126 127 #endif 128 129 #define CONFIG_ID_EEPROM 130 #define CONFIG_SYS_I2C_EEPROM_NXID 131 #define CONFIG_ID_EEPROM 132 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 133 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 134 135 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 136 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 137 138 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 139 140 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 141 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 142 143 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 144 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 145 #if 0 /* TODO */ 146 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 147 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 148 #endif 149 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 150 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 151 152 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 153 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 154 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 155 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 156 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 157 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 158 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 159 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 160 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 161 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 162 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 163 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 164 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 165 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 166 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 167 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 168 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 169 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 170 171 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 172 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 173 174 #undef CONFIG_SYS_FLASH_CHECKSUM 175 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 176 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 177 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 178 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 179 180 #define CONFIG_FLASH_CFI_DRIVER 181 #define CONFIG_SYS_FLASH_CFI 182 #define CONFIG_SYS_FLASH_EMPTY_INFO 183 184 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 185 #define CONFIG_SYS_RAMBOOT 186 #else 187 #undef CONFIG_SYS_RAMBOOT 188 #endif 189 190 #if defined(CONFIG_SYS_RAMBOOT) 191 #undef CONFIG_SPD_EEPROM 192 #define CONFIG_SYS_SDRAM_SIZE 256 193 #endif 194 195 #undef CONFIG_CLOCKS_IN_MHZ 196 197 #define CONFIG_SYS_INIT_RAM_LOCK 1 198 #ifndef CONFIG_SYS_INIT_RAM_LOCK 199 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 200 #else 201 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 202 #endif 203 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 204 205 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 206 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 207 208 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 209 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 210 211 /* Serial Port */ 212 #define CONFIG_CONS_INDEX 1 213 #define CONFIG_SYS_NS16550_SERIAL 214 #define CONFIG_SYS_NS16550_REG_SIZE 1 215 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 216 217 #define CONFIG_SYS_BAUDRATE_TABLE \ 218 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 219 220 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 221 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 222 223 /* maximum size of the flat tree (8K) */ 224 #define OF_FLAT_TREE_MAX_SIZE 8192 225 226 /* 227 * I2C 228 */ 229 #define CONFIG_SYS_I2C 230 #define CONFIG_SYS_I2C_FSL 231 #define CONFIG_SYS_FSL_I2C_SPEED 400000 232 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 233 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 234 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 235 236 /* 237 * General PCI 238 * Addresses are mapped 1-1. 239 */ 240 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 241 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 242 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 243 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 244 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 245 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 246 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 247 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 248 249 /* controller 1, Base address 0xa000 */ 250 #define CONFIG_SYS_PCIE1_NAME "ULI" 251 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 252 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 253 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 254 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 255 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 256 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 257 258 /* controller 2, Base Address 0x9000 */ 259 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 260 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 261 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 262 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 263 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 264 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 265 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 266 267 #if defined(CONFIG_PCI) 268 269 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 270 271 #define CONFIG_CMD_REGINFO 272 273 #define CONFIG_ULI526X 274 #ifdef CONFIG_ULI526X 275 #endif 276 277 /************************************************************ 278 * USB support 279 ************************************************************/ 280 #define CONFIG_PCI_OHCI 1 281 #define CONFIG_USB_OHCI_NEW 1 282 #define CONFIG_SYS_USB_EVENT_POLL 1 283 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 284 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 285 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 286 287 #if !defined(CONFIG_PCI_PNP) 288 #define PCI_ENET0_IOADDR 0xe0000000 289 #define PCI_ENET0_MEMADDR 0xe0000000 290 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 291 #endif 292 293 #define CONFIG_DOS_PARTITION 294 #define CONFIG_SCSI_AHCI 295 296 #ifdef CONFIG_SCSI_AHCI 297 #define CONFIG_LIBATA 298 #define CONFIG_SATA_ULI5288 299 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 300 #define CONFIG_SYS_SCSI_MAX_LUN 1 301 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 302 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 303 #endif 304 305 #endif /* CONFIG_PCI */ 306 307 /* 308 * BAT0 2G Cacheable, non-guarded 309 * 0x0000_0000 2G DDR 310 */ 311 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 312 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 313 314 /* 315 * BAT1 1G Cache-inhibited, guarded 316 * 0x8000_0000 256M PCI-1 Memory 317 * 0xa000_0000 256M PCI-Express 1 Memory 318 * 0x9000_0000 256M PCI-Express 2 Memory 319 */ 320 321 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 322 | BATL_GUARDEDSTORAGE) 323 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 324 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 325 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 326 327 /* 328 * BAT2 16M Cache-inhibited, guarded 329 * 0xe100_0000 1M PCI-1 I/O 330 */ 331 332 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 333 | BATL_GUARDEDSTORAGE) 334 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 335 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 336 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 337 338 /* 339 * BAT3 4M Cache-inhibited, guarded 340 * 0xe000_0000 4M CCSR 341 */ 342 343 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 344 | BATL_GUARDEDSTORAGE) 345 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 346 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 347 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 348 349 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 350 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 351 | BATL_PP_RW | BATL_CACHEINHIBIT \ 352 | BATL_GUARDEDSTORAGE) 353 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 354 | BATU_BL_1M | BATU_VS | BATU_VP) 355 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 356 | BATL_PP_RW | BATL_CACHEINHIBIT) 357 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 358 #endif 359 360 /* 361 * BAT4 32M Cache-inhibited, guarded 362 * 0xe200_0000 1M PCI-Express 2 I/O 363 * 0xe300_0000 1M PCI-Express 1 I/O 364 */ 365 366 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 367 | BATL_GUARDEDSTORAGE) 368 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 369 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 370 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 371 372 /* 373 * BAT5 128K Cacheable, non-guarded 374 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 375 */ 376 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 377 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 378 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 379 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 380 381 /* 382 * BAT6 256M Cache-inhibited, guarded 383 * 0xf000_0000 256M FLASH 384 */ 385 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 386 | BATL_GUARDEDSTORAGE) 387 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 388 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 389 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 390 391 /* Map the last 1M of flash where we're running from reset */ 392 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 393 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 394 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 395 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 396 | BATL_MEMCOHERENCE) 397 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 398 399 /* 400 * BAT7 4M Cache-inhibited, guarded 401 * 0xe800_0000 4M PIXIS 402 */ 403 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 404 | BATL_GUARDEDSTORAGE) 405 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 406 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 407 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 408 409 /* 410 * Environment 411 */ 412 #ifndef CONFIG_SYS_RAMBOOT 413 #define CONFIG_ENV_IS_IN_FLASH 1 414 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 415 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 416 #define CONFIG_ENV_SIZE 0x2000 417 #else 418 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 419 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 420 #define CONFIG_ENV_SIZE 0x2000 421 #endif 422 423 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 424 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 425 426 /* 427 * BOOTP options 428 */ 429 #define CONFIG_BOOTP_BOOTFILESIZE 430 #define CONFIG_BOOTP_BOOTPATH 431 #define CONFIG_BOOTP_GATEWAY 432 #define CONFIG_BOOTP_HOSTNAME 433 434 /* 435 * Command line configuration. 436 */ 437 438 #if defined(CONFIG_PCI) 439 #define CONFIG_CMD_PCI 440 #define CONFIG_SCSI 441 #endif 442 443 #define CONFIG_WATCHDOG /* watchdog enabled */ 444 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 445 446 /* 447 * Miscellaneous configurable options 448 */ 449 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 450 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 451 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 452 453 #if defined(CONFIG_CMD_KGDB) 454 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 455 #else 456 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 457 #endif 458 459 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 460 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 461 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 462 463 /* 464 * For booting Linux, the board info and command line data 465 * have to be in the first 8 MB of memory, since this is 466 * the maximum mapped by the Linux kernel during initialization. 467 */ 468 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 469 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 470 471 #if defined(CONFIG_CMD_KGDB) 472 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 473 #endif 474 475 /* 476 * Environment Configuration 477 */ 478 #define CONFIG_IPADDR 192.168.1.100 479 480 #define CONFIG_HOSTNAME unknown 481 #define CONFIG_ROOTPATH "/opt/nfsroot" 482 #define CONFIG_BOOTFILE "uImage" 483 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 484 485 #define CONFIG_SERVERIP 192.168.1.1 486 #define CONFIG_GATEWAYIP 192.168.1.1 487 #define CONFIG_NETMASK 255.255.255.0 488 489 /* default location for tftp and bootm */ 490 #define CONFIG_LOADADDR 0x10000000 491 492 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 493 494 #define CONFIG_BAUDRATE 115200 495 496 #if defined(CONFIG_PCI1) 497 #define PCI_ENV \ 498 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 499 "echo e;md ${a}e00 9\0" \ 500 "pci1regs=setenv a e0008; run pcireg\0" \ 501 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 502 "pci d.w $b.0 56 1\0" \ 503 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 504 "pci w.w $b.0 56 ffff\0" \ 505 "pci1err=setenv a e0008; run pcierr\0" \ 506 "pci1errc=setenv a e0008; run pcierrc\0" 507 #else 508 #define PCI_ENV "" 509 #endif 510 511 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 512 #define PCIE_ENV \ 513 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 514 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 515 "pcie1regs=setenv a e000a; run pciereg\0" \ 516 "pcie2regs=setenv a e0009; run pciereg\0" \ 517 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 518 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 519 "pci d $b.0 130 1\0" \ 520 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 521 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 522 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 523 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 524 "pcie1err=setenv a e000a; run pcieerr\0" \ 525 "pcie2err=setenv a e0009; run pcieerr\0" \ 526 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 527 "pcie2errc=setenv a e0009; run pcieerrc\0" 528 #else 529 #define PCIE_ENV "" 530 #endif 531 532 #define DMA_ENV \ 533 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 534 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 535 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 536 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 537 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 538 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 539 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 540 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 541 542 #ifdef ENV_DEBUG 543 #define CONFIG_EXTRA_ENV_SETTINGS \ 544 "netdev=eth0\0" \ 545 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 546 "tftpflash=tftpboot $loadaddr $uboot; " \ 547 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 548 " +$filesize; " \ 549 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 550 " +$filesize; " \ 551 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 552 " $filesize; " \ 553 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 554 " +$filesize; " \ 555 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 556 " $filesize\0" \ 557 "consoledev=ttyS0\0" \ 558 "ramdiskaddr=0x18000000\0" \ 559 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 560 "fdtaddr=0x17c00000\0" \ 561 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 562 "bdev=sda3\0" \ 563 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 564 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 565 "maxcpus=1" \ 566 "eoi=mw e00400b0 0\0" \ 567 "iack=md e00400a0 1\0" \ 568 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 569 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 570 "md ${a}f00 5\0" \ 571 "ddr1regs=setenv a e0002; run ddrreg\0" \ 572 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 573 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 574 "md ${a}e60 1; md ${a}ef0 1d\0" \ 575 "guregs=setenv a e00e0; run gureg\0" \ 576 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 577 "mcmregs=setenv a e0001; run mcmreg\0" \ 578 "diuregs=md e002c000 1d\0" \ 579 "dium=mw e002c01c\0" \ 580 "diuerr=md e002c014 1\0" \ 581 "pmregs=md e00e1000 2b\0" \ 582 "lawregs=md e0000c08 4b\0" \ 583 "lbcregs=md e0005000 36\0" \ 584 "dma0regs=md e0021100 12\0" \ 585 "dma1regs=md e0021180 12\0" \ 586 "dma2regs=md e0021200 12\0" \ 587 "dma3regs=md e0021280 12\0" \ 588 PCI_ENV \ 589 PCIE_ENV \ 590 DMA_ENV 591 #else 592 #define CONFIG_EXTRA_ENV_SETTINGS \ 593 "netdev=eth0\0" \ 594 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 595 "consoledev=ttyS0\0" \ 596 "ramdiskaddr=0x18000000\0" \ 597 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 598 "fdtaddr=0x17c00000\0" \ 599 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 600 "bdev=sda3\0" 601 #endif 602 603 #define CONFIG_NFSBOOTCOMMAND \ 604 "setenv bootargs root=/dev/nfs rw " \ 605 "nfsroot=$serverip:$rootpath " \ 606 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 607 "console=$consoledev,$baudrate $othbootargs;" \ 608 "tftp $loadaddr $bootfile;" \ 609 "tftp $fdtaddr $fdtfile;" \ 610 "bootm $loadaddr - $fdtaddr" 611 612 #define CONFIG_RAMBOOTCOMMAND \ 613 "setenv bootargs root=/dev/ram rw " \ 614 "console=$consoledev,$baudrate $othbootargs;" \ 615 "tftp $ramdiskaddr $ramdiskfile;" \ 616 "tftp $loadaddr $bootfile;" \ 617 "tftp $fdtaddr $fdtfile;" \ 618 "bootm $loadaddr $ramdiskaddr $fdtaddr" 619 620 #define CONFIG_BOOTCOMMAND \ 621 "setenv bootargs root=/dev/$bdev rw " \ 622 "console=$consoledev,$baudrate $othbootargs;" \ 623 "tftp $loadaddr $bootfile;" \ 624 "tftp $fdtaddr $fdtfile;" \ 625 "bootm $loadaddr - $fdtaddr" 626 627 #endif /* __CONFIG_H */ 628