1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2007-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * MPC8610HPCD board configuration file 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 15 16 /* video */ 17 #define CONFIG_FSL_DIU_FB 18 19 #ifdef CONFIG_FSL_DIU_FB 20 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 21 #define CONFIG_VIDEO_LOGO 22 #define CONFIG_VIDEO_BMP_LOGO 23 #endif 24 25 #ifdef RUN_DIAG 26 #define CONFIG_SYS_DIAG_ADDR 0xff800000 27 #endif 28 29 /* 30 * virtual address to be used for temporary mappings. There 31 * should be 128k free at this VA. 32 */ 33 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 34 35 #define CONFIG_PCI1 1 /* PCI controller 1 */ 36 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 37 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 38 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 39 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 41 42 #define CONFIG_ENV_OVERWRITE 43 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 44 45 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 46 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 47 #define CONFIG_ALTIVEC 1 48 49 /* 50 * L2CR setup -- make sure this is right for your board! 51 */ 52 #define CONFIG_SYS_L2 53 #define L2_INIT 0 54 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 58 #endif 59 60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 61 #define CONFIG_SYS_MEMTEST_END 0x00400000 62 63 /* 64 * Base addresses -- Note these are effective addresses where the 65 * actual resources get mapped (not physical addresses) 66 */ 67 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 68 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 69 70 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 71 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 72 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 73 74 /* DDR Setup */ 75 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 76 #define CONFIG_DDR_SPD 77 78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 79 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 80 81 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 82 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 83 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 84 #define CONFIG_VERY_BIG_RAM 85 86 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 87 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 88 89 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 90 91 /* These are used when DDR doesn't use SPD. */ 92 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 93 94 #if 0 /* TODO */ 95 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 96 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 97 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 98 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 99 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 100 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 101 #define CONFIG_SYS_DDR_MODE_1 0x00480432 102 #define CONFIG_SYS_DDR_MODE_2 0x00000000 103 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 104 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 105 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 106 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 107 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 108 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 109 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 110 111 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 112 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 113 #define CONFIG_SYS_DDR_SBE 0x000f0000 114 115 #endif 116 117 #define CONFIG_ID_EEPROM 118 #define CONFIG_SYS_I2C_EEPROM_NXID 119 #define CONFIG_ID_EEPROM 120 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 121 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 122 123 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 124 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 125 126 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 127 128 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 129 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 130 131 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 132 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 133 #if 0 /* TODO */ 134 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 135 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 136 #endif 137 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 138 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 139 140 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 141 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 142 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 143 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 144 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 145 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 146 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 147 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 148 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 149 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 150 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 151 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 152 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 153 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 154 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 155 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 156 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 157 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 158 159 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 160 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 161 162 #undef CONFIG_SYS_FLASH_CHECKSUM 163 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 164 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 166 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 167 168 #define CONFIG_SYS_FLASH_EMPTY_INFO 169 170 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 171 #define CONFIG_SYS_RAMBOOT 172 #else 173 #undef CONFIG_SYS_RAMBOOT 174 #endif 175 176 #if defined(CONFIG_SYS_RAMBOOT) 177 #undef CONFIG_SPD_EEPROM 178 #define CONFIG_SYS_SDRAM_SIZE 256 179 #endif 180 181 #undef CONFIG_CLOCKS_IN_MHZ 182 183 #define CONFIG_SYS_INIT_RAM_LOCK 1 184 #ifndef CONFIG_SYS_INIT_RAM_LOCK 185 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 186 #else 187 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 188 #endif 189 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 190 191 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 192 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 193 194 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 195 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 196 197 /* Serial Port */ 198 #define CONFIG_SYS_NS16550_SERIAL 199 #define CONFIG_SYS_NS16550_REG_SIZE 1 200 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 201 202 #define CONFIG_SYS_BAUDRATE_TABLE \ 203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 204 205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 207 208 /* maximum size of the flat tree (8K) */ 209 #define OF_FLAT_TREE_MAX_SIZE 8192 210 211 /* 212 * I2C 213 */ 214 #define CONFIG_SYS_I2C 215 #define CONFIG_SYS_I2C_FSL 216 #define CONFIG_SYS_FSL_I2C_SPEED 400000 217 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 218 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 219 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 220 221 /* 222 * General PCI 223 * Addresses are mapped 1-1. 224 */ 225 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 226 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 227 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 228 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 229 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 230 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 231 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 232 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 233 234 /* controller 1, Base address 0xa000 */ 235 #define CONFIG_SYS_PCIE1_NAME "ULI" 236 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 237 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 238 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 239 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 240 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 241 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 242 243 /* controller 2, Base Address 0x9000 */ 244 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 245 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 246 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 247 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 248 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 249 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 250 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 251 252 #if defined(CONFIG_PCI) 253 254 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 255 256 #define CONFIG_ULI526X 257 258 /************************************************************ 259 * USB support 260 ************************************************************/ 261 #define CONFIG_PCI_OHCI 1 262 #define CONFIG_USB_OHCI_NEW 1 263 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 264 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 265 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 266 267 #if !defined(CONFIG_PCI_PNP) 268 #define PCI_ENET0_IOADDR 0xe0000000 269 #define PCI_ENET0_MEMADDR 0xe0000000 270 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 271 #endif 272 273 #ifdef CONFIG_SCSI_AHCI 274 #define CONFIG_SATA_ULI5288 275 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 276 #define CONFIG_SYS_SCSI_MAX_LUN 1 277 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 278 #endif 279 280 #endif /* CONFIG_PCI */ 281 282 /* 283 * BAT0 2G Cacheable, non-guarded 284 * 0x0000_0000 2G DDR 285 */ 286 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 287 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 288 289 /* 290 * BAT1 1G Cache-inhibited, guarded 291 * 0x8000_0000 256M PCI-1 Memory 292 * 0xa000_0000 256M PCI-Express 1 Memory 293 * 0x9000_0000 256M PCI-Express 2 Memory 294 */ 295 296 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 297 | BATL_GUARDEDSTORAGE) 298 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 299 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 300 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 301 302 /* 303 * BAT2 16M Cache-inhibited, guarded 304 * 0xe100_0000 1M PCI-1 I/O 305 */ 306 307 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 308 | BATL_GUARDEDSTORAGE) 309 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 310 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 311 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 312 313 /* 314 * BAT3 4M Cache-inhibited, guarded 315 * 0xe000_0000 4M CCSR 316 */ 317 318 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 319 | BATL_GUARDEDSTORAGE) 320 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 321 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 322 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 323 324 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 325 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 326 | BATL_PP_RW | BATL_CACHEINHIBIT \ 327 | BATL_GUARDEDSTORAGE) 328 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 329 | BATU_BL_1M | BATU_VS | BATU_VP) 330 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 331 | BATL_PP_RW | BATL_CACHEINHIBIT) 332 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 333 #endif 334 335 /* 336 * BAT4 32M Cache-inhibited, guarded 337 * 0xe200_0000 1M PCI-Express 2 I/O 338 * 0xe300_0000 1M PCI-Express 1 I/O 339 */ 340 341 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 342 | BATL_GUARDEDSTORAGE) 343 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 344 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 345 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 346 347 /* 348 * BAT5 128K Cacheable, non-guarded 349 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 350 */ 351 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 352 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 353 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 354 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 355 356 /* 357 * BAT6 256M Cache-inhibited, guarded 358 * 0xf000_0000 256M FLASH 359 */ 360 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 361 | BATL_GUARDEDSTORAGE) 362 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 363 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 364 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 365 366 /* Map the last 1M of flash where we're running from reset */ 367 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 368 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 369 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 370 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 371 | BATL_MEMCOHERENCE) 372 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 373 374 /* 375 * BAT7 4M Cache-inhibited, guarded 376 * 0xe800_0000 4M PIXIS 377 */ 378 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 379 | BATL_GUARDEDSTORAGE) 380 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 381 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 382 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 383 384 /* 385 * Environment 386 */ 387 #ifndef CONFIG_SYS_RAMBOOT 388 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 389 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 390 #define CONFIG_ENV_SIZE 0x2000 391 #else 392 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 393 #define CONFIG_ENV_SIZE 0x2000 394 #endif 395 396 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 397 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 398 399 /* 400 * BOOTP options 401 */ 402 #define CONFIG_BOOTP_BOOTFILESIZE 403 404 /* 405 * Command line configuration. 406 */ 407 408 #define CONFIG_WATCHDOG /* watchdog enabled */ 409 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 410 411 /* 412 * Miscellaneous configurable options 413 */ 414 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 415 416 /* 417 * For booting Linux, the board info and command line data 418 * have to be in the first 8 MB of memory, since this is 419 * the maximum mapped by the Linux kernel during initialization. 420 */ 421 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 422 #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ 423 424 #if defined(CONFIG_CMD_KGDB) 425 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 426 #endif 427 428 /* 429 * Environment Configuration 430 */ 431 #define CONFIG_IPADDR 192.168.1.100 432 433 #define CONFIG_HOSTNAME "unknown" 434 #define CONFIG_ROOTPATH "/opt/nfsroot" 435 #define CONFIG_BOOTFILE "uImage" 436 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 437 438 #define CONFIG_SERVERIP 192.168.1.1 439 #define CONFIG_GATEWAYIP 192.168.1.1 440 #define CONFIG_NETMASK 255.255.255.0 441 442 /* default location for tftp and bootm */ 443 #define CONFIG_LOADADDR 0x10000000 444 445 #if defined(CONFIG_PCI1) 446 #define PCI_ENV \ 447 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 448 "echo e;md ${a}e00 9\0" \ 449 "pci1regs=setenv a e0008; run pcireg\0" \ 450 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 451 "pci d.w $b.0 56 1\0" \ 452 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 453 "pci w.w $b.0 56 ffff\0" \ 454 "pci1err=setenv a e0008; run pcierr\0" \ 455 "pci1errc=setenv a e0008; run pcierrc\0" 456 #else 457 #define PCI_ENV "" 458 #endif 459 460 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 461 #define PCIE_ENV \ 462 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 463 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 464 "pcie1regs=setenv a e000a; run pciereg\0" \ 465 "pcie2regs=setenv a e0009; run pciereg\0" \ 466 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 467 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 468 "pci d $b.0 130 1\0" \ 469 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 470 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 471 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 472 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 473 "pcie1err=setenv a e000a; run pcieerr\0" \ 474 "pcie2err=setenv a e0009; run pcieerr\0" \ 475 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 476 "pcie2errc=setenv a e0009; run pcieerrc\0" 477 #else 478 #define PCIE_ENV "" 479 #endif 480 481 #define DMA_ENV \ 482 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 483 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 484 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 485 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 486 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 487 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 488 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 489 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 490 491 #ifdef ENV_DEBUG 492 #define CONFIG_EXTRA_ENV_SETTINGS \ 493 "netdev=eth0\0" \ 494 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 495 "tftpflash=tftpboot $loadaddr $uboot; " \ 496 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 497 " +$filesize; " \ 498 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 499 " +$filesize; " \ 500 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 501 " $filesize; " \ 502 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 503 " +$filesize; " \ 504 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 505 " $filesize\0" \ 506 "consoledev=ttyS0\0" \ 507 "ramdiskaddr=0x18000000\0" \ 508 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 509 "fdtaddr=0x17c00000\0" \ 510 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 511 "bdev=sda3\0" \ 512 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 513 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 514 "maxcpus=1" \ 515 "eoi=mw e00400b0 0\0" \ 516 "iack=md e00400a0 1\0" \ 517 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 518 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 519 "md ${a}f00 5\0" \ 520 "ddr1regs=setenv a e0002; run ddrreg\0" \ 521 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 522 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 523 "md ${a}e60 1; md ${a}ef0 1d\0" \ 524 "guregs=setenv a e00e0; run gureg\0" \ 525 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 526 "mcmregs=setenv a e0001; run mcmreg\0" \ 527 "diuregs=md e002c000 1d\0" \ 528 "dium=mw e002c01c\0" \ 529 "diuerr=md e002c014 1\0" \ 530 "pmregs=md e00e1000 2b\0" \ 531 "lawregs=md e0000c08 4b\0" \ 532 "lbcregs=md e0005000 36\0" \ 533 "dma0regs=md e0021100 12\0" \ 534 "dma1regs=md e0021180 12\0" \ 535 "dma2regs=md e0021200 12\0" \ 536 "dma3regs=md e0021280 12\0" \ 537 PCI_ENV \ 538 PCIE_ENV \ 539 DMA_ENV 540 #else 541 #define CONFIG_EXTRA_ENV_SETTINGS \ 542 "netdev=eth0\0" \ 543 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 544 "consoledev=ttyS0\0" \ 545 "ramdiskaddr=0x18000000\0" \ 546 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 547 "fdtaddr=0x17c00000\0" \ 548 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 549 "bdev=sda3\0" 550 #endif 551 552 #define CONFIG_NFSBOOTCOMMAND \ 553 "setenv bootargs root=/dev/nfs rw " \ 554 "nfsroot=$serverip:$rootpath " \ 555 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 556 "console=$consoledev,$baudrate $othbootargs;" \ 557 "tftp $loadaddr $bootfile;" \ 558 "tftp $fdtaddr $fdtfile;" \ 559 "bootm $loadaddr - $fdtaddr" 560 561 #define CONFIG_RAMBOOTCOMMAND \ 562 "setenv bootargs root=/dev/ram rw " \ 563 "console=$consoledev,$baudrate $othbootargs;" \ 564 "tftp $ramdiskaddr $ramdiskfile;" \ 565 "tftp $loadaddr $bootfile;" \ 566 "tftp $fdtaddr $fdtfile;" \ 567 "bootm $loadaddr $ramdiskaddr $fdtaddr" 568 569 #define CONFIG_BOOTCOMMAND \ 570 "setenv bootargs root=/dev/$bdev rw " \ 571 "console=$consoledev,$baudrate $othbootargs;" \ 572 "tftp $loadaddr $bootfile;" \ 573 "tftp $fdtaddr $fdtfile;" \ 574 "bootm $loadaddr - $fdtaddr" 575 576 #endif /* __CONFIG_H */ 577