1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 * 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* High Level Configuration Options */ 18 #define CONFIG_MPC86xx 1 /* MPC86xx */ 19 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 20 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 21 #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ 22 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 23 24 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 25 26 /* video */ 27 #undef CONFIG_VIDEO 28 29 #if defined(CONFIG_VIDEO) 30 #define CONFIG_CFB_CONSOLE 31 #define CONFIG_VGA_AS_SINGLE_DEVICE 32 #endif 33 34 #ifdef RUN_DIAG 35 #define CFG_DIAG_ADDR 0xff800000 36 #endif 37 38 #define CFG_RESET_ADDRESS 0xfff00100 39 40 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 41 #define CONFIG_PCI1 1 /* PCI controler 1 */ 42 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 43 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_ENV_OVERWRITE 48 49 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 50 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 51 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 52 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 54 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 55 #define CONFIG_NUM_DDR_CONTROLLERS 1 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 58 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 59 #define CONFIG_ALTIVEC 1 60 61 /* 62 * L2CR setup -- make sure this is right for your board! 63 */ 64 #define CFG_L2 65 #define L2_INIT 0 66 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 67 68 #ifndef CONFIG_SYS_CLK_FREQ 69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 70 #endif 71 72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 73 #define CONFIG_MISC_INIT_R 1 74 75 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 76 #define CFG_MEMTEST_END 0x00400000 77 78 /* 79 * Base addresses -- Note these are effective addresses where the 80 * actual resources get mapped (not physical addresses) 81 */ 82 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 83 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 84 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 85 86 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 87 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 88 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 89 90 #define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000) 91 92 /* 93 * DDR Setup 94 */ 95 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 96 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 97 #define CONFIG_VERY_BIG_RAM 98 99 #define MPC86xx_DDR_SDRAM_CLK_CNTL 100 101 #if defined(CONFIG_SPD_EEPROM) 102 /* 103 * Determine DDR configuration from I2C interface. 104 */ 105 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 106 #else 107 /* 108 * Manually set up DDR1 parameters 109 */ 110 111 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 112 113 #if 0 /* TODO */ 114 #define CFG_DDR_CS0_BNDS 0x0000000F 115 #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 116 #define CFG_DDR_TIMING_3 0x00000000 117 #define CFG_DDR_TIMING_0 0x00260802 118 #define CFG_DDR_TIMING_1 0x3935d322 119 #define CFG_DDR_TIMING_2 0x14904cc8 120 #define CFG_DDR_MODE_1 0x00480432 121 #define CFG_DDR_MODE_2 0x00000000 122 #define CFG_DDR_INTERVAL 0x06180100 123 #define CFG_DDR_DATA_INIT 0xdeadbeef 124 #define CFG_DDR_CLK_CTRL 0x03800000 125 #define CFG_DDR_OCD_CTRL 0x00000000 126 #define CFG_DDR_OCD_STATUS 0x00000000 127 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 128 #define CFG_DDR_CONTROL2 0x04400010 129 130 #define CFG_DDR_ERR_INT_EN 0x00000000 131 #define CFG_DDR_ERR_DIS 0x00000000 132 #define CFG_DDR_SBE 0x000f0000 133 /* Not used in fixed_sdram function */ 134 #define CFG_DDR_MODE 0x00000022 135 #define CFG_DDR_CS1_BNDS 0x00000000 136 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 137 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 138 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 139 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 140 #endif 141 #endif 142 143 #define CFG_ID_EEPROM 144 #ifdef CFG_ID_EEPROM 145 #define CONFIG_ID_EEPROM 146 #endif 147 #define ID_EEPROM_ADDR 0x57 148 149 150 #define CFG_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 151 #define CFG_FLASH_BASE2 0xf8000000 152 153 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 154 155 #define CFG_BR0_PRELIM 0xf8001001 /* port size 16bit */ 156 #define CFG_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 157 158 #define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ 159 #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 160 #if 0 /* TODO */ 161 #define CFG_BR2_PRELIM 0xf0000000 162 #define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 163 #endif 164 #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ 165 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 166 167 168 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 169 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 170 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 171 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 172 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 173 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 174 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 175 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 176 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 177 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 178 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 179 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 180 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 181 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 182 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 183 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 184 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 185 #define CFG_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ 186 187 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 188 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ 189 190 #undef CFG_FLASH_CHECKSUM 191 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 192 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 193 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 194 195 #define CFG_FLASH_CFI_DRIVER 196 #define CFG_FLASH_CFI 197 #define CFG_FLASH_EMPTY_INFO 198 199 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 200 #define CFG_RAMBOOT 201 #else 202 #undef CFG_RAMBOOT 203 #endif 204 205 #if defined(CFG_RAMBOOT) 206 #undef CONFIG_SPD_EEPROM 207 #define CFG_SDRAM_SIZE 256 208 #endif 209 210 #undef CONFIG_CLOCKS_IN_MHZ 211 212 #define CONFIG_L1_INIT_RAM 213 #define CFG_INIT_RAM_LOCK 1 214 #ifndef CFG_INIT_RAM_LOCK 215 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 216 #else 217 #define CFG_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 218 #endif 219 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 220 221 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 222 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 223 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 224 225 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 226 #define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 227 228 /* Serial Port */ 229 #define CONFIG_CONS_INDEX 1 230 #undef CONFIG_SERIAL_SOFTWARE_FIFO 231 #define CFG_NS16550 232 #define CFG_NS16550_SERIAL 233 #define CFG_NS16550_REG_SIZE 1 234 #define CFG_NS16550_CLK get_bus_freq(0) 235 236 #define CFG_BAUDRATE_TABLE \ 237 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 238 239 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 240 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 241 242 /* Use the HUSH parser */ 243 #define CFG_HUSH_PARSER 244 #ifdef CFG_HUSH_PARSER 245 #define CFG_PROMPT_HUSH_PS2 "> " 246 #endif 247 248 /* 249 * Pass open firmware flat tree to kernel 250 */ 251 #define CONFIG_OF_LIBFDT 1 252 #define CONFIG_OF_BOARD_SETUP 1 253 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 254 255 256 /* maximum size of the flat tree (8K) */ 257 #define OF_FLAT_TREE_MAX_SIZE 8192 258 259 #define CFG_64BIT_VSPRINTF 1 260 #define CFG_64BIT_STRTOUL 1 261 262 /* 263 * I2C 264 */ 265 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 266 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 267 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 268 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 269 #define CFG_I2C_SLAVE 0x7F 270 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 271 #define CFG_I2C_OFFSET 0x3000 272 273 /* 274 * General PCI 275 * Addresses are mapped 1-1. 276 */ 277 #define CFG_PCI1_MEM_BASE 0x80000000 278 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 279 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 280 #define CFG_PCI1_IO_BASE 0x00000000 281 #define CFG_PCI1_IO_PHYS 0xe1000000 282 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 283 284 /* PCI view of System Memory */ 285 #define CFG_PCI_MEMORY_BUS 0x00000000 286 #define CFG_PCI_MEMORY_PHYS 0x00000000 287 #define CFG_PCI_MEMORY_SIZE 0x80000000 288 289 /* For RTL8139 */ 290 #define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) 291 #define _IO_BASE 0x00000000 292 293 /* controller 1, Base address 0xa000 */ 294 #define CFG_PCIE1_MEM_BASE 0xa0000000 295 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 296 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 297 #define CFG_PCIE1_IO_BASE 0x00000000 298 #define CFG_PCIE1_IO_PHYS 0xe3000000 299 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ 300 301 /* controller 2, Base Address 0x9000 */ 302 #define CFG_PCIE2_MEM_BASE 0x90000000 303 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 304 #define CFG_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 305 #define CFG_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ 306 #define CFG_PCIE2_IO_PHYS 0xe2000000 307 #define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ 308 309 310 #if defined(CONFIG_PCI) 311 312 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 313 314 #define CONFIG_NET_MULTI 315 #define CONFIG_CMD_NET 316 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 317 #define CONFIG_CMD_REGINFO 318 319 #define CONFIG_ULI526X 320 #ifdef CONFIG_ULI526X 321 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 322 #endif 323 324 /************************************************************ 325 * USB support 326 ************************************************************/ 327 #define CONFIG_PCI_OHCI 1 328 #define CONFIG_USB_OHCI_NEW 1 329 #define CONFIG_USB_KEYBOARD 1 330 #define CFG_DEVICE_DEREGISTER 331 #define CFG_USB_EVENT_POLL 1 332 #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" 333 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 334 #define CFG_OHCI_SWAP_REG_ACCESS 1 335 336 #if !defined(CONFIG_PCI_PNP) 337 #define PCI_ENET0_IOADDR 0xe0000000 338 #define PCI_ENET0_MEMADDR 0xe0000000 339 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 340 #endif 341 342 #define CONFIG_DOS_PARTITION 343 #define CONFIG_SCSI_AHCI 344 345 #ifdef CONFIG_SCSI_AHCI 346 #define CONFIG_SATA_ULI5288 347 #define CFG_SCSI_MAX_SCSI_ID 4 348 #define CFG_SCSI_MAX_LUN 1 349 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 350 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 351 #endif 352 353 #endif /* CONFIG_PCI */ 354 355 /* 356 * BAT0 2G Cacheable, non-guarded 357 * 0x0000_0000 2G DDR 358 */ 359 #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 360 #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 361 #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 362 #define CFG_IBAT0U CFG_DBAT0U 363 364 /* 365 * BAT1 1G Cache-inhibited, guarded 366 * 0x8000_0000 256M PCI-1 Memory 367 * 0xa000_0000 256M PCI-Express 1 Memory 368 * 0x9000_0000 256M PCI-Express 2 Memory 369 */ 370 371 #define CFG_DBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 372 | BATL_GUARDEDSTORAGE) 373 #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) 374 #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 375 #define CFG_IBAT1U CFG_DBAT1U 376 377 /* 378 * BAT2 16M Cache-inhibited, guarded 379 * 0xe100_0000 1M PCI-1 I/O 380 */ 381 382 #define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 383 | BATL_GUARDEDSTORAGE) 384 #define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP) 385 #define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 386 #define CFG_IBAT2U CFG_DBAT2U 387 388 /* 389 * BAT3 32M Cache-inhibited, guarded 390 * 0xe200_0000 1M PCI-Express 2 I/O 391 * 0xe300_0000 1M PCI-Express 1 I/O 392 */ 393 394 #define CFG_DBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 395 | BATL_GUARDEDSTORAGE) 396 #define CFG_DBAT3U (CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 397 #define CFG_IBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 398 #define CFG_IBAT3U CFG_DBAT3U 399 400 /* 401 * BAT4 4M Cache-inhibited, guarded 402 * 0xe000_0000 4M CCSR 403 */ 404 #define CFG_DBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 405 | BATL_GUARDEDSTORAGE) 406 #define CFG_DBAT4U (CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 407 #define CFG_IBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 408 #define CFG_IBAT4U CFG_DBAT4U 409 410 /* 411 * BAT5 128K Cacheable, non-guarded 412 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 413 */ 414 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 415 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 416 #define CFG_IBAT5L CFG_DBAT5L 417 #define CFG_IBAT5U CFG_DBAT5U 418 419 /* 420 * BAT6 256M Cache-inhibited, guarded 421 * 0xf000_0000 256M FLASH 422 */ 423 #define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 424 | BATL_GUARDEDSTORAGE) 425 #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 426 #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 427 #define CFG_IBAT6U CFG_DBAT6U 428 429 /* 430 * BAT7 4M Cache-inhibited, guarded 431 * 0xe800_0000 4M PIXIS 432 */ 433 #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 434 | BATL_GUARDEDSTORAGE) 435 #define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 436 #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 437 #define CFG_IBAT7U CFG_DBAT7U 438 439 440 /* 441 * Environment 442 */ 443 #ifndef CFG_RAMBOOT 444 #define CFG_ENV_IS_IN_FLASH 1 445 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 446 #define CFG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 447 #define CFG_ENV_SIZE 0x2000 448 #else 449 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 450 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 451 #define CFG_ENV_SIZE 0x2000 452 #endif 453 454 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 455 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 456 457 458 /* 459 * BOOTP options 460 */ 461 #define CONFIG_BOOTP_BOOTFILESIZE 462 #define CONFIG_BOOTP_BOOTPATH 463 #define CONFIG_BOOTP_GATEWAY 464 #define CONFIG_BOOTP_HOSTNAME 465 466 467 /* 468 * Command line configuration. 469 */ 470 #include <config_cmd_default.h> 471 472 #define CONFIG_CMD_PING 473 #define CONFIG_CMD_I2C 474 #define CONFIG_CMD_MII 475 476 #if defined(CFG_RAMBOOT) 477 #undef CONFIG_CMD_ENV 478 #endif 479 480 #if defined(CONFIG_PCI) 481 #define CONFIG_CMD_PCI 482 #define CONFIG_CMD_SCSI 483 #define CONFIG_CMD_EXT2 484 #define CONFIG_CMD_USB 485 #endif 486 487 488 #undef CONFIG_WATCHDOG /* watchdog disabled */ 489 490 /*DIU Configuration*/ 491 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 492 493 /* 494 * Miscellaneous configurable options 495 */ 496 #define CFG_LONGHELP /* undef to save memory */ 497 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 498 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 499 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 500 501 #if defined(CONFIG_CMD_KGDB) 502 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 503 #else 504 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 505 #endif 506 507 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 508 #define CFG_MAXARGS 16 /* max number of command args */ 509 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 510 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 511 512 /* 513 * For booting Linux, the board info and command line data 514 * have to be in the first 8 MB of memory, since this is 515 * the maximum mapped by the Linux kernel during initialization. 516 */ 517 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 518 519 /* 520 * Internal Definitions 521 * 522 * Boot Flags 523 */ 524 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 525 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 526 527 #if defined(CONFIG_CMD_KGDB) 528 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 529 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 530 #endif 531 532 /* 533 * Environment Configuration 534 */ 535 #define CONFIG_IPADDR 192.168.1.100 536 537 #define CONFIG_HOSTNAME unknown 538 #define CONFIG_ROOTPATH /opt/nfsroot 539 #define CONFIG_BOOTFILE uImage 540 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 541 542 #define CONFIG_SERVERIP 192.168.1.1 543 #define CONFIG_GATEWAYIP 192.168.1.1 544 #define CONFIG_NETMASK 255.255.255.0 545 546 /* default location for tftp and bootm */ 547 #define CONFIG_LOADADDR 1000000 548 549 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 550 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 551 552 #define CONFIG_BAUDRATE 115200 553 554 #if defined(CONFIG_PCI1) 555 #define PCI_ENV \ 556 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 557 "echo e;md ${a}e00 9\0" \ 558 "pci1regs=setenv a e0008; run pcireg\0" \ 559 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 560 "pci d.w $b.0 56 1\0" \ 561 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 562 "pci w.w $b.0 56 ffff\0" \ 563 "pci1err=setenv a e0008; run pcierr\0" \ 564 "pci1errc=setenv a e0008; run pcierrc\0" 565 #else 566 #define PCI_ENV "" 567 #endif 568 569 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 570 #define PCIE_ENV \ 571 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 572 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 573 "pcie1regs=setenv a e000a; run pciereg\0" \ 574 "pcie2regs=setenv a e0009; run pciereg\0" \ 575 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 576 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 577 "pci d $b.0 130 1\0" \ 578 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 579 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 580 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 581 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 582 "pcie1err=setenv a e000a; run pcieerr\0" \ 583 "pcie2err=setenv a e0009; run pcieerr\0" \ 584 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 585 "pcie2errc=setenv a e0009; run pcieerrc\0" 586 #else 587 #define PCIE_ENV "" 588 #endif 589 590 #define DMA_ENV \ 591 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 592 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 593 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 594 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 595 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 596 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 597 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 598 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 599 600 #ifdef ENV_DEBUG 601 #define CONFIG_EXTRA_ENV_SETTINGS \ 602 "netdev=eth0\0" \ 603 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 604 "tftpflash=tftpboot $loadaddr $uboot; " \ 605 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 606 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 607 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 608 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 609 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 610 "consoledev=ttyS0\0" \ 611 "ramdiskaddr=2000000\0" \ 612 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 613 "fdtaddr=c00000\0" \ 614 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 615 "bdev=sda3\0" \ 616 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 617 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 618 "maxcpus=1" \ 619 "eoi=mw e00400b0 0\0" \ 620 "iack=md e00400a0 1\0" \ 621 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 622 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 623 "md ${a}f00 5\0" \ 624 "ddr1regs=setenv a e0002; run ddrreg\0" \ 625 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 626 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 627 "md ${a}e60 1; md ${a}ef0 1d\0" \ 628 "guregs=setenv a e00e0; run gureg\0" \ 629 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 630 "mcmregs=setenv a e0001; run mcmreg\0" \ 631 "diuregs=md e002c000 1d\0" \ 632 "dium=mw e002c01c\0" \ 633 "diuerr=md e002c014 1\0" \ 634 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 635 "monitor=0-DVI\0" \ 636 "pmregs=md e00e1000 2b\0" \ 637 "lawregs=md e0000c08 4b\0" \ 638 "lbcregs=md e0005000 36\0" \ 639 "dma0regs=md e0021100 12\0" \ 640 "dma1regs=md e0021180 12\0" \ 641 "dma2regs=md e0021200 12\0" \ 642 "dma3regs=md e0021280 12\0" \ 643 PCI_ENV \ 644 PCIE_ENV \ 645 DMA_ENV 646 #else 647 #define CONFIG_EXTRA_ENV_SETTINGS \ 648 "netdev=eth0\0" \ 649 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 650 "consoledev=ttyS0\0" \ 651 "ramdiskaddr=2000000\0" \ 652 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 653 "fdtaddr=c00000\0" \ 654 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 655 "bdev=sda3\0" \ 656 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 657 "monitor=0-DVI\0" 658 #endif 659 660 #define CONFIG_NFSBOOTCOMMAND \ 661 "setenv bootargs root=/dev/nfs rw " \ 662 "nfsroot=$serverip:$rootpath " \ 663 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 664 "console=$consoledev,$baudrate $othbootargs;" \ 665 "tftp $loadaddr $bootfile;" \ 666 "tftp $fdtaddr $fdtfile;" \ 667 "bootm $loadaddr - $fdtaddr" 668 669 #define CONFIG_RAMBOOTCOMMAND \ 670 "setenv bootargs root=/dev/ram rw " \ 671 "console=$consoledev,$baudrate $othbootargs;" \ 672 "tftp $ramdiskaddr $ramdiskfile;" \ 673 "tftp $loadaddr $bootfile;" \ 674 "tftp $fdtaddr $fdtfile;" \ 675 "bootm $loadaddr $ramdiskaddr $fdtaddr" 676 677 #define CONFIG_BOOTCOMMAND \ 678 "setenv bootargs root=/dev/$bdev rw " \ 679 "console=$consoledev,$baudrate $othbootargs;" \ 680 "tftp $loadaddr $bootfile;" \ 681 "tftp $fdtaddr $fdtfile;" \ 682 "bootm $loadaddr - $fdtaddr" 683 684 #endif /* __CONFIG_H */ 685