1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* High Level Configuration Options */ 17 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 18 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xfff00000 22 23 24 /* video */ 25 #define CONFIG_FSL_DIU_FB 26 27 #ifdef CONFIG_FSL_DIU_FB 28 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 29 #define CONFIG_VIDEO 30 #define CONFIG_CMD_BMP 31 #define CONFIG_CFB_CONSOLE 32 #define CONFIG_VIDEO_SW_CURSOR 33 #define CONFIG_VGA_AS_SINGLE_DEVICE 34 #define CONFIG_VIDEO_LOGO 35 #define CONFIG_VIDEO_BMP_LOGO 36 #endif 37 38 #ifdef RUN_DIAG 39 #define CONFIG_SYS_DIAG_ADDR 0xff800000 40 #endif 41 42 /* 43 * virtual address to be used for temporary mappings. There 44 * should be 128k free at this VA. 45 */ 46 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 47 48 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 49 #define CONFIG_PCI1 1 /* PCI controler 1 */ 50 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 51 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 52 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 53 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 54 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 55 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 56 57 #define CONFIG_ENV_OVERWRITE 58 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 59 60 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 61 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 62 #define CONFIG_ALTIVEC 1 63 64 /* 65 * L2CR setup -- make sure this is right for your board! 66 */ 67 #define CONFIG_SYS_L2 68 #define L2_INIT 0 69 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 70 71 #ifndef CONFIG_SYS_CLK_FREQ 72 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 73 #endif 74 75 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 76 #define CONFIG_MISC_INIT_R 1 77 78 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 79 #define CONFIG_SYS_MEMTEST_END 0x00400000 80 81 /* 82 * Base addresses -- Note these are effective addresses where the 83 * actual resources get mapped (not physical addresses) 84 */ 85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 87 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 88 89 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 90 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 91 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 92 93 /* DDR Setup */ 94 #define CONFIG_SYS_FSL_DDR2 95 #undef CONFIG_FSL_DDR_INTERACTIVE 96 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 97 #define CONFIG_DDR_SPD 98 99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 100 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 101 102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 104 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 105 #define CONFIG_VERY_BIG_RAM 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 110 111 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 112 113 /* These are used when DDR doesn't use SPD. */ 114 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 115 116 #if 0 /* TODO */ 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 122 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 123 #define CONFIG_SYS_DDR_MODE_1 0x00480432 124 #define CONFIG_SYS_DDR_MODE_2 0x00000000 125 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x000f0000 136 137 #endif 138 139 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_NXID 142 #define CONFIG_ID_EEPROM 143 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 145 146 147 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 148 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 149 150 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 151 152 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 153 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 154 155 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 156 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 157 #if 0 /* TODO */ 158 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 159 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 160 #endif 161 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 162 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 163 164 165 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 166 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 167 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 168 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 169 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 170 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 171 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 172 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 173 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 174 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 175 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 176 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 177 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 178 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 179 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 180 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 181 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 182 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 183 184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 186 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 191 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 197 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 198 #define CONFIG_SYS_RAMBOOT 199 #else 200 #undef CONFIG_SYS_RAMBOOT 201 #endif 202 203 #if defined(CONFIG_SYS_RAMBOOT) 204 #undef CONFIG_SPD_EEPROM 205 #define CONFIG_SYS_SDRAM_SIZE 256 206 #endif 207 208 #undef CONFIG_CLOCKS_IN_MHZ 209 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #ifndef CONFIG_SYS_INIT_RAM_LOCK 212 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 213 #else 214 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 215 #endif 216 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 217 218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 219 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 220 221 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 222 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 223 224 /* Serial Port */ 225 #define CONFIG_CONS_INDEX 1 226 #define CONFIG_SYS_NS16550 227 #define CONFIG_SYS_NS16550_SERIAL 228 #define CONFIG_SYS_NS16550_REG_SIZE 1 229 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 230 231 #define CONFIG_SYS_BAUDRATE_TABLE \ 232 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 233 234 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 235 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 236 237 /* Use the HUSH parser */ 238 #define CONFIG_SYS_HUSH_PARSER 239 240 /* 241 * Pass open firmware flat tree to kernel 242 */ 243 #define CONFIG_OF_LIBFDT 1 244 #define CONFIG_OF_BOARD_SETUP 1 245 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 246 247 248 /* maximum size of the flat tree (8K) */ 249 #define OF_FLAT_TREE_MAX_SIZE 8192 250 251 /* 252 * I2C 253 */ 254 #define CONFIG_SYS_I2C 255 #define CONFIG_SYS_I2C_FSL 256 #define CONFIG_SYS_FSL_I2C_SPEED 400000 257 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 258 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 259 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 260 261 /* 262 * General PCI 263 * Addresses are mapped 1-1. 264 */ 265 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 266 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 267 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 268 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 269 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 270 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 271 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 272 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 273 274 /* controller 1, Base address 0xa000 */ 275 #define CONFIG_SYS_PCIE1_NAME "ULI" 276 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 277 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 278 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 279 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 280 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 281 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 282 283 /* controller 2, Base Address 0x9000 */ 284 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 285 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 286 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 287 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 288 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 289 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 290 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 291 292 293 #if defined(CONFIG_PCI) 294 295 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 296 297 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 298 #define CONFIG_CMD_REGINFO 299 300 #define CONFIG_ULI526X 301 #ifdef CONFIG_ULI526X 302 #endif 303 304 /************************************************************ 305 * USB support 306 ************************************************************/ 307 #define CONFIG_PCI_OHCI 1 308 #define CONFIG_USB_OHCI_NEW 1 309 #define CONFIG_USB_KEYBOARD 1 310 #define CONFIG_SYS_STDIO_DEREGISTER 311 #define CONFIG_SYS_USB_EVENT_POLL 1 312 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 313 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 314 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 315 316 #if !defined(CONFIG_PCI_PNP) 317 #define PCI_ENET0_IOADDR 0xe0000000 318 #define PCI_ENET0_MEMADDR 0xe0000000 319 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 320 #endif 321 322 #define CONFIG_DOS_PARTITION 323 #define CONFIG_SCSI_AHCI 324 325 #ifdef CONFIG_SCSI_AHCI 326 #define CONFIG_LIBATA 327 #define CONFIG_SATA_ULI5288 328 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 329 #define CONFIG_SYS_SCSI_MAX_LUN 1 330 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 331 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 332 #endif 333 334 #endif /* CONFIG_PCI */ 335 336 /* 337 * BAT0 2G Cacheable, non-guarded 338 * 0x0000_0000 2G DDR 339 */ 340 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 341 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 342 343 /* 344 * BAT1 1G Cache-inhibited, guarded 345 * 0x8000_0000 256M PCI-1 Memory 346 * 0xa000_0000 256M PCI-Express 1 Memory 347 * 0x9000_0000 256M PCI-Express 2 Memory 348 */ 349 350 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 351 | BATL_GUARDEDSTORAGE) 352 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 353 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 354 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 355 356 /* 357 * BAT2 16M Cache-inhibited, guarded 358 * 0xe100_0000 1M PCI-1 I/O 359 */ 360 361 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 362 | BATL_GUARDEDSTORAGE) 363 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 364 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 365 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 366 367 /* 368 * BAT3 4M Cache-inhibited, guarded 369 * 0xe000_0000 4M CCSR 370 */ 371 372 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 373 | BATL_GUARDEDSTORAGE) 374 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 375 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 376 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 377 378 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 379 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 380 | BATL_PP_RW | BATL_CACHEINHIBIT \ 381 | BATL_GUARDEDSTORAGE) 382 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 383 | BATU_BL_1M | BATU_VS | BATU_VP) 384 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 385 | BATL_PP_RW | BATL_CACHEINHIBIT) 386 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 387 #endif 388 389 /* 390 * BAT4 32M Cache-inhibited, guarded 391 * 0xe200_0000 1M PCI-Express 2 I/O 392 * 0xe300_0000 1M PCI-Express 1 I/O 393 */ 394 395 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 396 | BATL_GUARDEDSTORAGE) 397 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 398 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 399 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 400 401 402 /* 403 * BAT5 128K Cacheable, non-guarded 404 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 405 */ 406 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 407 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 408 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 409 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 410 411 /* 412 * BAT6 256M Cache-inhibited, guarded 413 * 0xf000_0000 256M FLASH 414 */ 415 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 416 | BATL_GUARDEDSTORAGE) 417 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 418 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 419 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 420 421 /* Map the last 1M of flash where we're running from reset */ 422 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 423 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 424 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 425 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 426 | BATL_MEMCOHERENCE) 427 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 428 429 /* 430 * BAT7 4M Cache-inhibited, guarded 431 * 0xe800_0000 4M PIXIS 432 */ 433 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 434 | BATL_GUARDEDSTORAGE) 435 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 436 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 437 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 438 439 440 /* 441 * Environment 442 */ 443 #ifndef CONFIG_SYS_RAMBOOT 444 #define CONFIG_ENV_IS_IN_FLASH 1 445 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 446 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 447 #define CONFIG_ENV_SIZE 0x2000 448 #else 449 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 450 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 451 #define CONFIG_ENV_SIZE 0x2000 452 #endif 453 454 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 455 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 456 457 458 /* 459 * BOOTP options 460 */ 461 #define CONFIG_BOOTP_BOOTFILESIZE 462 #define CONFIG_BOOTP_BOOTPATH 463 #define CONFIG_BOOTP_GATEWAY 464 #define CONFIG_BOOTP_HOSTNAME 465 466 467 /* 468 * Command line configuration. 469 */ 470 #define CONFIG_CMD_PING 471 #define CONFIG_CMD_I2C 472 #define CONFIG_CMD_MII 473 474 #if defined(CONFIG_PCI) 475 #define CONFIG_CMD_PCI 476 #define CONFIG_CMD_SCSI 477 #define CONFIG_CMD_EXT2 478 #define CONFIG_CMD_USB 479 #endif 480 481 482 #define CONFIG_WATCHDOG /* watchdog enabled */ 483 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 484 485 /* 486 * Miscellaneous configurable options 487 */ 488 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 489 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 490 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 491 492 #if defined(CONFIG_CMD_KGDB) 493 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 494 #else 495 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 496 #endif 497 498 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 499 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 500 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 501 502 /* 503 * For booting Linux, the board info and command line data 504 * have to be in the first 8 MB of memory, since this is 505 * the maximum mapped by the Linux kernel during initialization. 506 */ 507 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 508 509 #if defined(CONFIG_CMD_KGDB) 510 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 511 #endif 512 513 /* 514 * Environment Configuration 515 */ 516 #define CONFIG_IPADDR 192.168.1.100 517 518 #define CONFIG_HOSTNAME unknown 519 #define CONFIG_ROOTPATH "/opt/nfsroot" 520 #define CONFIG_BOOTFILE "uImage" 521 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 522 523 #define CONFIG_SERVERIP 192.168.1.1 524 #define CONFIG_GATEWAYIP 192.168.1.1 525 #define CONFIG_NETMASK 255.255.255.0 526 527 /* default location for tftp and bootm */ 528 #define CONFIG_LOADADDR 1000000 529 530 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 531 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 532 533 #define CONFIG_BAUDRATE 115200 534 535 #if defined(CONFIG_PCI1) 536 #define PCI_ENV \ 537 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 538 "echo e;md ${a}e00 9\0" \ 539 "pci1regs=setenv a e0008; run pcireg\0" \ 540 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 541 "pci d.w $b.0 56 1\0" \ 542 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 543 "pci w.w $b.0 56 ffff\0" \ 544 "pci1err=setenv a e0008; run pcierr\0" \ 545 "pci1errc=setenv a e0008; run pcierrc\0" 546 #else 547 #define PCI_ENV "" 548 #endif 549 550 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 551 #define PCIE_ENV \ 552 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 553 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 554 "pcie1regs=setenv a e000a; run pciereg\0" \ 555 "pcie2regs=setenv a e0009; run pciereg\0" \ 556 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 557 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 558 "pci d $b.0 130 1\0" \ 559 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 560 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 561 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 562 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 563 "pcie1err=setenv a e000a; run pcieerr\0" \ 564 "pcie2err=setenv a e0009; run pcieerr\0" \ 565 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 566 "pcie2errc=setenv a e0009; run pcieerrc\0" 567 #else 568 #define PCIE_ENV "" 569 #endif 570 571 #define DMA_ENV \ 572 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 573 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 574 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 575 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 576 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 577 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 578 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 579 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 580 581 #ifdef ENV_DEBUG 582 #define CONFIG_EXTRA_ENV_SETTINGS \ 583 "netdev=eth0\0" \ 584 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 585 "tftpflash=tftpboot $loadaddr $uboot; " \ 586 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 587 " +$filesize; " \ 588 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 589 " +$filesize; " \ 590 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 591 " $filesize; " \ 592 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 593 " +$filesize; " \ 594 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 595 " $filesize\0" \ 596 "consoledev=ttyS0\0" \ 597 "ramdiskaddr=2000000\0" \ 598 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 599 "fdtaddr=c00000\0" \ 600 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 601 "bdev=sda3\0" \ 602 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 603 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 604 "maxcpus=1" \ 605 "eoi=mw e00400b0 0\0" \ 606 "iack=md e00400a0 1\0" \ 607 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 608 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 609 "md ${a}f00 5\0" \ 610 "ddr1regs=setenv a e0002; run ddrreg\0" \ 611 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 612 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 613 "md ${a}e60 1; md ${a}ef0 1d\0" \ 614 "guregs=setenv a e00e0; run gureg\0" \ 615 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 616 "mcmregs=setenv a e0001; run mcmreg\0" \ 617 "diuregs=md e002c000 1d\0" \ 618 "dium=mw e002c01c\0" \ 619 "diuerr=md e002c014 1\0" \ 620 "pmregs=md e00e1000 2b\0" \ 621 "lawregs=md e0000c08 4b\0" \ 622 "lbcregs=md e0005000 36\0" \ 623 "dma0regs=md e0021100 12\0" \ 624 "dma1regs=md e0021180 12\0" \ 625 "dma2regs=md e0021200 12\0" \ 626 "dma3regs=md e0021280 12\0" \ 627 PCI_ENV \ 628 PCIE_ENV \ 629 DMA_ENV 630 #else 631 #define CONFIG_EXTRA_ENV_SETTINGS \ 632 "netdev=eth0\0" \ 633 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 634 "consoledev=ttyS0\0" \ 635 "ramdiskaddr=2000000\0" \ 636 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 637 "fdtaddr=c00000\0" \ 638 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 639 "bdev=sda3\0" 640 #endif 641 642 #define CONFIG_NFSBOOTCOMMAND \ 643 "setenv bootargs root=/dev/nfs rw " \ 644 "nfsroot=$serverip:$rootpath " \ 645 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 646 "console=$consoledev,$baudrate $othbootargs;" \ 647 "tftp $loadaddr $bootfile;" \ 648 "tftp $fdtaddr $fdtfile;" \ 649 "bootm $loadaddr - $fdtaddr" 650 651 #define CONFIG_RAMBOOTCOMMAND \ 652 "setenv bootargs root=/dev/ram rw " \ 653 "console=$consoledev,$baudrate $othbootargs;" \ 654 "tftp $ramdiskaddr $ramdiskfile;" \ 655 "tftp $loadaddr $bootfile;" \ 656 "tftp $fdtaddr $fdtfile;" \ 657 "bootm $loadaddr $ramdiskaddr $fdtaddr" 658 659 #define CONFIG_BOOTCOMMAND \ 660 "setenv bootargs root=/dev/$bdev rw " \ 661 "console=$consoledev,$baudrate $othbootargs;" \ 662 "tftp $loadaddr $bootfile;" \ 663 "tftp $fdtaddr $fdtfile;" \ 664 "bootm $loadaddr - $fdtaddr" 665 666 #endif /* __CONFIG_H */ 667