1 /*
2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 /*
8  * MPC8610HPCD board configuration file
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /* High Level Configuration Options */
15 #define CONFIG_MPC8610		1	/* MPC8610 specific */
16 #define CONFIG_MPC8610HPCD	1	/* MPC8610HPCD board specific */
17 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
18 
19 #define	CONFIG_SYS_TEXT_BASE	0xfff00000
20 
21 /* video */
22 #define CONFIG_FSL_DIU_FB
23 
24 #ifdef CONFIG_FSL_DIU_FB
25 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x2c000)
26 #define CONFIG_CMD_BMP
27 #define CONFIG_VIDEO_LOGO
28 #define CONFIG_VIDEO_BMP_LOGO
29 #endif
30 
31 #ifdef RUN_DIAG
32 #define CONFIG_SYS_DIAG_ADDR		0xff800000
33 #endif
34 
35 /*
36  * virtual address to be used for temporary mappings.  There
37  * should be 128k free at this VA.
38  */
39 #define CONFIG_SYS_SCRATCH_VA	0xc0000000
40 
41 #define CONFIG_PCI1		1	/* PCI controller 1 */
42 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
43 #define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
44 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
45 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
46 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
47 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
48 
49 #define CONFIG_ENV_OVERWRITE
50 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
51 
52 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
53 #define CONFIG_HIGH_BATS	1	/* High BATs supported & enabled */
54 #define CONFIG_ALTIVEC		1
55 
56 /*
57  * L2CR setup -- make sure this is right for your board!
58  */
59 #define CONFIG_SYS_L2
60 #define L2_INIT		0
61 #define L2_ENABLE	(L2CR_L2E |0x00100000 )
62 
63 #ifndef CONFIG_SYS_CLK_FREQ
64 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
65 #endif
66 
67 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
68 #define CONFIG_MISC_INIT_R		1
69 
70 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
71 #define CONFIG_SYS_MEMTEST_END		0x00400000
72 
73 /*
74  * Base addresses -- Note these are effective addresses where the
75  * actual resources get mapped (not physical addresses)
76  */
77 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
78 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
79 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
80 
81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
82 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
83 #define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
84 
85 /* DDR Setup */
86 #define CONFIG_SYS_FSL_DDR2
87 #undef CONFIG_FSL_DDR_INTERACTIVE
88 #define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
89 #define CONFIG_DDR_SPD
90 
91 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
92 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
93 
94 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
95 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
96 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
97 #define CONFIG_VERY_BIG_RAM
98 
99 #define CONFIG_NUM_DDR_CONTROLLERS	1
100 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
101 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
102 
103 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
104 
105 /* These are used when DDR doesn't use SPD.  */
106 #define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
107 
108 #if 0 /* TODO */
109 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
110 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
111 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
112 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
113 #define CONFIG_SYS_DDR_TIMING_1	0x3935d322
114 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
115 #define CONFIG_SYS_DDR_MODE_1		0x00480432
116 #define CONFIG_SYS_DDR_MODE_2		0x00000000
117 #define CONFIG_SYS_DDR_INTERVAL	0x06180100
118 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
119 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
120 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
121 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
122 #define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
123 #define CONFIG_SYS_DDR_CONTROL2	0x04400010
124 
125 #define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
126 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
127 #define CONFIG_SYS_DDR_SBE		0x000f0000
128 
129 #endif
130 
131 #define CONFIG_ID_EEPROM
132 #define CONFIG_SYS_I2C_EEPROM_NXID
133 #define CONFIG_ID_EEPROM
134 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
135 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
136 
137 #define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
138 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
139 
140 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
141 
142 #define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
143 #define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
144 
145 #define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
146 #define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
147 #if 0 /* TODO */
148 #define CONFIG_SYS_BR2_PRELIM		0xf0000000
149 #define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
150 #endif
151 #define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
152 #define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
153 
154 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
155 #define PIXIS_BASE	0xe8000000	/* PIXIS registers */
156 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
157 #define PIXIS_VER		0x1	/* Board version at offset 1 */
158 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
159 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
160 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
161 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
162 #define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
163 #define PIXIS_VCTL		0x10	/* VELA Control Register */
164 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
165 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
166 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
167 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
168 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
169 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
170 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
171 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
172 
173 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
174 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
175 
176 #undef	CONFIG_SYS_FLASH_CHECKSUM
177 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
178 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
179 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
180 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
181 
182 #define CONFIG_FLASH_CFI_DRIVER
183 #define CONFIG_SYS_FLASH_CFI
184 #define CONFIG_SYS_FLASH_EMPTY_INFO
185 
186 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
187 #define CONFIG_SYS_RAMBOOT
188 #else
189 #undef	CONFIG_SYS_RAMBOOT
190 #endif
191 
192 #if defined(CONFIG_SYS_RAMBOOT)
193 #undef CONFIG_SPD_EEPROM
194 #define CONFIG_SYS_SDRAM_SIZE	256
195 #endif
196 
197 #undef CONFIG_CLOCKS_IN_MHZ
198 
199 #define CONFIG_SYS_INIT_RAM_LOCK	1
200 #ifndef CONFIG_SYS_INIT_RAM_LOCK
201 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
202 #else
203 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
204 #endif
205 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
206 
207 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
208 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
209 
210 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
211 #define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
212 
213 /* Serial Port */
214 #define CONFIG_CONS_INDEX	1
215 #define CONFIG_SYS_NS16550_SERIAL
216 #define CONFIG_SYS_NS16550_REG_SIZE	1
217 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
218 
219 #define CONFIG_SYS_BAUDRATE_TABLE \
220 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
221 
222 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
223 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
224 
225 /* maximum size of the flat tree (8K) */
226 #define OF_FLAT_TREE_MAX_SIZE	8192
227 
228 /*
229  * I2C
230  */
231 #define CONFIG_SYS_I2C
232 #define CONFIG_SYS_I2C_FSL
233 #define CONFIG_SYS_FSL_I2C_SPEED	400000
234 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
235 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
236 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
237 
238 /*
239  * General PCI
240  * Addresses are mapped 1-1.
241  */
242 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
243 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
244 #define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
245 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
246 #define CONFIG_SYS_PCI1_IO_BUS	0x0000000
247 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
248 #define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
249 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
250 
251 /* controller 1, Base address 0xa000 */
252 #define CONFIG_SYS_PCIE1_NAME		"ULI"
253 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
254 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
255 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
256 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
257 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
258 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
259 
260 /* controller 2, Base Address 0x9000 */
261 #define CONFIG_SYS_PCIE2_NAME		"Slot 1"
262 #define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
263 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
264 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
265 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
266 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
267 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
268 
269 #if defined(CONFIG_PCI)
270 
271 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
272 
273 #define CONFIG_CMD_REGINFO
274 
275 #define CONFIG_ULI526X
276 #ifdef CONFIG_ULI526X
277 #endif
278 
279 /************************************************************
280  * USB support
281  ************************************************************/
282 #define CONFIG_PCI_OHCI		1
283 #define CONFIG_USB_OHCI_NEW		1
284 #define CONFIG_SYS_USB_EVENT_POLL	1
285 #define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
286 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
287 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
288 
289 #if !defined(CONFIG_PCI_PNP)
290 #define PCI_ENET0_IOADDR	0xe0000000
291 #define PCI_ENET0_MEMADDR	0xe0000000
292 #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
293 #endif
294 
295 #define CONFIG_DOS_PARTITION
296 #define CONFIG_SCSI_AHCI
297 
298 #ifdef CONFIG_SCSI_AHCI
299 #define CONFIG_LIBATA
300 #define CONFIG_SATA_ULI5288
301 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
302 #define CONFIG_SYS_SCSI_MAX_LUN	1
303 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
304 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
305 #endif
306 
307 #endif	/* CONFIG_PCI */
308 
309 /*
310  * BAT0		2G	Cacheable, non-guarded
311  * 0x0000_0000	2G	DDR
312  */
313 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
314 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
315 
316 /*
317  * BAT1		1G	Cache-inhibited, guarded
318  * 0x8000_0000	256M	PCI-1 Memory
319  * 0xa000_0000	256M	PCI-Express 1 Memory
320  * 0x9000_0000	256M	PCI-Express 2 Memory
321  */
322 
323 #define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
324 			| BATL_GUARDEDSTORAGE)
325 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
326 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
327 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
328 
329 /*
330  * BAT2		16M	Cache-inhibited, guarded
331  * 0xe100_0000	1M	PCI-1 I/O
332  */
333 
334 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
335 			| BATL_GUARDEDSTORAGE)
336 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
337 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
338 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
339 
340 /*
341  * BAT3		4M	Cache-inhibited, guarded
342  * 0xe000_0000	4M	CCSR
343  */
344 
345 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
346 			| BATL_GUARDEDSTORAGE)
347 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
348 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
349 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
350 
351 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
352 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
353 				       | BATL_PP_RW | BATL_CACHEINHIBIT \
354 				       | BATL_GUARDEDSTORAGE)
355 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
356 				       | BATU_BL_1M | BATU_VS | BATU_VP)
357 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
358 				       | BATL_PP_RW | BATL_CACHEINHIBIT)
359 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
360 #endif
361 
362 /*
363  * BAT4		32M	Cache-inhibited, guarded
364  * 0xe200_0000	1M	PCI-Express 2 I/O
365  * 0xe300_0000	1M	PCI-Express 1 I/O
366  */
367 
368 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
369 			| BATL_GUARDEDSTORAGE)
370 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
371 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
372 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
373 
374 /*
375  * BAT5		128K	Cacheable, non-guarded
376  * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
377  */
378 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
379 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
380 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
381 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
382 
383 /*
384  * BAT6		256M	Cache-inhibited, guarded
385  * 0xf000_0000	256M	FLASH
386  */
387 #define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
388 			| BATL_GUARDEDSTORAGE)
389 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
390 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
391 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
392 
393 /* Map the last 1M of flash where we're running from reset */
394 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
395 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
396 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
397 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
398 				 | BATL_MEMCOHERENCE)
399 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
400 
401 /*
402  * BAT7		4M	Cache-inhibited, guarded
403  * 0xe800_0000	4M	PIXIS
404  */
405 #define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
406 			| BATL_GUARDEDSTORAGE)
407 #define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
408 #define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
409 #define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
410 
411 /*
412  * Environment
413  */
414 #ifndef CONFIG_SYS_RAMBOOT
415 #define CONFIG_ENV_IS_IN_FLASH	1
416 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
417 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 126k (one sector) for env */
418 #define CONFIG_ENV_SIZE		0x2000
419 #else
420 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
421 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
422 #define CONFIG_ENV_SIZE		0x2000
423 #endif
424 
425 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
426 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
427 
428 /*
429  * BOOTP options
430  */
431 #define CONFIG_BOOTP_BOOTFILESIZE
432 #define CONFIG_BOOTP_BOOTPATH
433 #define CONFIG_BOOTP_GATEWAY
434 #define CONFIG_BOOTP_HOSTNAME
435 
436 /*
437  * Command line configuration.
438  */
439 
440 #if defined(CONFIG_PCI)
441 #define CONFIG_CMD_PCI
442 #define CONFIG_SCSI
443 #endif
444 
445 #define CONFIG_WATCHDOG			/* watchdog enabled */
446 #define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
447 
448 /*
449  * Miscellaneous configurable options
450  */
451 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
452 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
453 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
454 
455 #if defined(CONFIG_CMD_KGDB)
456 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
457 #else
458 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
459 #endif
460 
461 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
462 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
463 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
464 
465 /*
466  * For booting Linux, the board info and command line data
467  * have to be in the first 8 MB of memory, since this is
468  * the maximum mapped by the Linux kernel during initialization.
469  */
470 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
471 #define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
472 
473 #if defined(CONFIG_CMD_KGDB)
474 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
475 #endif
476 
477 /*
478  * Environment Configuration
479  */
480 #define CONFIG_IPADDR		192.168.1.100
481 
482 #define CONFIG_HOSTNAME		unknown
483 #define CONFIG_ROOTPATH		"/opt/nfsroot"
484 #define CONFIG_BOOTFILE		"uImage"
485 #define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
486 
487 #define CONFIG_SERVERIP		192.168.1.1
488 #define CONFIG_GATEWAYIP	192.168.1.1
489 #define CONFIG_NETMASK		255.255.255.0
490 
491 /* default location for tftp and bootm */
492 #define CONFIG_LOADADDR		0x10000000
493 
494 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
495 
496 #define CONFIG_BAUDRATE	115200
497 
498 #if defined(CONFIG_PCI1)
499 #define PCI_ENV \
500  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
501 	"echo e;md ${a}e00 9\0" \
502  "pci1regs=setenv a e0008; run pcireg\0" \
503  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
504 	"pci d.w $b.0 56 1\0" \
505  "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
506 	"pci w.w $b.0 56 ffff\0"	\
507  "pci1err=setenv a e0008; run pcierr\0"	\
508  "pci1errc=setenv a e0008; run pcierrc\0"
509 #else
510 #define	PCI_ENV ""
511 #endif
512 
513 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
514 #define PCIE_ENV \
515  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
516 	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
517  "pcie1regs=setenv a e000a; run pciereg\0"	\
518  "pcie2regs=setenv a e0009; run pciereg\0"	\
519  "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
520 	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
521 	"pci d $b.0 130 1\0" \
522  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
523 	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
524 	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
525  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
526  "pcie1err=setenv a e000a; run pcieerr\0"	\
527  "pcie2err=setenv a e0009; run pcieerr\0"	\
528  "pcie1errc=setenv a e000a; run pcieerrc\0"	\
529  "pcie2errc=setenv a e0009; run pcieerrc\0"
530 #else
531 #define	PCIE_ENV ""
532 #endif
533 
534 #define DMA_ENV \
535  "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
536 	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
537  "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
538 	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
539  "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
540 	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
541  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
542 	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
543 
544 #ifdef ENV_DEBUG
545 #define	CONFIG_EXTRA_ENV_SETTINGS				\
546 "netdev=eth0\0"							\
547 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
548 "tftpflash=tftpboot $loadaddr $uboot; "				\
549 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
550 		" +$filesize; "	\
551 	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
552 		" +$filesize; "	\
553 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
554 		" $filesize; "	\
555 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
556 		" +$filesize; "	\
557 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
558 		" $filesize\0"	\
559 "consoledev=ttyS0\0"						\
560 "ramdiskaddr=0x18000000\0"					\
561 "ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
562 "fdtaddr=0x17c00000\0"						\
563 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
564 "bdev=sda3\0"					\
565 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
566 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
567 "maxcpus=1"	\
568 "eoi=mw e00400b0 0\0"						\
569 "iack=md e00400a0 1\0"						\
570 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
571 	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
572 	"md ${a}f00 5\0" \
573 "ddr1regs=setenv a e0002; run ddrreg\0" \
574 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
575 	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
576 	"md ${a}e60 1; md ${a}ef0 1d\0" \
577 "guregs=setenv a e00e0; run gureg\0" \
578 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
579 "mcmregs=setenv a e0001; run mcmreg\0" \
580 "diuregs=md e002c000 1d\0" \
581 "dium=mw e002c01c\0" \
582 "diuerr=md e002c014 1\0" \
583 "pmregs=md e00e1000 2b\0" \
584 "lawregs=md e0000c08 4b\0" \
585 "lbcregs=md e0005000 36\0" \
586 "dma0regs=md e0021100 12\0" \
587 "dma1regs=md e0021180 12\0" \
588 "dma2regs=md e0021200 12\0" \
589 "dma3regs=md e0021280 12\0" \
590  PCI_ENV \
591  PCIE_ENV \
592  DMA_ENV
593 #else
594 #define CONFIG_EXTRA_ENV_SETTINGS				\
595 	"netdev=eth0\0"						\
596 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
597 	"consoledev=ttyS0\0"					\
598 	"ramdiskaddr=0x18000000\0"				\
599 	"ramdiskfile=8610hpcd/ramdisk.uboot\0"			\
600 	"fdtaddr=0x17c00000\0"					\
601 	"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"			\
602 	"bdev=sda3\0"
603 #endif
604 
605 #define CONFIG_NFSBOOTCOMMAND					\
606  "setenv bootargs root=/dev/nfs rw "				\
607 	"nfsroot=$serverip:$rootpath "				\
608 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
609 	"console=$consoledev,$baudrate $othbootargs;"		\
610  "tftp $loadaddr $bootfile;"					\
611  "tftp $fdtaddr $fdtfile;"					\
612  "bootm $loadaddr - $fdtaddr"
613 
614 #define CONFIG_RAMBOOTCOMMAND \
615  "setenv bootargs root=/dev/ram rw "				\
616 	"console=$consoledev,$baudrate $othbootargs;"		\
617  "tftp $ramdiskaddr $ramdiskfile;"				\
618  "tftp $loadaddr $bootfile;"					\
619  "tftp $fdtaddr $fdtfile;"					\
620  "bootm $loadaddr $ramdiskaddr $fdtaddr"
621 
622 #define CONFIG_BOOTCOMMAND		\
623  "setenv bootargs root=/dev/$bdev rw "	\
624 	"console=$consoledev,$baudrate $othbootargs;"	\
625  "tftp $loadaddr $bootfile;"		\
626  "tftp $fdtaddr $fdtfile;"		\
627  "bootm $loadaddr - $fdtaddr"
628 
629 #endif	/* __CONFIG_H */
630