1 /* 2 * Copyright 2007 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 /* 10 * MPC8610HPCD board configuration file 11 * 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* High Level Configuration Options */ 18 #define CONFIG_MPC86xx 1 /* MPC86xx */ 19 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 20 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 21 #define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */ 22 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 23 24 #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ 25 26 /* video */ 27 #undef CONFIG_VIDEO 28 29 #if defined(CONFIG_VIDEO) 30 #define CONFIG_CFB_CONSOLE 31 #define CONFIG_VGA_AS_SINGLE_DEVICE 32 #endif 33 34 #ifdef RUN_DIAG 35 #define CFG_DIAG_ADDR 0xff800000 36 #endif 37 38 #define CFG_RESET_ADDRESS 0xfff00100 39 40 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 41 #define CONFIG_PCI1 1 /* PCI controler 1 */ 42 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 43 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_ENV_OVERWRITE 48 49 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 50 #undef CONFIG_DDR_DLL /* possible DLL fix needed */ 51 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 52 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 54 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 55 #define CONFIG_NUM_DDR_CONTROLLERS 1 56 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 57 58 #define CONFIG_ALTIVEC 1 59 60 /* 61 * L2CR setup -- make sure this is right for your board! 62 */ 63 #define CFG_L2 64 #define L2_INIT 0 65 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 66 67 #ifndef CONFIG_SYS_CLK_FREQ 68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 69 #endif 70 71 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 72 #define CONFIG_MISC_INIT_R 1 73 74 #undef CFG_DRAM_TEST /* memory test, takes time */ 75 #define CFG_MEMTEST_START 0x00200000 /* memtest region */ 76 #define CFG_MEMTEST_END 0x00400000 77 #define CFG_ALT_MEMTEST 78 79 /* 80 * Base addresses -- Note these are effective addresses where the 81 * actual resources get mapped (not physical addresses) 82 */ 83 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 84 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 85 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 86 87 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 88 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 89 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 90 91 #define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000) 92 93 /* 94 * DDR Setup 95 */ 96 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 97 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 98 #define CONFIG_VERY_BIG_RAM 99 100 #define MPC86xx_DDR_SDRAM_CLK_CNTL 101 102 #if defined(CONFIG_SPD_EEPROM) 103 /* 104 * Determine DDR configuration from I2C interface. 105 */ 106 #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ 107 #else 108 /* 109 * Manually set up DDR1 parameters 110 */ 111 112 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 113 114 #if 0 /* TODO */ 115 #define CFG_DDR_CS0_BNDS 0x0000000F 116 #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 117 #define CFG_DDR_TIMING_3 0x00000000 118 #define CFG_DDR_TIMING_0 0x00260802 119 #define CFG_DDR_TIMING_1 0x3935d322 120 #define CFG_DDR_TIMING_2 0x14904cc8 121 #define CFG_DDR_MODE_1 0x00480432 122 #define CFG_DDR_MODE_2 0x00000000 123 #define CFG_DDR_INTERVAL 0x06180100 124 #define CFG_DDR_DATA_INIT 0xdeadbeef 125 #define CFG_DDR_CLK_CTRL 0x03800000 126 #define CFG_DDR_OCD_CTRL 0x00000000 127 #define CFG_DDR_OCD_STATUS 0x00000000 128 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 129 #define CFG_DDR_CONTROL2 0x04400010 130 131 #define CFG_DDR_ERR_INT_EN 0x00000000 132 #define CFG_DDR_ERR_DIS 0x00000000 133 #define CFG_DDR_SBE 0x000f0000 134 /* Not used in fixed_sdram function */ 135 #define CFG_DDR_MODE 0x00000022 136 #define CFG_DDR_CS1_BNDS 0x00000000 137 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 138 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 139 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 140 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 141 #endif 142 #endif 143 144 #define CFG_ID_EEPROM 145 #ifdef CFG_ID_EEPROM 146 #define CONFIG_ID_EEPROM 147 #endif 148 #define ID_EEPROM_ADDR 0x57 149 150 151 #define CFG_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 152 #define CFG_FLASH_BASE2 0xf8000000 153 154 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} 155 156 #define CFG_BR0_PRELIM 0xf8001001 /* port size 16bit */ 157 #define CFG_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 158 159 #define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ 160 #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 161 #if 0 /* TODO */ 162 #define CFG_BR2_PRELIM 0xf0000000 163 #define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 164 #endif 165 #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ 166 #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 167 168 169 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 170 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 171 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 172 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 173 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 174 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 175 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 176 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 177 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 178 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 179 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 180 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 181 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 182 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 183 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 184 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 185 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 186 #define CFG_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ 187 188 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 189 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ 190 191 #undef CFG_FLASH_CHECKSUM 192 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 193 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 194 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 195 196 #define CFG_FLASH_CFI_DRIVER 197 #define CFG_FLASH_CFI 198 #define CFG_FLASH_EMPTY_INFO 199 200 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 201 #define CFG_RAMBOOT 202 #else 203 #undef CFG_RAMBOOT 204 #endif 205 206 #if defined(CFG_RAMBOOT) 207 #undef CONFIG_SPD_EEPROM 208 #define CFG_SDRAM_SIZE 256 209 #endif 210 211 #undef CONFIG_CLOCKS_IN_MHZ 212 213 #define CONFIG_L1_INIT_RAM 214 #define CFG_INIT_RAM_LOCK 1 215 #ifndef CFG_INIT_RAM_LOCK 216 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 217 #else 218 #define CFG_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 219 #endif 220 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ 221 222 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 223 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 224 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 225 226 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 227 #define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 228 229 /* Serial Port */ 230 #define CONFIG_CONS_INDEX 1 231 #undef CONFIG_SERIAL_SOFTWARE_FIFO 232 #define CFG_NS16550 233 #define CFG_NS16550_SERIAL 234 #define CFG_NS16550_REG_SIZE 1 235 #define CFG_NS16550_CLK get_bus_freq(0) 236 237 #define CFG_BAUDRATE_TABLE \ 238 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 239 240 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 241 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 242 243 /* Use the HUSH parser */ 244 #define CFG_HUSH_PARSER 245 #ifdef CFG_HUSH_PARSER 246 #define CFG_PROMPT_HUSH_PS2 "> " 247 #endif 248 249 /* 250 * Pass open firmware flat tree to kernel 251 */ 252 #define CONFIG_OF_LIBFDT 1 253 #define CONFIG_OF_BOARD_SETUP 1 254 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 255 256 257 /* maximum size of the flat tree (8K) */ 258 #define OF_FLAT_TREE_MAX_SIZE 8192 259 260 #define CFG_64BIT_VSPRINTF 1 261 #define CFG_64BIT_STRTOUL 1 262 263 /* 264 * I2C 265 */ 266 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 267 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 268 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 269 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 270 #define CFG_I2C_SLAVE 0x7F 271 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 272 #define CFG_I2C_OFFSET 0x3000 273 274 /* 275 * General PCI 276 * Addresses are mapped 1-1. 277 */ 278 #define CFG_PCI1_MEM_BASE 0x80000000 279 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 280 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 281 #define CFG_PCI1_IO_BASE 0x00000000 282 #define CFG_PCI1_IO_PHYS 0xe1000000 283 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ 284 285 /* PCI view of System Memory */ 286 #define CFG_PCI_MEMORY_BUS 0x00000000 287 #define CFG_PCI_MEMORY_PHYS 0x00000000 288 #define CFG_PCI_MEMORY_SIZE 0x80000000 289 290 /* For RTL8139 */ 291 #define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); }) 292 #define _IO_BASE 0x00000000 293 294 /* controller 1, Base address 0xa000 */ 295 #define CFG_PCIE1_MEM_BASE 0xa0000000 296 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 297 #define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 298 #define CFG_PCIE1_IO_BASE 0x00000000 299 #define CFG_PCIE1_IO_PHYS 0xe3000000 300 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ 301 302 /* controller 2, Base Address 0x9000 */ 303 #define CFG_PCIE2_MEM_BASE 0x90000000 304 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 305 #define CFG_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 306 #define CFG_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ 307 #define CFG_PCIE2_IO_PHYS 0xe2000000 308 #define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ 309 310 311 #if defined(CONFIG_PCI) 312 313 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 314 315 #define CONFIG_NET_MULTI 316 #define CONFIG_CMD_NET 317 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 318 #define CONFIG_CMD_REGINFO 319 320 #define CONFIG_ULI526X 321 #ifdef CONFIG_ULI526X 322 #define CONFIG_ETHADDR 00:E0:0C:00:00:01 323 #endif 324 325 /************************************************************ 326 * USB support 327 ************************************************************/ 328 #define CONFIG_PCI_OHCI 1 329 #define CONFIG_USB_OHCI_NEW 1 330 #define CONFIG_USB_KEYBOARD 1 331 #define CFG_DEVICE_DEREGISTER 332 #define CFG_USB_EVENT_POLL 1 333 #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" 334 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 335 #define CFG_OHCI_SWAP_REG_ACCESS 1 336 337 #if !defined(CONFIG_PCI_PNP) 338 #define PCI_ENET0_IOADDR 0xe0000000 339 #define PCI_ENET0_MEMADDR 0xe0000000 340 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 341 #endif 342 343 #define CONFIG_DOS_PARTITION 344 #define CONFIG_SCSI_AHCI 345 346 #ifdef CONFIG_SCSI_AHCI 347 #define CONFIG_SATA_ULI5288 348 #define CFG_SCSI_MAX_SCSI_ID 4 349 #define CFG_SCSI_MAX_LUN 1 350 #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 351 #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 352 #endif 353 354 #endif /* CONFIG_PCI */ 355 356 /* 357 * BAT0 2G Cacheable, non-guarded 358 * 0x0000_0000 2G DDR 359 */ 360 #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 361 #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 362 #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) 363 #define CFG_IBAT0U CFG_DBAT0U 364 365 /* 366 * BAT1 1G Cache-inhibited, guarded 367 * 0x8000_0000 256M PCI-1 Memory 368 * 0xa000_0000 256M PCI-Express 1 Memory 369 * 0x9000_0000 256M PCI-Express 2 Memory 370 */ 371 372 #define CFG_DBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 373 | BATL_GUARDEDSTORAGE) 374 #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) 375 #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 376 #define CFG_IBAT1U CFG_DBAT1U 377 378 /* 379 * BAT2 16M Cache-inhibited, guarded 380 * 0xe100_0000 1M PCI-1 I/O 381 */ 382 383 #define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 384 | BATL_GUARDEDSTORAGE) 385 #define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP) 386 #define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 387 #define CFG_IBAT2U CFG_DBAT2U 388 389 /* 390 * BAT3 32M Cache-inhibited, guarded 391 * 0xe200_0000 1M PCI-Express 2 I/O 392 * 0xe300_0000 1M PCI-Express 1 I/O 393 */ 394 395 #define CFG_DBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 396 | BATL_GUARDEDSTORAGE) 397 #define CFG_DBAT3U (CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 398 #define CFG_IBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 399 #define CFG_IBAT3U CFG_DBAT3U 400 401 /* 402 * BAT4 4M Cache-inhibited, guarded 403 * 0xe000_0000 4M CCSR 404 */ 405 #define CFG_DBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 406 | BATL_GUARDEDSTORAGE) 407 #define CFG_DBAT4U (CFG_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 408 #define CFG_IBAT4L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 409 #define CFG_IBAT4U CFG_DBAT4U 410 411 /* 412 * BAT5 128K Cacheable, non-guarded 413 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 414 */ 415 #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 416 #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 417 #define CFG_IBAT5L CFG_DBAT5L 418 #define CFG_IBAT5U CFG_DBAT5U 419 420 /* 421 * BAT6 256M Cache-inhibited, guarded 422 * 0xf000_0000 256M FLASH 423 */ 424 #define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 425 | BATL_GUARDEDSTORAGE) 426 #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 427 #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 428 #define CFG_IBAT6U CFG_DBAT6U 429 430 /* 431 * BAT7 4M Cache-inhibited, guarded 432 * 0xe800_0000 4M PIXIS 433 */ 434 #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 435 | BATL_GUARDEDSTORAGE) 436 #define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 437 #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 438 #define CFG_IBAT7U CFG_DBAT7U 439 440 441 /* 442 * Environment 443 */ 444 #ifndef CFG_RAMBOOT 445 #define CFG_ENV_IS_IN_FLASH 1 446 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 447 #define CFG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 448 #define CFG_ENV_SIZE 0x2000 449 #else 450 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 451 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 452 #define CFG_ENV_SIZE 0x2000 453 #endif 454 455 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 456 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 457 458 459 /* 460 * BOOTP options 461 */ 462 #define CONFIG_BOOTP_BOOTFILESIZE 463 #define CONFIG_BOOTP_BOOTPATH 464 #define CONFIG_BOOTP_GATEWAY 465 #define CONFIG_BOOTP_HOSTNAME 466 467 468 /* 469 * Command line configuration. 470 */ 471 #include <config_cmd_default.h> 472 473 #define CONFIG_CMD_PING 474 #define CONFIG_CMD_I2C 475 #define CONFIG_CMD_MII 476 477 #if defined(CFG_RAMBOOT) 478 #undef CONFIG_CMD_ENV 479 #endif 480 481 #if defined(CONFIG_PCI) 482 #define CONFIG_CMD_PCI 483 #define CONFIG_CMD_SCSI 484 #define CONFIG_CMD_EXT2 485 #define CONFIG_CMD_USB 486 #endif 487 488 489 #undef CONFIG_WATCHDOG /* watchdog disabled */ 490 491 /*DIU Configuration*/ 492 #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ 493 494 /* 495 * Miscellaneous configurable options 496 */ 497 #define CFG_LONGHELP /* undef to save memory */ 498 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 499 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 500 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 501 502 #if defined(CONFIG_CMD_KGDB) 503 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 504 #else 505 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 506 #endif 507 508 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 509 #define CFG_MAXARGS 16 /* max number of command args */ 510 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 511 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 512 513 /* 514 * For booting Linux, the board info and command line data 515 * have to be in the first 8 MB of memory, since this is 516 * the maximum mapped by the Linux kernel during initialization. 517 */ 518 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 519 520 /* 521 * Internal Definitions 522 * 523 * Boot Flags 524 */ 525 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 526 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 527 528 #if defined(CONFIG_CMD_KGDB) 529 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 530 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 531 #endif 532 533 /* 534 * Environment Configuration 535 */ 536 #define CONFIG_IPADDR 192.168.1.100 537 538 #define CONFIG_HOSTNAME unknown 539 #define CONFIG_ROOTPATH /opt/nfsroot 540 #define CONFIG_BOOTFILE uImage 541 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 542 543 #define CONFIG_SERVERIP 192.168.1.1 544 #define CONFIG_GATEWAYIP 192.168.1.1 545 #define CONFIG_NETMASK 255.255.255.0 546 547 /* default location for tftp and bootm */ 548 #define CONFIG_LOADADDR 1000000 549 550 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 551 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 552 553 #define CONFIG_BAUDRATE 115200 554 555 #if defined(CONFIG_PCI1) 556 #define PCI_ENV \ 557 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 558 "echo e;md ${a}e00 9\0" \ 559 "pci1regs=setenv a e0008; run pcireg\0" \ 560 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 561 "pci d.w $b.0 56 1\0" \ 562 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 563 "pci w.w $b.0 56 ffff\0" \ 564 "pci1err=setenv a e0008; run pcierr\0" \ 565 "pci1errc=setenv a e0008; run pcierrc\0" 566 #else 567 #define PCI_ENV "" 568 #endif 569 570 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 571 #define PCIE_ENV \ 572 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 573 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 574 "pcie1regs=setenv a e000a; run pciereg\0" \ 575 "pcie2regs=setenv a e0009; run pciereg\0" \ 576 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 577 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 578 "pci d $b.0 130 1\0" \ 579 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 580 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 581 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 582 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 583 "pcie1err=setenv a e000a; run pcieerr\0" \ 584 "pcie2err=setenv a e0009; run pcieerr\0" \ 585 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 586 "pcie2errc=setenv a e0009; run pcieerrc\0" 587 #else 588 #define PCIE_ENV "" 589 #endif 590 591 #define DMA_ENV \ 592 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 593 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 594 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 595 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 596 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 597 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 598 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 599 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 600 601 #ifdef ENV_DEBUG 602 #define CONFIG_EXTRA_ENV_SETTINGS \ 603 "netdev=eth0\0" \ 604 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 605 "tftpflash=tftpboot $loadaddr $uboot; " \ 606 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 607 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 608 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 609 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 610 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 611 "consoledev=ttyS0\0" \ 612 "ramdiskaddr=2000000\0" \ 613 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 614 "fdtaddr=c00000\0" \ 615 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 616 "bdev=sda3\0" \ 617 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 618 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 619 "maxcpus=1" \ 620 "eoi=mw e00400b0 0\0" \ 621 "iack=md e00400a0 1\0" \ 622 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 623 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 624 "md ${a}f00 5\0" \ 625 "ddr1regs=setenv a e0002; run ddrreg\0" \ 626 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 627 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 628 "md ${a}e60 1; md ${a}ef0 1d\0" \ 629 "guregs=setenv a e00e0; run gureg\0" \ 630 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 631 "mcmregs=setenv a e0001; run mcmreg\0" \ 632 "diuregs=md e002c000 1d\0" \ 633 "dium=mw e002c01c\0" \ 634 "diuerr=md e002c014 1\0" \ 635 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \ 636 "monitor=0-DVI\0" \ 637 "pmregs=md e00e1000 2b\0" \ 638 "lawregs=md e0000c08 4b\0" \ 639 "lbcregs=md e0005000 36\0" \ 640 "dma0regs=md e0021100 12\0" \ 641 "dma1regs=md e0021180 12\0" \ 642 "dma2regs=md e0021200 12\0" \ 643 "dma3regs=md e0021280 12\0" \ 644 PCI_ENV \ 645 PCIE_ENV \ 646 DMA_ENV 647 #else 648 #define CONFIG_EXTRA_ENV_SETTINGS \ 649 "netdev=eth0\0" \ 650 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 651 "consoledev=ttyS0\0" \ 652 "ramdiskaddr=2000000\0" \ 653 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 654 "fdtaddr=c00000\0" \ 655 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 656 "bdev=sda3\0" \ 657 "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ 658 "monitor=0-DVI\0" 659 #endif 660 661 #define CONFIG_NFSBOOTCOMMAND \ 662 "setenv bootargs root=/dev/nfs rw " \ 663 "nfsroot=$serverip:$rootpath " \ 664 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 665 "console=$consoledev,$baudrate $othbootargs;" \ 666 "tftp $loadaddr $bootfile;" \ 667 "tftp $fdtaddr $fdtfile;" \ 668 "bootm $loadaddr - $fdtaddr" 669 670 #define CONFIG_RAMBOOTCOMMAND \ 671 "setenv bootargs root=/dev/ram rw " \ 672 "console=$consoledev,$baudrate $othbootargs;" \ 673 "tftp $ramdiskaddr $ramdiskfile;" \ 674 "tftp $loadaddr $bootfile;" \ 675 "tftp $fdtaddr $fdtfile;" \ 676 "bootm $loadaddr $ramdiskaddr $fdtaddr" 677 678 #define CONFIG_BOOTCOMMAND \ 679 "setenv bootargs root=/dev/$bdev rw " \ 680 "console=$consoledev,$baudrate $othbootargs;" \ 681 "tftp $loadaddr $bootfile;" \ 682 "tftp $fdtaddr $fdtfile;" \ 683 "bootm $loadaddr - $fdtaddr" 684 685 #endif /* __CONFIG_H */ 686